Fairchild NC7WZ240L8X Tinylogic. uhs dual inverting buffer with 3-state output Datasheet

Revised January 2005
NC7WZ240
TinyLogic UHS Dual Inverting Buffer
with 3-STATE Outputs
General Description
Features
The NC7WZ240 is a Dual Inverting Buffer with independent active LOW enables for the 3-STATE outputs. The
Ultra High Speed device is fabricated with advanced
CMOS technology to achieve superior switching performance with high output drive while maintaining low static
power dissipation over a broad VCC operating range. The
device is specified to operate over the 1.65V to 5.5V VCC
operating range. The inputs and outputs are high impedance when VCC is 0V. Inputs tolerate voltages up to 5.5V
independent of VCC operating range. Outputs tolerate voltages above VCC when in the 3-STATE condition.
■ Space saving US8 surface mount package
■ MicroPak Pb-Free leadless package
■ Ultra High Speed; tPD 2.3 ns typ into 50 pF at 5V VCC
■ High Output Drive; ±24 mA at 3V VCC
■ Broad VCC Operating Range: 1.65V to 5.5V
■ Matches the performance of LCX when operated at
3.3V VCC
■ Power down high impedance inputs/outputs
■ Overvoltage tolerant inputs facilitate 5V to 3V translation
■ Outputs are overvoltage tolerant in 3-STATE mode
■ Patented noise/EMI reduction circuitry implemented
Ordering Code:
Product
Order
Package
Code
Number
Number
Top Mark
NC7WZ240K8X MAB08A
NC7WZ240L8X
MAC08A
WZ40
U7
Package Description
Supplied As
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
5k Units on Tape and Reel
Pb-Free package per JEDEC J-STD-020B.
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500398
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NC7WZ240 TinyLogic UHS Dual Inverting Buffer with 3-STATE Outputs
March 2001
NC7WZ240
Logic Symbol
Connection Diagrams
IEEE/IEC
Pin Assignments for US8
Pin Descriptions
Pin Names
Description
OEn
Enable Inputs for 3-STATE Outputs
(Top View)
An
Inputs
Yn
3-STATE Outputs
Pin One Orientation Diagram
Function Table
Inputs
Output
OE
An
Yn
L
L
H
L
H
L
H
L
Z
H
H = HIGH Logic Level
H
L = LOW Logic Level
Z
AAA represents Product Code Top Mark - see ordering code
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
Z = 3-STATE
Pad Assignment for MicroPak
(Top Through View)
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2
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC)
−0.5V to +7.0V
DC Input Voltage (VIN) (Note 2)
−0.5V to +7.0V
Supply Voltage Operating (VCC)
DC Output Voltage (VOUT)
−0.5V to +7.0V
Supply Voltage Data Retention (VCC)
DC Input Diode Current (IIK)
1.65V to 5.5V
1.5V to 5.5V
Input Voltage (VIN)
@VIN < 0V
−50 mA
DC Output Diode Current (IOK)
@VOUT < 0V
−50 mA
± 50 mA
DC Output Source/Sink Current (IOUT )
+150°C
Junction Lead Temperature (TL)
+260°C
(Soldering, 10 seconds)
Power Dissipation (PD) @ +85°C
0V to VCC
0V to 5.5V
−40°C to +85°C
Input Rise and Fall Time (tr, tf)
−65°C to +150°C
Storage Temperature Range (TSTG)
Junction Lead Temperature under Bias (TJ)
Active State
3-STATE
Operating Temperature (TA)
± 100 mA
DC VCC/Ground Current (ICC/IGND)
0V to 5.5V
Output Voltage (VOUT)
VCC @ 1.8V, 0.15V, 2.5V ± 0.2V
0 ns/V to 20 ns/V
VCC @ 3.3V ± 0.3V
0 ns/V to 10 ns/V
VCC @ 5.0V ± 0.5V
0 ns/V to 5 ns/V
Thermal Resistance (θJA)
250°C/W
250 mW
Note 1: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications.
Note 2: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
VIH
Parameter
HIGH Level Input Voltage
(V)
LOW Level Input Voltage
VOH
HIGH Level Output Voltage
Min
Typ
LOW Level Output Voltage
IIN
Input Leakage Current
IOZ
3-STATE Output Leakage
IOFF
Power Off Leakage Current
ICC
Quiescent Supply Current
Min
Max
0.75 VCC
1.65 to 1.95
0.25 VCC
0.25 VCC
0.3 VCC
0.3 VCC
1.65
1.55
1.65
1.55
Units
Conditions
V
0.7 VCC
0.7 VCC
2.3 to 5.5
VOL
TA = −40°C to +85°C
Max
1.65 to 1.95 0.75 VCC
2.3 to 5.5
VIL
TA = +25°C
VCC
V
VIN = VIH IOH = −100 µA
2.3
2.2
2.3
2.2
3.0
2.9
3.0
2.9
4.5
4.4
4.5
4.4
1.65
1.29
1.52
1.29
IOH = −4 mA
2.3
1.9
2.15
1.9
VIN = VIH IOH = −8 mA
3.0
2.4
2.80
2.4
3.0
2.3
2.68
2.3
4.5
3.8
4.20
V
V
or VIL
or VIL
IOH = −16 mA
IOH = −24 mA
IOH = −32 mA
3.8
1.65
0.0
0.10
0.10
VIN = VIH IOL = 100 µA
2.3
0.0
0.10
0.10
3.0
0.0
0.10
0.10
4.5
0.0
0.10
0.10
1.65
0.08
0.24
0.24
IOL = 4 mA
2.3
0.10
0.3
0.3
IOL = 8 mA
3.0
0.15
0.4
0.4
3.0
0.22
0.55
0.55
4.5
0.22
0.55
0.55
0 to 5.5
±0.1
±1
µA
VIN = 5.5V, GND
1.65 to 5.5
±0.5
±5
µA
VIN = VIH or VIL
0.0
1
10
µA
VIN or VOUT = 5.5V
1.65 to 5.5
1
10
µA
VIN = 5.5V, GND
V
V
or VIL
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
0 ≤ VOUT ≤ 5.5V
3
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NC7WZ240
Absolute Maximum Ratings(Note 1)
NC7WZ240
Noise Characteristics
Symbol
TA = + 25°C
VCC
Parameter
Units
Conditions
VOLP (Note 4) Quiet Output Maximum Dynamic VOL
5.0
1.0
V
CL = 50 pF
VOLV (Note 4) Quiet Output Minimum Dynamic VOL
5.0
1.0
V
CL = 50 pF
VOHV (Note 4) Quiet Output Minimum Dynamic VOH
5.0
4.0
V
CL = 50 pF
VIHD (Note 4)
Minimum HIGH Level Dynamic Input Voltage
5.0
3.5
V
CL = 50 pF
VILD (Note 4)
Maximum LOW Level Dynamic Input Voltage
5.0
1.5
V
CL = 50 pF
(V)
Typ
Max
Note 4: Parameter guaranteed by design.
AC Electrical Characteristics
Symbol
Parameter
TA = +25°C
VCC
(V)
Min
Typ
TA = −40°C to +85°C
Max
Min
Max
tPLH,
Propagation Delay
1.8 ± 0.15
2.0
12.0
2.0
13.0
tPHL
An to Yn
2.5 ± 0.2
1.0
7.5
1.0
8.0
3.3 ± 0.3
0.8
5.2
0.8
5.5
5.0 ± 0.5
0.5
4.5
0.5
4.8
tPLH,
Propagation Delay
3.3 ± 0.3
1.2
5.7
1.2
6.0
tPHL
An to Yn
5.0 ± 0.5
0.8
5.0
0.8
5.3
tOSLH,
Output to Output Skew
3.3 ± 0.3
1.0
1.0
tOSHL
(Note 5)
5.0 ± 0.5
0.8
0.8
Units
Conditions
Figure
Number
CL = 15 pF
ns
RD = 1 MΩ
S1= Open
CL = 50 pF
ns
RD = 500Ω
Figures
1, 3
Figures
1, 3
S1= Open
CL = 50 pF
ns
RD = 500Ω
Figures
1, 3
S1= Open
tPZL,
Output Enable Time
tPZH
1.8 ± 0.15
3.0
14.0
3.0
15.0
CL = 50 pF
2.5 ± 0.2
1.8
8.5
1.8
9.0
RD, RU = 500 Ω
3.3 ± 0.3
1.2
6.2
1.2
6.5
5.5 ± 0.5
0.8
5.5
0.8
5.8
S1 = VI for tPZL
1.8 ± 0.15
2.5
12.0
2.5
13.0
CL = 50 pF
ns
S1 = GND for tPZH
Figures
1, 3
VI = 2 x VCC
tPLZ,
Output Disable Time
tPHZ
2.5 ± 0.2
1.5
8.0
1.5
8.5
3.3 ± 0.3
0.8
5.7
0.8
6.0
5.0 ± 0.5
0.3
4.7
0.3
5.0
RD, RU = 500 Ω
ns
S1 = GND for tPZH
S1 = VI for tPZL
Figures
1, 3
VI = 2 x VCC
CIN
Input Capacitance
0
2.5
COUT
Output Capacitance
5.0
4
CPD
Power Dissipation Capacitance
3.3
10
5.0
12
pF
pF
(Note 6)
Figure 2
Note 5: Parameter guaranteed by design. tOSLH = |tPLHmax − tPLHmin|; tOSHL = |tPHLmax − tPHLmin|.
Note 6: C PD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD ) at no output
loading and operating at 50% duty cycle. (See Figure 2.) CPD is related to ICCD dynamic operating current by the expression:
ICCD = (CPD)(VCC)(fIN) + (ICCstatic).
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4
NC7WZ240
AC Loading and Waveforms
CL includes load and stray capacitance
Input PRR = 1.0 MHz; tw = 500 ns
FIGURE 1. AC Test Circuit
Input = AC Waveform; tr = tf = 1.8 ns;
PRR = 10 MHz; Duty Cycle = 50%
FIGURE 2. ICCD Test Circuit
FIGURE 3. AC Waveforms
5
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NC7WZ240
Tape and Reel Specification
Tape Format for US8
Package
Designator
K8X
Tape
Number
Cavity
Section
Cavities
Status
Cover Tape
Status
Leader (Start End)
125 (typ)
Empty
Sealed
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
Cover Tape
TAPE DIMENSIONS inches (millimeters)
Tape Format for MicroPak
Package
Designator
L8X
Tape
Number
Cavity
Section
Cavities
Status
Status
Leader (Start End)
125 (typ)
Empty
Sealed
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
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6
NC7WZ240
Tape and Reel Specification
(Continued)
REEL DIMENSIONS inches (millimeters)
Tape
Size
8 mm
A
B
C
D
N
W1
W2
W3
7.0
0.059
0.512
0.795
2.165
0.331 + 0.059/−0.000
0.567
W1 + 0.078/−0.039
(177.8)
(1.50)
(13.00)
(20.20)
(55.00)
(8.40 + 1.50/−0.00)
(14.40)
(W1 + 2.00/−1.00)
7
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NC7WZ240
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
Package Number MAB08A
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8
NC7WZ240 TinyLogic UHS Dual Inverting Buffer with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
Package Number MAC08A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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9
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