Fairchild NDS335N N-channel logic level enhancement mode field effect transistor Datasheet

July 1996
NDS335N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These N -Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and other battery powered circuits where fast switching,
and low in-line power loss are needed in a very small outline
surface mount package.
1.7 A, 20 V. RDS(ON) = 0.14 Ω @ VGS= 2.7 V
RDS(ON) = 0.11 Ω @ VGS= 4.5 V.
Industry standard outline SOT-23 surface mount package
using poprietary SuperSOTTM-3 design for superior thermal
and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
________________________________________________________________________________
D
S
G
Absolute Maximum Ratings
T A = 25°C unless otherwise noted
Symbol
Parameter
NDS335N
Units
VDSS
Drain-Source Voltage
20
V
VGSS
Gate-Source Voltage - Continuous
8
V
ID
Maximum Drain Current - Continuous (Note 1a)
1.7
A
- Pulsed
PD
Maximum Power Dissipation
10
(Note 1a)
(Note 1b)
TJ,TSTG
Operating and Storage Temperature Range
0.5
W
0.46
-55 to 150
°C
250
°C/W
75
°C/W
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
(Note 1a)
© 1997 Fairchild Semiconductor Corporation
(Note 1)
NDS335 Rev.C
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
IDSS
Zero Gate Voltage Drain Current
VDS = 16 V, VGS= 0 V
20
V
TJ =125°C
1
µA
10
µA
IGSSF
Gate - Body Leakage, Forward
VGS = 8 V, VDS = 0 V
100
nA
IGSSR
Gate - Body Leakage, Reverse
VGS = -8 V, VDS = 0 V
-100
nA
1
V
ON CHARACTERISTICS (Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
RDS(ON)
Static Drain-Source On-Resistance
VGS = 2.7 V, ID = 1.7 A
0.5
TJ =125°C
0.3
TJ =125°C
VGS = 4.5 V, ID = 1.7 A
ID(ON)
gFS
On-State Drain Current
Forward Transconductance
VGS = 2.7 V, VDS = 5 V
5
VGS = 4.5 V, VDS = 5 V
10
VDS = 5 V, ID = 1.7 A,
0.7
0.5
0.8
0.084
0.14
0.13
0.25
0.065
0.11
Ω
A
6
S
240
pF
130
pF
40
pF
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
SWITCHING CHARACTERISTICS (Note 2)
td(on)
Turn - On Delay Time
tr
Turn - On Rise Time
td(off)
Turn - Off Delay Time
tf
Turn - Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 5 V, ID = 1 A,
VGS = 4.5 V, RGen = 6 Ω
VDS = 10 V, ID = 1.7 A,
VGS = 4.5 V
8
20
ns
29
45
ns
28
40
ns
8
20
ns
6.4
9
nC
0.5
nC
2
nC
NDS335 Rev.C
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.42
A
10
A
1.2
V
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Maximum Continuous Drain-Source Diode Forward Current
ISM
Maximum Pulsed Drain-Source Diode Forward Current
VSD
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 0.42 A (Note 2)
0.8
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
PD (t ) =
T J−TA
R θJ A(t )
=
T J−TA
R θJ C+RθCA(t )
= I 2D (t ) × RDS(ON )
TJ
Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper.
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.
1a
1b
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS335 Rev.C
Typical Electrical Characteristics
2.5
2.0
R DS(on), NORMALIZED
I D , DRAIN-SOURCE CURRENT (A)
VGS =4.5V
3.0
4
2.7
3
2
1.5
1
0
0
0.4
0.8
1.2
1.6
DRAIN-SOURCE ON-RESISTANCE
1.75
5
1.5
VGS = 2.0V
1.25
2.5
3.0
0
1
2
VDS , DRAIN-SOURCE VOLTAGE (V)
I
R DS(on) , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
1.6
VGS = 2.7V
1.4
1.2
1
0.8
3
4
5
, DRAIN CURRENT (A)
VGS = 2.7 V
0
25
50
75
100
125
TJ = 125°C
1.5
1.25
25°C
1
-55°C
0.75
0.5
-25
150
0
1
2
25°C
125°C
4
3
2
1
0.5
1
V
GS
1.5
2
2.5
, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
3
GATE-SOURCE THRESHOLD VOLTAGE
T = -55°C
J
V DS = 5.0V
4
5
Figure 4. On-Resistance Variation
with Drain Current and Temperature.
Figure 3. On-Resistance Variation
with Temperature.
5
3
ID , DRAIN CURRENT (A)
TJ , JUNCTION TEMPERATURE (°C)
Vth , NORMALIZED
R DS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
I D = 1.7A
0.6
-50
ID , DRAIN CURRENT (A)
D
1.75
1.8
0
4.5
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage.
Figure 1. On-Region Characteristics.
0
3.5
0.75
0.5
2
2.7
1
1.3
1.2
V DS= V GS
I D = 250µA
1.1
1
0.9
0.8
0.7
0.6
0.5
-50
-25
0
25
50
75
100
125
150
TJ , JUNCTION TEMPERATURE (°C)
Figure 6. Gate Threshold Variation
with Temperature.
NDS335 Rev.C
1
1.12
I , REVERSE DRAIN CURRENT (A)
I = 250µA
D
1.08
1.04
1
0.96
0.92
-50
0.1
TJ = 125°C
0
J
25
50
75
100
125
-55°C
0.001
0
150
SD
0.6
0.8
1
1.2
, BODY DIODE FORWARD VOLTAGE (V)
Figure 8. Body Diode Forward Voltage Variation
with Source Current and
Temperature.
5
VGS , GATE-SOURCE VOLTAGE (V)
400
C iss
200
100
C oss
50
10
0.1
0.4
V
600
20
0.2
, JUNCTION TEMPERATURE (°C)
Figure 7. Breakdown Voltage Variation with
Temperature.
CAPACITANCE (pF)
25°C
0.01
0.0001
-25
T
f = 1 MHz
V GS = 0V
C rss
0.5
DS
1
2
5
10
10V
15V
3
2
1
20
0
2
4
Q
, DRAIN TO SOURCE VOLTAGE (V)
Figure 9. Capacitance Characteristics.
6
t d(on)
t off
tr
t d(off)
tf
90%
90%
V OUT
D
VOUT
10%
10%
INVERTED
DUT
G
8
, GATE CHARGE (nC)
t on
RL
V IN
g
Figure 10. Gate Charge Characteristics.
VDD
R GEN
VDS = 5V
I D = 1.7A
4
0
0.2
V
VGS
V GS = 0V
S
BV DSS , NORMALIZED
DRAIN-SOURCE BREAKDOWN VOLTAGE
Typical Electrical Characteristics (continued)
90%
V IN
50%
50%
S
10%
PULSE WIDTH
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
NDS335 Rev.C
Typical Electrical Characteristics (continued)
20
VDS = 5.0V
25°C
8
6
125°C
4
2
3
RD
1
2
3
4
5
N)
LI
10
0.3
10s
0.1
0.01
0.1
0.2
0.5
V
D
DS
0.8
0.6
1a
1b
0.4
4.5"x5" FR-4 Board
o
TA = 25 C
Still Air
0.2
0
0
0.1
0.2
0.3
2
5
10
20
30
2.4
2
1a
1.6
1b
4.5"x5" FR-4 Board
o
TA = 25 C
Still Air
VGS = 2.7V
1.2
0.8
0
0.4
0.1
2oz COPPER MOUNTING PAD AREA (in2 )
Figue 15. SuperSOTTM _ 3 Maximum
Steady-State Power Dissipation versus
Mounting Pad Area.
1
, DRAIN-SOURCE VOLTAGE (V)
Figure 14. Maximum Safe Operating Area
ID , STEADY-STATE DRAIN CURRENT (A)
STEADY-STATE POWER DISSIPATION (W)
1
s
DC
VGS = 2.7V
SINGLE PULSE
RθJA =See Note1b
TA = 25°C
I , DRAIN CURRENT (A)
Figure 13. Transconductance Variation with Drain
Current and Temperature.
0m
1s
FS
g
0
S(O
T
MI
1
0.03
0
10
0u
s
10m
s
10
T J = -55°C
10
I D , DRAIN CURRENT (A)
, TRANSCONDUCTANCE (SIEMENS)
12
0.2
0.3
0.4
2
2oz COPPER MOUNTING PAD AREA (in )
Figure 16. Maximum Steady-State Drain
Current versus Copper Mounting Pad Area.
Copper
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
0.5
0.2
D = 0.5
R θJA (t) = r(t) * R θJA
R θJA = See Note 1b
0.2
0.1
0.1
0.05
0.05
0.02
0.01
0.005
P(pk)
0.02
t1
0.01
t2
TJ - TA = P * R θJA (t)
Single Pulse
Duty Cycle, D = t1 /t2
0.002
0.001
0.0001
0.001
0.01
0.1
t 1 , TIME (sec)
1
10
100
300
Figure 17. Transient Thermal Response Curve.
Note : Characterization performed using the conditions described in note 1b. Transient thermal
change depending on the circuit board design.
response will
NDS335 Rev.C