Sample & Buy Product Folder Support & Community Tools & Software Technical Documents NA555, NE555, SA555, SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 xx555 Precision Timers 1 Features 3 Description • • • • These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. 1 • Timing From Microseconds to Hours Astable or Monostable Operation Adjustable Duty Cycle TTL-Compatible Output Can Sink or Source Up to 200 mA On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters. The threshold and trigger levels normally are twothirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flipflop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. 2 Applications • • • Fingerprint Biometrics Iris Biometrics RFID Reader The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs. Device Information(1) PART NUMBER xx555 PACKAGE BODY SIZE (NOM) PDIP (8) 9.81 mm × 6.35 mm SOP (8) 6.20 mm × 5.30 mm TSSOP (8) 3.00 mm × 4.40 mm SOIC (8) 4.90 mm × 3.91 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Simplified Schematic VCC 8 6 THRES 2 TRIG CONT 5 Î Î Î Î Î Î Î Î Î RESET 4 Î Î Î Î Î Î Î R1 R 3 OUT 1 S 7 DISCH 1 GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. NA555, NE555, SA555, SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 4 4 4 5 6 7 Absolute Maximum Ratings ..................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Electrical Characteristics........................................... Operating Characteristics.......................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 8.1 8.2 8.3 8.4 9 Overview ................................................................... 9 Functional Block Diagram ......................................... 9 Feature Description................................................... 9 Device Functional Modes........................................ 12 Applications and Implementation ...................... 13 9.1 Application Information............................................ 13 9.2 Typical Applications ................................................ 13 10 Power Supply Recommendations ..................... 18 11 Device and Documentation Support ................. 19 11.1 11.2 11.3 11.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 12 Mechanical, Packaging, and Orderable Information ........................................................... 19 5 Revision History Changes from Revision H (June 2010) to Revision I Page • Updated document to new TI enhanced data sheet format. .................................................................................................. 1 • Deleted Ordering Information table. ...................................................................................................................................... 1 • Added Military Disclaimer to Features list. ............................................................................................................................. 1 • Added Applications. ................................................................................................................................................................ 1 • Added Device Information table. ............................................................................................................................................ 1 • Moved Tstg to Handling Ratings table. .................................................................................................................................... 4 • Added DISCH switch on-state voltage parameter. ................................................................................................................. 5 • Added Device and Documentation Support section............................................................................................................. 19 • Added ESD warning. ............................................................................................................................................................ 19 • Added Mechanical, Packaging, and Orderable Information section..................................................................................... 19 2 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 NA555, NE555, SA555, SE555 www.ti.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 6 Pin Configuration and Functions NA555...D OR P PACKAGE NE555...D, P, PS, OR PW PACKAGE SA555...D OR P PACKAGE SE555...D, JG, OR P PACKAGE (TOP VIEW) 1 8 2 7 3 6 4 5 VCC DISCH THRES CONT NC GND NC VCC NC NC TRIG NC OUT NC 4 3 2 1 20 19 18 5 17 6 16 7 15 14 9 10 11 12 13 8 NC DISCH NC THRES NC NC RESET NC CONT NC GND TRIG OUT RESET SE555...FK PACKAGE (TOP VIEW) NC – No internal connection Pin Functions PIN NAME D, P, PS, PW, JG FK I/O DESCRIPTION NO. CONT 5 12 I/O Controls comparator thresholds, Outputs 2/3 VCC, allows bypass capacitor connection DISCH 7 17 O Open collector output to discharge timing capacitor GND 1 2 – Ground 1, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 19 – No internal connection NC OUT 3 7 O High current timer output signal RESET 4 10 I Active low reset input forces output and discharge low. THRES 6 15 I End of timing input. THRES > CONT sets output low and discharge low TRIG 2 5 I Start of timing input. TRIG < ½ CONT sets output high and discharge open VCC 8 20 – Input supply voltage, 4.5 V to 16 V. (SE555 maximum is 18 V) Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 3 NA555, NE555, SA555, SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN VCC Supply voltage (2) VI Input voltage IO Output current θJA 18 CONT, RESET, THRES, TRIG Package thermal impedance (3) (4) θJC Package thermal impedance (5) (6) TJ Operating virtual junction temperature (1) (2) (3) (4) (5) (6) MAX UNIT V VCC V ±225 mA D package 97 P package 85 PS package 95 PW package 149 FK package 5.61 JG package 14.5 °C/W °C/W 150 °C Case temperature for 60 s FK package 260 °C Lead temperature 1,6 mm (1/16 in) from case for 60 s JG package 300 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. The package thermal impedance is calculated in accordance with JESD 51-7. Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) - TC) / θJC. Operating at the absolute maximum TJ of 150°C can affect reliability. The package thermal impedance is calculated in accordance with MIL-STD-883. 7.2 Handling Ratings PARAMETER Tstg DEFINITION Storage temperature range MIN MAX UNIT –65 150 °C UNIT 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC Supply voltage VI Input voltage IO Output current TA 4 Operating free-air temperature Submit Documentation Feedback MIN MAX NA555, NE555, SA555 4.5 16 SE555 4.5 18 CONT, RESET, THRES, and TRIG V VCC V ±200 mA NA555 –40 105 NE555 0 70 SA555 –40 85 SE555 –55 125 °C Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 NA555, NE555, SA555, SE555 www.ti.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 7.4 Electrical Characteristics VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted) PARAMETER THRES voltage level TEST CONDITIONS MIN TYP MAX MIN TYP MAX 9.4 10 10.6 8.8 10 11.2 VCC = 5 V 2.7 3.3 4 2.4 3.3 4.2 30 250 5 5.2 1.67 1.9 4.8 VCC = 15 V TA = –55°C to 125°C TRIG voltage level RESET current 3 1.45 VCC = 5 V RESET voltage level 0.3 5.6 1.1 1.67 2.2 0.5 2 0.7 1 nA V 0.9 1 0.3 1.1 μA V RESET at VCC 0.1 0.4 0.1 0.4 RESET at 0 V –0.4 –1 –0.4 –1.5 20 100 20 100 nA 0.15 0.4 V 9 10 11 2.6 3.3 4 0.1 0.25 0.4 0.75 2 2.5 VCC = 5 V, IO = 8 mA 9.6 TA = –55°C to 125°C TA = –55°C to 125°C VCC = 15 V, IOL = 10 mA VCC = 15 V, IOL = 50 mA VCC = 15 V, IOL = 100 mA VCC = 5 V, IOL = 5 mA Output low, No load Supply current Output high, No load 3.8 0.1 0.15 0.5 1 2 TA = –55°C to 125°C 2.2 2.7 V 2.5 TA = –55°C to 125°C 2.5 0.35 0.1 TA = –55°C to 125°C 0.2 0.1 0.35 0.15 0.4 0.8 0.15 13 0.25 13.3 12.75 13.3 12 12.5 3 TA = –55°C to 125°C V 0.2 TA = –55°C to 125°C TA = –55°C to 125°C mA 3.8 0.4 VCC = 15 V, IOH = –200 mA VCC = 5 V, IOH = –100 mA 3.3 TA = –55°C to 125°C VCC = 5 V, IOL = 8 mA VCC = 15 V, IOH = –100 mA 10.4 10.4 2.9 VCC = 15 V, IOL = 200 mA VCC = 5 V, IOL = 3.5 mA 10 9.6 2.9 VCC = 5 V (1) 0.7 TA = –55°C to 125°C CONT voltage (open circuit) High-level output voltage 250 5 V 1.9 0.5 VCC = 15 V Low-level output voltage 30 4.5 6 TA = –55°C to 125°C TRIG at 0 V DISCH switch off-state current DISCH switch on-state voltage UNIT VCC = 15 V THRES current (1) TRIG current NA555 NE555 SA555 SE555 12.5 3.3 2.75 V 3.3 2 VCC = 15 V 10 12 10 15 VCC = 5 V 3 5 3 6 VCC = 15 V 9 10 9 13 VCC = 5 V 2 4 2 5 mA This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 12. For example, when VCC = 5 V, the maximum value is R = RA + RB ≉ 3.4 MΩ, and for VCC = 15 V, the maximum value is 10 MΩ. Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 5 NA555, NE555, SA555, SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www.ti.com 7.5 Operating Characteristics VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted) PARAMETER MIN Initial error of timing interval (2) Each timer, monostable (3) Temperature coefficient of timing interval Each timer, monostable (3) Each timer, astable Each timer, astable TA = 25°C (5) TYP MAX 0.5 1.5 (4) 1.5 TA = MIN to MAX (5) (3) Supply-voltage sensitivity of Each timer, monostable (5) timing interval Each timer, astable NA555 NE555 SA555 SE555 TEST CONDITIONS (1) 30 0.05 TYP MAX 1 3 2.25 100 (4) 90 TA = 25°C MIN UNIT 50 ppm/ °C 150 0.2 (4) 0.15 0.1 % 0.5 0.3 %/V Output-pulse rise time CL = 15 pF, TA = 25°C 100 200 (4) 100 300 ns Output-pulse fall time CL = 15 pF, TA = 25°C 100 200 (4) 100 300 ns (1) (2) (3) (4) (5) 6 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA = 2 kΩ to 100 kΩ, C = 0.1 μF. On products compliant to MIL-PRF-38535, this parameter is not production tested. Values specified are for a device in an astable circuit similar to Figure 12, with the following component values: RA = 1 kΩ to 100 kΩ, C = 0.1 μF. Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 NA555, NE555, SA555, SE555 www.ti.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 7.6 Typical Characteristics Data for temperatures below –40°C and above 105°C are applicable for SE555 circuits only. 10 7 VCC = 5 V 4 2 VOL − Low-Level Output Voltage − V VOL − Low-Level Output Voltage − V 10 7 TA = −55°C 1 0.7 TA = 25°C 0.4 TA = 125°C 0.2 0.1 0.07 0.04 VCC = 10 V 4 2 TA = 25°C 1 0.7 TA= −55°C 0.4 TA = 125°C 0.2 0.1 0.07 0.04 0.02 0.02 0.01 0.01 1 2 4 7 10 20 40 1 70 100 Figure 1. Low-Level Output Voltage vs Low-Level Output Current 7 10 20 40 70 100 Figure 2. Low-Level Output Voltage vs Low-Level Output Current TA = −55°C VCC = 15 V 1.8 4 TA = −55°C ( VCC − VOH) − Voltage Drop − V VOL − Low-Level Output Voltage − V 4 2.0 10 7 2 1 0.7 0.4 TA = 25°C 0.2 TA = 125°C 0.1 0.07 0.04 0.02 1.6 TA = 25°C 1.4 1.2 TA = 125°C 1 0.8 0.6 0.4 0.2 0.01 1 2 4 7 10 20 40 0 70 100 VCC = 5 V to 15 V 1 2 4 7 10 20 40 70 100 IOH − High-Level Output Current − mA IOL − Low-Level Output Current − mA Figure 3. Low-Level Output Voltage vs Low-Level Output Current Output Low, No Load 9 8 TA = 25°C 7 6 5 TA = −55°C 4 Figure 4. Drop Between Supply Voltage and Output vs High-Level Output Current Pulse Duration Relative to Value at VCC = 10 V 10 I CC − Supply Current − mA 2 IOL − Low-Level Output Current − mA IOL − Low-Level Output Current − mA TA = 125°C 3 2 1 1.015 1.010 1.005 1 0.995 0.990 8 0.985 0 5 6 7 8 9 10 11 12 13 14 15 0 5 10 15 20 VCC − Supply Voltage − V VCC − Supply Voltage − V Figure 5. Supply Current vs Supply Voltage Figure 6. Normalized Output Pulse Duration (Monostable Operation) vs Supply Voltage Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 7 NA555, NE555, SA555, SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www.ti.com Typical Characteristics (continued) Data for temperatures below –40°C and above 105°C are applicable for SE555 circuits only. 1000 VCC = 10 V 900 TA = 125°C 1.010 t PD – Propagation Delay Time – ns Pulse Duration Relative to Value at TA = 25 C 1.015 1.005 1 0.995 0.990 8 700 TA = 70°C 600 500 TA = 25°C 400 300 T A = 0° C 200 TA = –55°C 100 0.985 −75 8 −50 −25 0 25 50 75 100 125 TA − Free-Air Temperature − °C Figure 7. Normalized Output Pulse Duration (Monostable Operation) vs Free-Air Temperature 8 800 Submit Documentation Feedback 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Lowest Level of Trigger Pulse – ×VCC 0.4 Figure 8. Propagation Delay Time vs Lowest Voltage Level of Trigger Pulse Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 NA555, NE555, SA555, SE555 www.ti.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 8 Detailed Description 8.1 Overview The xx555 timer is a popular and easy to use for general purpose timing applications from 10 µs to hours or from < 1mHz to 100 kHz. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. Maximum output sink and discharge sink current is greater for higher VCC and less for lower VCC. 8.2 Functional Block Diagram VCC 8 6 THRES 2 TRIG CONT 5 Î Î Î Î Î Î Î Î Î RESET 4 Î Î Î Î Î Î Î R1 R 3 OUT 1 S 7 DISCH 1 GND A. Pin numbers shown are for the D, JG, P, PS, and PW packages. B. RESET can override TRIG, which can override THRES. 8.3 Feature Description 8.3.1 Mono-stable Operation For mono-stable operation, any of these timers can be connected as shown in Figure 9. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high, and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1. Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 9 NA555, NE555, SA555, SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www.ti.com Feature Description (continued) VCC (5 V to 15 V) RA Î Î Î 4 7 6 Input 2 5 8 CONT VCC RL RESET DISCH OUT 3 Output THRES TRIG GND 1 Pin numbers shown are for the D, JG, P, PS, and PW packages. Figure 9. Circuit for Monostable Operation Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the sequence ends only if TRIG is high for at least 10 µs before the end of the timing interval. When the trigger is grounded, the comparator storage time can be as long as 10 µs, which limits the minimum monostable pulse width to 10 µs. Because of the threshold level and saturation voltage of Q1, the output pulse duration is approximately tw = 1.1RAC. Figure 11 is a plot of the time constant for various values of RA and C. The threshold levels and charge rates both are directly proportional to the supply voltage, VCC. The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is constant during the time interval. ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC. 10 RA = 10 MΩ 1 Input Voltage ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ Output Voltage Capacitor Voltage tw − Output Pulse Duration − s Voltage − 2 V/div RA = 9.1 kΩ CL = 0.01 µF RL = 1 kΩ See Figure 9 RA = 1 MΩ 10−1 10−2 10−3 RA = 100 kΩ RA = 10 kΩ 10−4 RA = 1 kΩ 10−5 0.001 0.01 Figure 10. Typical Monostable Waveforms 10 Submit Documentation Feedback 0.1 1 10 100 C − Capacitance − µF Time − 0.1 ms/div Figure 11. Output Pulse Duration vs Capacitance Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 NA555, NE555, SA555, SE555 www.ti.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 Feature Description (continued) 8.3.2 A-stable Operation As shown in Figure 12, adding a second resistor, RB, to the circuit of Figure 9 and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multi-vibrator. The capacitor C charges through RA and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and RB. ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ This astable connection results in capacitor C charging and discharging between the threshold-voltage level (≈ 0.67 × VCC) and the trigger-voltage level (≈ 0.33 × VCC). As in the mono-stable circuit, charge and discharge times (and, therefore, the frequency and duty cycle) are independent of the supply voltage. VCC (5 V to 15 V) Î Î Î 0.01 µF Open (see Note A) 5 8 VCC CONT 4 7 RB 6 2 RL RESET DISCH 3 OUT Output THRES t H TRIG GND C RL = 1 kW See Figure 12 Voltage − 1 V/div RA RA = 5 kW RB = 3 kW C = 0.15 µF tL Output Voltage 1 Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: Decoupling CONT voltage to ground with a capacitor can improve operation. This should be evaluated for individual applications. Figure 12. Circuit for Astable Operation Capacitor Voltage Time − 0.5 ms/div Figure 13. Typical Astable Waveforms Figure 12 shows typical waveforms generated during astable operation. The output high-level duration tH and low-level duration tL can be calculated as follows: tH = 0.693 (R A + RB )C (1) tL = 0.693 (RB )C (2) Other useful relationships are shown below: period = tH + tL = 0.693 (R A + 2RB )C (3) 1.44 frequency » (R A +2RB )C (4) tL RB Output driver duty cycle = = tH + tL R A + 2RB (5) Output waveform duty cycle = Low-to-high ratio = tH RB = 1tH + tL R A + 2RB (6) tL RB = tH R A + RB Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 (7) Submit Documentation Feedback 11 NA555, NE555, SA555, SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www.ti.com Feature Description (continued) 100 k RA + 2 RB = 1 kΩ f − Free-Running Frequency − Hz RA + 2 RB = 10 kΩ 10 k RA + 2 RB = 100 kΩ 1k 100 10 1 RA + 2 RB = 1 MΩ RA + 2 RB = 10 MΩ 0.1 0.001 0.01 0.1 1 10 100 C − Capacitance − µF Figure 14. Free-Running Frequency 8.3.3 Frequency Divider By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency divider. Figure 15 shows a divide-by-three circuit that makes use of the fact that re-triggering cannot occur during the timing cycle. ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ Voltage − 2 V/div VCC = 5 V RA = 1250 Ω C = 0.02 µF See Figure 9 Input Voltage Output Voltage Capacitor Voltage Time − 0.1 ms/div Figure 15. Divide-by-Three Circuit Waveforms 8.4 Device Functional Modes Table 1. Function Table (1) 12 RESET TRIGGER VOLTAGE (1) THRESHOLD VOLTAGE (1) OUTPUT DISCHARGE SWITCH Low Irrelevant Irrelevant Low On High <1/3 VCC Irrelevant High Off High >1/3 VCC >2/3 VCC Low High >1/3 VCC <2/3 VCC On As previously established Voltage levels shown are nominal. Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 NA555, NE555, SA555, SE555 www.ti.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 9 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The xx555 timer devices use resistor and capacitor charging delay to provide a programmable time delay or operating frequency. This section presents a simplified discussion of the design process. 9.2 Typical Applications 9.2.1 Missing-Pulse Detector The circuit shown in Figure 16 can be used to detect a missing pulse or abnormally long spacing between consecutive pulses in a train of pulses. The timing interval of the monostable circuit is re-triggered continuously by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing, missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse as shown in Figure 17. VCC (5 V to 15 V) 4 RESET Input 2 8 VCC OUT 0.01 µF 3 TRIG DISCH 5 RL CONT THRES GND 7 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ RA Output 6 C 1 A5T3644 Pin numbers shown are shown for the D, JG, P, PS, and PW packages. Figure 16. Circuit for Missing-Pulse Detector 9.2.1.1 Design Requirements Input fault (missing pulses) must be input high. Input stuck low will not be detected because timing capacitor "C" will remain discharged. 9.2.1.2 Detailed Design Procedure Choose RA and C so that RA× C > [maximum normal input high time]. RL improves VOH, but it is not required for TTL compatibility. Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 13 NA555, NE555, SA555, SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www.ti.com ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Typical Applications (continued) 9.2.1.3 Application Curves Voltage − 2 V/div VCC = 5 V RA = 1 kΩ C = 0.1 µF See Figure 15 Input Voltage ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Output Voltage Capacitor Voltage Time − 0.1 ms/div Figure 17. Completed Timing Waveforms for Missing-Pulse Detector 9.2.2 Pulse-Width Modulation The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is accomplished by applying an external voltage (or current) to CONT. Figure 18 shows a circuit for pulse-width modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the threshold voltage. Figure 19 shows the resulting output pulse-width modulation. While a sine-wave modulation signal is shown, any wave shape could be used. VCC (5 V to 15 V) 4 RESET Clock Input 2 RL 8 VCC OUT TRIG RA 3 Output 7 DISCH Modulation 5 Input (see Note A) CONT THRES 6 GND C 1 Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. Figure 18. Circuit for Pulse-Width Modulation 14 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 NA555, NE555, SA555, SE555 www.ti.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 Typical Applications (continued) 9.2.2.1 Design Requirements Clock input must have VOL and VOH levels that are less than and greater than 1/3 VCC. Modulation input can vary from ground to VCC. The application must be tolerant of a nonlinear transfer function; the relationship between modulation input and pulse width is not linear because the capacitor charge is based RC on an negative exponential curve. 9.2.2.2 Detailed Design Procedure Choose RA and C so that RA × C = 1/4 [clock input period]. RL improves VOH, but it is not required for TTL compatibility. ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ 9.2.2.3 Application Curves RA = 3 kΩ C = 0.02 µF RL = 1 kΩ See Figure 18 Voltage − 2 V/div Modulation Input Voltage Clock Input Voltage Output Voltage Capacitor Voltage Time − 0.5 ms/div Figure 19. Pulse-Width-Modulation Waveforms 9.2.3 Pulse-Position Modulation As shown in Figure 20, any of these timers can be used as a pulse-position modulator. This application modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure 21 shows a triangular-wave modulation signal for such a circuit; however, any wave shape could be used. Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 15 NA555, NE555, SA555, SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www.ti.com Typical Applications (continued) VCC (5 V to 15 V) 4 8 RESET 2 VCC OUT RA 3 Output TRIG DISCH Modulation Input 5 (see Note A) RL CONT THRES 7 6 RB GND C Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. Figure 20. Circuit for Pulse-Position Modulation 9.2.3.1 Design Requirements Both DC and AC coupled modulation input will change the upper and lower voltage thresholds for the timing capacitor. Both frequency and duty cycle will vary with the modulation voltage. 9.2.3.2 Detailed Design Procedure The nominal output frequency and duty cycle can be determined using formulas in A-stable Operation section. RL improves VOH, but it is not required for TTL compatibility. 16 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 NA555, NE555, SA555, SE555 www.ti.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 Typical Applications (continued) ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 9.2.3.3 Application Curves Voltage − 2 V/div RA = 3 kΩ RB = 500 Ω RL = 1 kΩ See Figure 20 Modulation Input Voltage Output Voltage Capacitor Voltage Time − 0.1 ms/div Figure 21. Pulse-Position-Modulation Waveforms 9.2.4 Sequential Timer Many applications, such as computers, require signals for initializing conditions during start-up. Other applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be connected to provide such sequential control. The timers can be used in various combinations of astable or monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 22 shows a sequencer circuit with possible applications in many systems, and Figure 23 shows the output waveforms. VCC 4 RESET 2 8 VCC 3 OUT TRIG S DISCH 5 0.01 µF CONT 4 RESET RA 33 kΩ 2 0.001 µF 7 1 CA = 10 µF RA = 100 kΩ 6 0.01 µF CA RB Output A CONT THRES GND 1 CB CB = 4.7 µF RB = 100 kΩ 4 RESET 33 kΩ 2 0.001 µF DISCH 7 5 THRES GND TRIG 8 VCC 3 OUT DISCH 5 6 0.01 µF Output B TRIG 8 VCC 3 OUT CONT THRES GND 1 CC CC = 14.7 µF RC = 100 kΩ RC 7 6 Output C Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: S closes momentarily at t = 0. Figure 22. Sequential Timer Circuit Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 17 NA555, NE555, SA555, SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www.ti.com Typical Applications (continued) 9.2.4.1 Design Requirements The sequential timer application chains together multiple mono-stable timers. The joining components are the 33kΩ resistors and 0.001-µF capacitors. The output high to low edge passes a 10-µs start pulse to the next monostable. 9.2.4.2 Detailed Design Procedure The timing resistors and capacitors can be chosen using this formula. tw = 1.1 × R × C. ÏÏÏÏÏ ÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ 9.2.4.3 Application Curves See Figure 22 Voltage − 5 V/div Output A twA twA = 1.1 RACA twB Output B twB = 1.1 RBCB Output C twC twC = 1.1 RCCC t=0 t − Time − 1 s/div Figure 23. Sequential Timer Waveforms 10 Power Supply Recommendations The devices are designed to operate from an input voltage supply range between 4.5 V and 16 V. (18 V for SE555). A bypass capacitor is highly recommended from VCC to ground pin; ceramic 0.1 µF capacitor is sufficient. 18 Submit Documentation Feedback Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 NA555, NE555, SA555, SE555 www.ti.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY NA555 Click here Click here Click here Click here Click here NE555 Click here Click here Click here Click here Click here SA555 Click here Click here Click here Click here Click here SE555 Click here Click here Click here Click here Click here 11.2 Trademarks All trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. Copyright © 1973–2014, Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 31-Jan-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) JM38510/10901BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510 /10901BPA M38510/10901BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510 /10901BPA NA555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU | CU SN N / A for Pkg Type -40 to 105 NA555P NA555PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 105 NA555P NE555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 NE555 NE555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DRG3 PREVIEW SOIC D 8 TBD Call TI Call TI 0 to 70 NE555 NE555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU | CU SN N / A for Pkg Type 0 to 70 NE555P NE555PE3 PREVIEW PDIP P 8 TBD Call TI Call TI 0 to 70 NE555P NE555PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE555P Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 31-Jan-2016 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) NE555PSLE OBSOLETE SO PS 8 TBD Call TI Call TI 0 to 70 NE555PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWE4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWRE4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555Y OBSOLETE TBD Call TI Call TI 0 to 70 SA555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 SA555 SA555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA555P SA555PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA555P 0 Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 31-Jan-2016 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SE555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555FKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SE555FKB SE555JG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 SE555JG SE555JGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 SE555JGB SE555N OBSOLETE PDIP N 8 TBD Call TI Call TI -55 to 125 SE555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 SE555P (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com 31-Jan-2016 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SE555, SE555M : • Catalog: SE555 • Military: SE555M • Space: SE555-SP, SE555-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant NA555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NA555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE555DR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 NE555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE555PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 NE555PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 SA555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SA555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SE555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SE555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) NA555DR SOIC D 8 2500 340.5 338.1 20.6 NA555DR SOIC D 8 2500 367.0 367.0 35.0 NE555DR SOIC D 8 2500 364.0 364.0 27.0 NE555DR SOIC D 8 2500 367.0 367.0 35.0 NE555DRG4 SOIC D 8 2500 367.0 367.0 35.0 NE555DRG4 SOIC D 8 2500 340.5 338.1 20.6 NE555PSR SO PS 8 2000 367.0 367.0 38.0 NE555PWR TSSOP PW 8 2000 367.0 367.0 35.0 SA555DR SOIC D 8 2500 340.5 338.1 20.6 SA555DRG4 SOIC D 8 2500 340.5 338.1 20.6 SE555DR SOIC D 8 2500 367.0 367.0 38.0 SE555DRG4 SOIC D 8 2500 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP 6.2 SEATING PLANE PIN 1 ID AREA A 0.1 C 6X 0.65 8 1 3.1 2.9 NOTE 3 2X 1.95 4 5 B 4.5 4.3 NOTE 4 SEE DETAIL A 8X 0.30 0.19 0.1 C A 1.2 MAX B (0.15) TYP 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM 1 8 (R0.05) TYP SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) TYP 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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