ON NLSF302MNR2G Quad 2−input nor gate Datasheet

NLSF302
Quad 2−Input NOR Gate
The NLSF302 is an advanced high speed CMOS 2−input NOR gate
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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Features
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High Speed: tPD = 3.6 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2.0 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Function Compatible with Other Standard Logic Families
QFN−16 Package
Latchup Performance Exceeds 300 mA
ESD Performance: Human Body Model; > 2000 V,
Machine Model > 200 V
Chip Complexity: 40 FETs or 10 Equivalent Gates
Pb−Free Package is Available*
FUNCTION TABLE
Inputs
B
Y
L
L
H
H
L
H
L
H
H
L
L
L
MARKING DIAGRAM
ÇÇÇ
ÇÇÇ
ÇÇÇ
16
1
NLSF
302
ALYW G
G
NLSF302 = Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Output
A
QFN−16
MN SUFFIX
CASE 485G
ORDERING INFORMATION
Device
NLSF302MNR2
NLSF302MNR2G
Package
Shipping†
QFN−16
3000/Tape & Reel
QFN−16
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 4
1
Publication Order Number:
NLSF302/D
NLSF302
B2
A3
B3
Y=A+B
9
1
NLSF302
MN Package
11
NC
Y2
3
(Top View)
10
A4
A2
4
9
Y3
Y3
6
Y4
Figure 1. LOGIC DIAGRAM
7
8
B3
5
A3
12
B4
2
10
13
12
Y2
7
8
13
GND
B4
5
14
B2
A4
3
15
NC
Y1
4
Y4
A2
15
1
VCC
B1
16
Y1
A1
A1
B1
16
Figure 2. PIN ASSIGNMENT (QFN−16)
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MAXIMUM RATINGS
Symbol
Value
Unit
DC Supply Voltage
Parameter
VCC
– 0.5 to + 7.0
V
DC Input Voltage
Vin
– 0.5 to + 7.0
V
DC Output Voltage
Vout
– 0.5 to VCC + 0.5
V
Input Diode Current
IIK
− 20
mA
Output Diode Current
IOK
± 20
mA
DC Output Current, per Pin
Iout
± 25
mA
DC Supply Current, VCC and GND Pins
ICC
± 50
mA
Power Dissipation in Still Air
PD
450
mW
Storage Temperature
Tstg
– 65 to + 150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
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Symbol
Min
Max
Unit
DC Supply Voltage
Parameter
VCC
2.0
5.5
V
DC Input Voltage
Vin
0
5.5
V
DC Output Voltage
Vout
0
VCC
V
TA
−40
+85
°C
tr, tf
0
0
100
20
ns/V
Operating Temperature
Input Rise and Fall Time
VCC = 3.3 V ± 0.3 V
VCC =5.0 V ± 0.5 V
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2
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
NLSF302
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DC ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Symbol
TA = 25°C
VCC
V
Min
1.50
VCC x 0.7
Minimum High−Level
Input Voltage
VIH
2.0
3.0 to 5.5
Maximum Low−Level
Input Voltage
VIL
2.0
3.0 to 5.5
VOH
2.0
3.0
4.5
1.9
2.9
4.4
3.0
4.5
2.58
3.94
Minimum High−Level
Output Voltage
Vin = VIH or VIL
IOH = −50 mA
Vin = VIH or VIL
IOH = −4 mA
IOH = −8 mA
Maximum Low−Level
Output Voltage
VOL
Vin = VIH or VIL
IOL = 50 mA
Typ
Max
Min
Max
1.50
VCC x 0.7
0.50
VCC x 0.3
2.0
3.0
4.5
Unit
V
0.50
VCC x 0.3
V
V
1.9
2.9
4.4
2.48
3.80
2.0
3.0
4.5
Vin = VIH or VIL
IOL = 4 mA
IOL = 8 mA
TA = − 40 to 85°C
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
V
Maximum Input Leakage
Current
Vin = 5.5 V or GND
Iin
0 to 5.5
± 0.1
± 1.0
mA
Maximum Quiescent
Supply Current
Vin = VCC or GND
ICC
5.5
2.0
20.0
mA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Parameter
Test Conditions
Symbol
Maximum Propagation Delay,
Input A or B to Output Y
VCC = 3.3 ± 0.3 V CL = 15 pF
CL = 50 pF
tPLH,
tPHL
Min
VCC = 5.0 ± 0.5 V CL = 15 pF
CL = 50 pF
Maximum Input Capacitance
Cin
TA = − 40 to 85°C
Typ
Max
Min
Max
Unit
5.6
8.1
7.9
11.4
1.0
1.0
9.5
13.0
ns
3.6
5.1
5.5
7.5
1.0
1.0
6.5
8.5
4
10
10
pF
Typical @ 25°C, VCC = 5.0 V
Power Dissipation Capacitance (Note 1)
15
CPD
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0V)
TA = 25°C
Symbol
Typ
Max
Unit
Quiet Output Maximum Dynamic VOL
VOLP
0.3
0.8
V
Quiet Output Minimum Dynamic VOL
VOLV
− 0.3
− 0.8
V
Minimum High Level Dynamic Input Voltage
VIHD
3.5
V
Maximum Low Level Dynamic Input Voltage
VILD
1.5
V
Characteristic
TEST POINT
A or B
VCC
50%
GND
tPLH
tPHL
OUTPUT
DEVICE
UNDER
TEST
INPUT
CL*
Y 50% VCC
*Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
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3
Figure 5. Input Equivalent Circuit
NLSF302
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE C
D
PIN 1
LOCATION
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
A
B
ÇÇ
ÇÇ
ÇÇ
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
0.15 C
TOP VIEW
0.15 C
(A3)
0.10 C
A
16 X
0.08 C
SIDE VIEW
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.18 TYP
0.30
0.50
SEATING
PLANE
A1
C
D2
16X
e
L
5
NOTE 5
EXPOSED PAD
8
4
9
E2
16X
K
12
1
16
16X
13
b
0.10 C A B
0.05 C
e
BOTTOM VIEW
NOTE 3
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NLSF302/D
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