NEC NP40N055MHE-S18-AY Mos field effect transistor switching n-channel power mos fet Datasheet

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP40N055EHE, NP40N055KHE
NP40N055CHE, NP40N055DHE, NP40N055MHE, NP40N055NHE
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
These products are N-channel MOS Field Effect Transistors designed for high current switching applications.
<R>
ORDERING INFORMATION
PART NUMBER
NP40N055EHE-E1-AY
Note1, 2
NP40N055EHE-E2-AY
Note1, 2
NP40N055KHE-E1-AY
Note1
NP40N055KHE-E2-AY
Note1
NP40N055CHE-S12-AZ
Note1, 2
NP40N055DHE-S12-AY
Note1, 2
NP40N055MHE-S18-AY
Note1
NP40N055NHE-S18-AY
Note1
LEAD PLATING
PACKING
Pure Sn (Tin)
Tape 800 p/reel
PACKAGE
TO-263 (MP-25ZJ) typ. 1.4 g
TO-263 (MP-25ZK) typ. 1.5 g
Sn-Ag-Cu
Pure Sn (Tin)
TO-220 (MP-25) typ. 1.9 g
Tube 50 p/tube
Notes 1. Pb-free (This product does not contain Pb in the external electrode.)
2. Not for new design
TO-262 (MP-25 Fin Cut) typ. 1.8 g
TO-220 (MP-25K) typ. 1.9 g
TO-262 (MP-25SK) typ. 1.8 g
(TO-220)
FEATURES
• Channel temperature 175 degree rated
• Super low on-state resistance
RDS(on) = 23 mΩ MAX. (VGS = 10 V, ID = 20 A)
• Low input capacitance
(TO-262)
Ciss = 1070 pF TYP.
• Built-in gate protection diode
(TO-263)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D14092EJ6V0DS00 (6th edition)
Date Published October 2007 NS
Printed in Japan
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
2002, 2007
NP40N055EHE, NP40N055KHE, NP40N055CHE, NP40N055DHE, NP40N055MHE, NP40N055NHE
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
55
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±20
V
Drain Current (DC) (TC = 25°C)
ID(DC)
±40
A
ID(pulse)
±100
A
Drain Current (Pulse)
Note1
Total Power Dissipation (TA = 25°C)
PT
1.8
W
Total Power Dissipation (TC = 25°C)
PT
66
W
Channel Temperature
Tch
175
°C
Tstg
−55 to +175
°C
Single Avalanche Current
Note2
IAS
29/21/7
A
Single Avalanche Energy
Note2
EAS
0.8/44/49
mJ
Storage Temperature
Notes 1. PW ≤ 10 μs, Duty cycle ≤ 1%
2. Starting Tch = 25°C, VDD = 28 V, RG = 25 Ω, VGS = 20 → 0 V (See Figure 4.)
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Rth(ch-C)
2.27
°C/W
Channel to Ambient Thermal Resistance
Rth(ch-A)
83.3
°C/W
2
Data Sheet D14092EJ6V0DS
NP40N055EHE, NP40N055KHE, NP40N055CHE, NP40N055DHE, NP40N055MHE, NP40N055NHE
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
18
23
mΩ
4.0
V
Drain to Source On-state Resistance
RDS(on)
VGS = 10 V, ID = 20 A
Gate to Source Threshold Voltage
VGS(th)
VDS = VGS, ID = 250 μA
2.0
3.0
Forward Transfer Admittance
| yfs |
VDS = 10 V, ID = 20 A
7
14
Drain Leakage Current
IDSS
VDS = 55 V, VGS = 0 V
10
μA
Gate to Source Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
±10
μA
Input Capacitance
Ciss
VDS = 25 V,
1070
1610
pF
Coss
VGS = 0 V,
190
280
pF
95
180
pF
Output Capacitance
f = 1 MHz
S
Reverse Transfer Capacitance
Crss
Turn-on Delay Time
td(on)
ID = 20 A,
16
35
ns
tr
VGS = 10 V,
9.2
23
ns
29
57
ns
9.2
23
ns
35
nC
Rise Time
VDD = 28 V,
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
ID = 40 A,
23
Gate to Source Charge
QGS
VDD = 44 V,
6
nC
9
nC
IF = 40 A, VGS = 0 V
1.0
V
RG = 1 Ω
VGS = 10 V
Gate to Drain Charge
QGD
Body Diode Forward Voltage
VF(S-D)
Reverse Recovery Time
trr
IF = 40 A, VGS = 0 V,
38
ns
Qrr
di/dt = 100 A/μs
46
nC
Reverse Recovery Charge
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = 20 → 0 V
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
50 Ω
VGS
RL
Wave Form
RG
PG.
VDD
VGS
0
VGS
10 %
90 %
VDD
VDS
90 %
IAS
90 %
VDS
VGS
0
BVDSS
VDS
10 % 10 %
0
Wave Form
VDS
ID
τ
VDD
Starting Tch
τ = 1 μs
Duty Cycle ≤ 1 %
td(on)
tr
ton
td(off)
tf
toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
PG.
50 Ω
RL
VDD
Data Sheet D14092EJ6V0DS
3
NP40N055EHE, NP40N055KHE, NP40N055CHE, NP40N055DHE, NP40N055MHE, NP40N055NHE
TYPICAL CHARACTERISTICS (TA = 25°C)
Figure1. DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
Figure2. TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
70
100
80
60
40
20
0
0
25
50
75
60
50
40
30
20
10
0
100 125 150 175 200
50
75
100 125 150 175 200
TC - Case Temperature - °C
Figure.3 FORWARD BIAS SAFE OPERATING AREA
Figure4. SINGLE AVALANCHE ENERGY
DERATING FACTOR
1000
100
d
ite
Lim0 V)
n)
o
1
(
S
RDVGS =
(
10
ID(pulse)
ID(DC)
PW
10
1m
DC
Po
Lim wer
ite Dis
sip
d
ati
s
=1
0μ
s
0μ
s
on
1
TC = 25°C
Single Pulse
0.1
0.1
1
10
60
Single Pulse Avalanche Energy - mJ
ID - Drain Current - A
25
0
TC - Case Temperature - °C
49 mJ
44 mJ
50
40
IAS = 7 A
21 A
29 A
30
20
10
0.8 mJ
0
25
100
50
75
100
125
150
175
Starting Tch - Starting Channel Temperature - °C
VDS - Drain to Source Voltage - V
Figure5. TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
rth(t) - Transient Thermal Resistance - °C/W
1000
100
Rth(ch-A) = 83.3°C/W
10
Rth(ch-C) = 2.27°C/W
1
0.1
Single Pulse
0.01
10 μ
100 μ
1m
10 m
100 m
1
PW - Pulse Width - s
4
Data Sheet D14092EJ6V0DS
10
100
1000
NP40N055EHE, NP40N055KHE, NP40N055CHE, NP40N055DHE, NP40N055MHE, NP40N055NHE
Figure7. DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
Figure6. FORWARD TRANSFER CHARACTERISTICS
1000
120
Pulsed
ID - Drain Current - A
ID - Drain Current - A
100
100
TA = −55°C
25°C
75°C
150°C
175°C
10
1
0.1
80
VGS =10 V
60
40
20
2
3
4
VDS = 10 V
6
7
5
Pulsed
0
0
10
TA = 175°C
75°C
25°C
−55°C
0.1
0.1
1
10
100
RDS(on) - Drain to Source On-state Resistance - mΩ
ID - Drain Current - A
Figure10. DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
50
Pulsed
40
30
VGS = 10 V
20
10
0
0.1
1
10
100
RDS(on) - Drain to Source On-state Resistance - mΩ
Figure8. FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
100 Pulsed
VDS = 10 V
0.01
0.01
4
3
5
VDS - Drain to Source Voltage - V
VGS(th) - Gate to Source Threshold Voltage - V
| yfs | - Forward Transfer Admittance - S
VGS - Gate to Source Voltage - V
1
2
1
Figure9. DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
50
Pulsed
40
30
ID = 20 A
20
10
0
0
2
4
6
8
10
12
14
16
18
VGS - Gate to Source Voltage - V
Figure11. GATE TO SOURCE THRESHOLD VOLTAGE vs.
CHANNEL TEMPERATURE
VDS = VGS
ID = 250 μA
4.0
3.0
2.0
1.0
0
−50
0
50
100
150
Tch - Channel Temperature - °C
ID - Drain Current - A
Data Sheet D14092EJ6V0DS
5
Figure13. SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
Figure12. DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
1000
Pulsed
IF - Diode Forward Current - A
40
30
VGS = 10 V
20
10
Pulsed
100
VGS = 10 V
0V
10
1
ID = 20 A
0
−50
50
0
100
0.1
0
150
VF(S-D) - Source to Drain Voltage - V
Figure14. CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
10000
VGS = 0 V
f = 1 MHz
Ciss
1000
Coss
100
10
0.1
Crss
1
10
Figure15. SWITCHING CHARACTERISTICS
1000
100
tf
100
td(off)
td(on)
tr
10
VDD = 28 V
VGS = 10 V
1 RG = 1 Ω
0.1
VDS - Drain to Source Voltage - V
10
1
10
100
16
80
14
12
60
VGS
VDD = 44 V
28 V
11 V
40
10
8
6
4
20
2
VDS
0
0
IF - Diode Forward Current - A
6
100
Figure17. DYNAMIC INPUT/OUTPUT CHARACTERISTICS
VDS - Drain to Source Voltage - V
trr - Reverse Recovery Time - ns
di/dt = 100 A/μs
VGS = 0 V
100
1
0.1
10
1
ID - Drain Current - A
Figure16. REVERSE RECOVERY TIME vs.
DIODE FORWARD CURRENT
1000
1.5
1.0
0.5
Tch - Channel Temperature - °C
10
ID = 40 A
20
30
QG - Gate Charge - nC
Data Sheet D14092EJ6V0DS
40
VGS - Gate to Source Voltage - V
50
td(on), tr, td(off), tf - Switching Time - ns
Ciss, Coss, Crss - Capacitance - pF
RDS(on) - Drain to source On-state Resistance - mΩ
NP40N055EHE, NP40N055KHE, NP40N055CHE, NP40N055DHE, NP40N055MHE, NP40N055NHE
NP40N055EHE, NP40N055KHE, NP40N055CHE, NP40N055DHE, NP40N055MHE, NP40N055NHE
PACKAGE DRAWINGS (Unit: mm)
Note
1.3 ± 0.2
10.0 ± 0.3
No plating
7.88 MIN.
4
2
3
1.4 ± 0.2
0.7 ± 0.2
2.54 TYP.
9.15 ± 0.3
8.0 TYP.
8.5 ± 0.2
1
5.7 ± 0.4
1.0 ± 0.5
4
4.45 ± 0.2
0.025 to
0.25
P.
.5R
0
TY
R
0.8
2.54 TYP.
P.
TY
0.5 ± 0.2
0.75 ± 0.2
0.5 ±
2.8 ± 0.2
1.Gate
2.Drain
3.Source
4.Fin (Drain)
1
2
1.Gate
2.Drain
2.5
3.Source
15.5 MAX.
5.9 MIN.
4
1
0.75 ± 0.1
2.54 TYP.
1.3 ± 0.2
12.7 MIN.
6.0 MAX.
1 2 3
0.5 ± 0.2
2.8 ± 0.2
0.75 ± 0.3
2.54 TYP.
2
3
1.0 ± 0.5
10 TYP.
Note
4.8 MAX.
1.3 ± 0.2
8.5 ± 0.2
1.3 ± 0.2
4.Fin (Drain)
12.7 MIN.
4.8 MAX.
φ 3.6 ± 0.2
10.0 TYP.
1.3 ± 0.2
3
4)TO-262 (MP-25 Fin Cut)
4
8ο
0.25
Note
10.6 MAX.
0.2
0 to
2.54
3)TO-220 (MP-25)
1.3 ± 0.2
2.54 ± 0.25
4.8 MAX.
10 TYP.
1.35 ± 0.3
2)TO-263 (MP-25ZK)
15.25 ± 0.5
1)TO-263 (MP-25ZJ)
3.0 ± 0.3
<R>
0.5 ± 0.2
2.8 ± 0.2
2.54 TYP.
1.Gate
2.Drain
3.Source
4.Fin (Drain)
2.54 TYP.
1.Gate
2.Drain
3.Source
4.Fin (Drain)
Note Not for new design
Data Sheet D14092EJ6V0DS
7
NP40N055EHE, NP40N055KHE, NP40N055CHE, NP40N055DHE, NP40N055MHE, NP40N055NHE
0.8 ± 0.1
0.5 ± 0.2
2.5 ± 0.2
2.54 TYP.
1.Gate
2.Drain
3.Source
4.Fin (Drain)
1.3 ± 0.2
10.1 ± 0.3
1 2 3
4.45 ± 0.2
1.27 ± 0.2
3.1 ± 0.3
4
8.9 ± 0.2
15.9 MAX.
1.27 ± 0.2
2.54 TYP.
10.0 ± 0.2
13.7 ± 0.3
3
13.7 ± 0.3
1 2
4.45 ± 0.2
1.3 ± 0.2
3.1 ± 0.2
4
φ 3.8 ± 0.2
6.3 ± 0.3
2.8 ± 0.3
10.0 ± 0.2
1.2 ± 0.3
6)TO-262 (MP-25SK)
5)TO-220 (MP-25K)
0.8 ± 0.1
0.5 ± 0.2
2.54 TYP.
2.54 TYP.
2.5 ± 0.2
1.Gate
2.Drain
3.Source
4.Fin (Drain)
EQUIVALENT CIRCUIT
Drain
Gate
Gate
Protection
Diode
Remark
Body
Diode
Source
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
8
Data Sheet D14092EJ6V0DS
NP40N055EHE, NP40N055KHE, NP40N055CHE, NP40N055DHE, NP40N055MHE, NP40N055NHE
<R>
TAPE INFORMATION
There are two types (-E1, -E2) of taping depending on the direction of the device.
Draw-out side
<R>
Reel side
MARKING INFORMATION
NEC
40N055
HE
<R>
Pb-free plating marking
Abbreviation of part number
Lot code
RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, please contact an NEC Electronics
sales representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Soldering Method
Soldering Conditions
Infrared reflow
Maximum temperature (Package's surface temperature): 260°C or below
MP-25ZJ, MP-25ZK
Time at maximum temperature: 10 seconds or less
Time of temperature higher than 220°C: 60 seconds or less
Preheating time at 160 to 180°C: 60 to 120 seconds
Recommended
Condition Symbol
IR60-00-3
Maximum number of reflow processes: 3 times
Maximum chlorine content of rosin flux (percentage mass): 0.2% or less
Wave soldering
Maximum temperature (Solder temperature): 260°C or below
MP-25, MP-25K, MP-25SK,
Time: 10 seconds or less
MP-25 Fin Cut
Maximum chlorine content of rosin flux: 0.2% (wt.) or less
Partial heating
Maximum temperature (Pin temperature): 350°C or below
MP-25ZJ, MP-25ZK,
Time (per side of the device): 3 seconds or less
MP-25K, MP-25SK
Maximum chlorine content of rosin flux: 0.2% (wt.) or less
Partial heating
Maximum temperature (Pin temperature): 300°C or below
MP-25, MP-25 Fin Cut
Time (per side of the device): 3 seconds or less
THDWS
P350
P300
Maximum chlorine content of rosin flux: 0.2% (wt.) or less
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet D14092EJ6V0DS
9
NP40N055EHE, NP40N055KHE, NP40N055CHE, NP40N055DHE, NP40N055MHE, NP40N055NHE
• The information in this document is current as of October, 2007. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
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M8E 02. 11-1
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