DATA SHEET MOS FIELD EFFECT TRANSISTOR NP80N03CLE,NP80N03DLE,NP80N03ELE NP80N03KLE SWITCHING N-CHANNEL POWER MOS FET ORDERING INFORMATION DESCRIPTION These products are N-channel MOS Field Effect Transistor designed for high current switching applications. PART NUMBER FEATURES • Channel Temperature 175 degree rated • Super Low On-state Resistance RDS(on)1 = 7.0 mΩ MAX. (VGS = 10 V, ID = 40 A) RDS(on)2 = 9.0 mΩ MAX. (VGS = 5 V, ID = 40 A) • Low Ciss : Ciss = 2600 pF TYP. • Built-in Gate Protection Diode ★ PACKAGE NP80N03CLE TO-220AB NP80N03DLE TO-262 NP80N03ELE TO-263 (MP-25ZJ) NP80N03KLE TO-263 (MP-25ZK) (TO-220AB) ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) VDSS 30 V Gate to Source Voltage (VDS = 0 V) VGSS ±20 V ID(DC) ±80 A Drain Current (DC) Note1 Note2 ID(pulse) ±320 A Total Power Dissipation (TA = 25°C) PT 1.8 W Total Power Dissipation (TC = 25°C) PT 120 W Channel Temperature Tch 175 °C Drain Current (Pulse) Tstg –55 to +175 °C Single Avalanche Current Note3 IAS 50 / 40 / 9 A Single Avalanche Energy Note3 EAS 2.5 / 160 / 400 mJ Storage Temperature Notes 1. Calculated constant current according to MAX. allowable channel temperature. 2. PW ≤ 10 µs, Duty cycle ≤ 1% 3. Starting Tch = 25°C, RG = 25 Ω , VGS = 20 → 0 V (see Figure 4.) (TO-262) (TO-263) THERMAL RESISTANCE Channel to Case Thermal Resistance Rth(ch-C) 1.25 °C/W Channel to Ambient Thermal Resistance Rth(ch-A) 83.3 °C/W The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. D14032EJ4V0DS00 (4th edition) Date Published December 2002 NS CP(K) Printed in Japan The mark ★ shows major revised points. 1999, 2000 NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 30 V, VGS = 0 V 10 µA Gate to Source Leakage Current IGSS VGS = ±20 V, VDS = 0 V ±10 µA Gate to Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 1.5 2.0 2.5 V Forward Transfer Admittance | yfs | VDS = 10 V, ID = 40 A 20 41 RDS(on)1 VGS = 10 V, ID = 40 A 5.3 7.0 mΩ RDS(on)2 VGS = 5 V, ID = 40 A 6.8 9.0 mΩ RDS(on)3 VGS = 4.5 V, ID = 40 A 7.5 11 mΩ Drain to Source On-state Resistance S Input Capacitance Ciss VDS = 25 V 2600 3900 pF Output Capacitance Coss VGS = 0 V 590 890 pF Reverse Transfer Capacitance Crss f = 1 MHz 270 490 pF Turn-on Delay Time td(on) VDD = 15 V, ID = 40 A 20 44 ns VGS = 10 V 12 31 ns RG = 1 Ω 60 120 ns 14 35 ns Rise Time tr Turn-off Delay Time td(off) Fall Time tf Total Gate Charge 1 QG1 VDD = 24 V, VGS = 10 V, ID = 80 A 48 72 nC Total Gate Charge 2 QG2 VDD = 24 V 28 42 nC Gate to Source Charge QGS VGS = 5 V 10 nC Gate to Drain Charge QGD ID = 80 A 14 nC VF(S-D) IF = 80 A, VGS = 0 V 1.0 V Reverse Recovery Time trr IF = 80 A, VGS = 0 V 34 ns Reverse Recovery Charge Qrr di/dt = 100 A/µs 22 nC Body Diode Forward Voltage TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG. VGS = 20 → 0 V TEST CIRCUIT 2 SWITCHING TIME D.U.T. L 50 Ω VGS RL Wave Form RG PG. VDD VGS 0 VGS 10% 90% VDD VDS 90% BVDSS IAS VDS VDS ID Starting Tch τ τ = 1 µs Duty Cycle ≤ 1% TEST CIRCUIT 3 GATE CHARGE PG. 2 50 Ω 10% 0 10% Wave Form VDD D.U.T. IG = 2 mA 90% VDS VGS 0 RL VDD Data Sheet D14032EJ4V0DS td(on) tr ton td(off) tf toff NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE TYPICAL CHARACTERISTICS (T A = 25°C) Figure2. TOTAL POWER DISSIPATION vs. CASE TEMPERATURE Figure1. DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA PT - Total Power Dissipation - W 100 80 60 40 20 0 0 25 50 75 120 100 80 60 40 20 0 100 125 150 175 200 25 0 50 TC - Case Temperature - ˚C 75 100 125 150 175 200 TC - Case Temperature - ˚C Figure4. SINGLE AVALANCHE ENERGY DERATING FACTOR Figure3. FORWARD BIAS SAFE OPERATING AREA 450 ID(pulse) 100 d ite ) Lim10 V = ) (on DS GS R tV (a ID(DC) DC Po Lim wer ite Dis sip d ati on PW 10 0µ s EAS- Single Avalanche Energy - mJ 1000 =1 0µ s 1m s 10 1 TC = 25˚C Single pulse 0.1 0.1 VDS 1 10 - Drain to Source Voltage - V 400 mJ 400 350 300 IAS = 9 A 40 A 50 A 250 200 160 mJ 150 100 50 2.5 mJ 0 25 100 50 75 100 125 150 175 Starting Tch - Starting Channel Temperature - ˚C Figure5. TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH 1000 rth(t) - Transient Thermal Resistance - ˚C/W ID - Drain Current - A dT - Percentage of Rated Power - % 140 100 Rth(ch-A) = 83.3˚C/W 10 Rth(ch-C) = 1.25˚C/W 1 0.1 Single pulse 0.01 10 µ 100 µ 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s Data Sheet D14032EJ4V0DS 3 NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE Figure7. DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE Figure6. FORWARD TRANSFER CHARACTERISTICS 1000 400 Pulsed Pulsed ID - Drain Current - A ID - Drain Current - A 350 100 TA = −50˚C 25˚C 75˚C 150˚C 175˚C 10 1 VGS = 10 V 300 250 5V 200 150 100 4.5 V 50 0.1 1 2 3 5 4 0 0.0 6 TA = 175˚C 75˚C 25˚C −50˚C 0.1 0.1 1 10 100 RDS(on) - Drain to Source On-state Resistance - mΩ ID - Drain Current - A 4 Figure10. DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT Pulsed 30 20 VGS = 4.5 V 5V 10 V 10 0 1 10 100 1000 RDS(on) - Drain to Source On-state Resistance - mΩ 10 VGS(th) - Gate to Source Threshold Voltage - V | yfs | - Forward Transfer Admittance - S Figure8. FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT 100 VDS = 10 V Pulsed 0.01 0.01 4.0 3.0 VDS - Drain to Source Voltage - V VGS - Gate to Source Voltage - V 1 2.0 1.0 Figure9. DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 50 Pulsed 40 30 20 10 0 ID = 40 A 0 2 4 6 8 10 12 14 16 18 VGS - Gate to Source Voltage - V Figure11. GATE TO SOURCE THRESHOLD VOLTAGE vs. CHANNEL TEMPERATURE 3.0 VDS = VGS ID = 250 µ A 2.5 2.0 1.5 1.0 0.5 0 −50 0 50 100 150 Tch - Channel Temperature - ˚C ID - Drain Current - A Data Sheet D14032EJ4V0DS Figure13. SOURCE TO DRAIN DIODE FORWARD VOLTAGE Figure12. DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE 12 Pulsed 10 VGS = 4.5 V 5V 10 V 8 6 4 2 ID = 40 A −50 50 0 100 100 VGS = 10 V 10 VGS = 0 V 1 0.1 0 150 VSD - Source to Drain Voltage - V Figure15. SWITCHING CHARACTERISTICS td(on), tr, td(off), tf - Switching Time - ns 10000 VGS = 0 V f = 1 MHz Ciss 1000 Coss Crss 100 10 0.1 1 10 100 1000 tf 100 td(off) td(on) 10 tr 1 0.1 100 10 Figure17. DYNAMIC INPUT/OUTPUT CHARACTERISTICS VDS - Drain to Source Voltage - V trr - Reverse Recovery Time - ns di/dt = 100 A/µs VGS = 0 V 40 16 35 14 10 VGS 30 VDD = 24 V 15 V 6V 25 20 12 10 8 6 15 4 10 VDS 5 2 ID = 80 A 0 1 100 ID - Drain Current - A Figure16. REVERSE RECOVERY TIME vs. DRAIN CURRENT 1 0.1 10 1 VDS - Drain to Source Voltage - V 1000 1.5 1.0 0.5 Tch - Channel Temperature - ˚C Figure14. CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE Ciss, Coss, Crss - Capacitance - pF Pulsed VGS - Gate to Source Voltage - V 0 1000 ISD - Diode Forward Current - A RDS(on) - Drain to Source On-state Resistance - mΩ NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE 100 0 10 20 30 40 50 60 70 80 0 QG - Gate Charge - nC IF - Drain Current - A Data Sheet D14032EJ4V0DS 5 NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE PACKAGE DRAWINGS (Unit: mm) 1) TO-220AB (MP-25) 2) TO-262 (MP-25 Fin Cut) 1.3±0.2 10 TYP. 4 15.5 MAX. 5.9 MIN. 10.0 TYP. 4 1 2 3 0.5±0.2 2.8±0.2 0.5±0.2 0.75±0.3 2.54 TYP. 2.54 TYP. 1.Gate 2.Drain 3.Source 4.Fin (Drain) 1.Gate 2.Drain 3.Source 4.Fin (Drain) 10.0±0.3 1.3±0.2 No plating 7.88 MIN. 4 3 5.7±0.4 2 1.4±0.2 0.7±0.2 2.54 TYP. 9.15±0.3 8.0 TYP. 8.5±0.2 1.0±0.5 4 2.54 TYP. TY R 0.8 0.025 to 0.25 P. TY 0.5± 0.5±0.2 0.75±0.2 0.2 0 to 8o 0.25 1.Gate 2.Drain 3.Source 4.Fin (Drain) 1 2 3 1.Gate 2.Drain 3.Source 2.5 2.8±0.2 1.3±0.2 P. R 0.5 2.54 6 4.45±0.2 Data Sheet D14032EJ4V0DS 4.Fin (Drain) 2.54±0.25 4.8 MAX. 10 TYP. 1.35±0.3 ★ 4) TO-263 (MP-25ZK) 3) TO-263 (MP-25ZJ) 1 2.8±0.2 2.54 TYP. 15.25±0.5 0.75±0.1 2.54 TYP. 1.3±0.2 12.7 MIN. 1.3±0.2 12.7 MIN. 6.0 MAX. 1 2 3 1.3±0.2 4.8 MAX. 8.5±0.2 3.0±0.3 φ 3.6±0.2 1.0±0.5 4.8 MAX. 10.6 MAX. NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE EQUIVALENT CIRCUIT Drain Body Diode Gate Gate Protection Diode Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. Source Data Sheet D14032EJ4V0DS 7 NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE • The information in this document is current as of December, 2002. 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