ON NTB5404N Power mosfet Datasheet

NTB5404N, NTP5404N,
NVB5404N
Power MOSFET
40 V, 167 A, Single N−Channel, D2PAK &
TO−220
Features
•
•
•
•
•
www.onsemi.com
Low RDS(on)
High Current Capability
Low Gate Charge
AEC−Q101 Qualified and PPAP Capable − NVB5404N
These Devices are Pb−Free and are RoHS Compliant
V(BR)DSS
RDS(ON) MAX
ID MAX
(Note 1)
40 V
4.5 m @ 10 V
167 A
D
Applications
• Electronic Brake Systems
• Electronic Power Steering
• Bridge Circuits
N−Channel
G
S
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol
Value
Units
Drain−to−Source Voltage
VDSS
40
V
Gate−to−Source Voltage
VGS
±20
V
ID
167
A
Continuous Drain
Current − RJC
Steady
State
Power Dissipation −
RJC
Steady
State
TC = 25°C
Continuous Drain
Current − RJA
(Note 1)
Steady
State
TA = 25°C
Power Dissipation −
RJA (Note 1)
Steady
State
TC = 25°C
TC = 100°C
Pulsed Drain Current
tp = 10 s
Operating Junction and Storage Temperature
Source Current (Body Diode) Pulsed
Single Pulse Drain−to Source Avalanche
Energy − (VDD = 50 V, VGS = 10 V, IPK = 45 A,
L = 1 mH, RG = 25 )
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
PD
254
W
ID
24
A
PD
5.4
W
IDM
670
A
TJ,
TSTG
−55 to
175
°C
IS
75
A
EAS
1000
mJ
TL
260
°C
THERMAL RESISTANCE RATINGS
Symbol
Max
Unit
Junction−to−Case (Drain)
RθJC
0.59
°C/W
Junction−to−Ambient (Note 1)
RθJA
50
°C/W
1. Surface mounted on FR4 board using 1 sq in pad size,
(Cu Area 1.127 sq in [2 oz] including traces).
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 8
D2PAK
CASE 418B
STYLE 2
2
NTB5404NG
AYWW
3
1
4
17
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Parameter
1
118
TA = 100°C
TA = 25°C
MARKING
DIAGRAMS
1
TO−220AB
CASE 221A
STYLE 5
1
2
3
G
A
Y
WW
NTP5404NRG
AYWW
= Pb−Free Device
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping†
NTB5404NT4G
D2PAK
800 / Tape & Reel
(Pb−Free)
NTP5404NRG
TO−220
(Pb−Free)
50 Units / Rail
NVB5404NT4G
D2PAK
(Pb−Free)
800 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTB5404N/D
NTB5404N, NTP5404N, NVB5404N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise stated)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 A
40
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
V
34
IDSS
VGS = 0 V,
VDS = 40 V
mV/°C
TJ = 25°C
1.0
TJ = 100°C
10
IGSS
VDS = 0 V, VGS = ±30 V
VGS(TH)
VGS = VDS, ID = 250 A
±100
A
nA
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
Gate Threshold Temperature
Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(TH)/TJ
1.5
3.5
−8.2
RDS(on)
gFS
V
mV/°C
VGS = 10 V, ID = 40 A
3.5
4.5
VGS = 5.0 V, ID = 15 A
5.1
7.0
VDS = 10 V, ID = 15 A
35
m
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
VGS = 0 V, f = 1.0 MHz,
VDS = 32 V
4300
7000
1075
1700
1000
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
450
Total Gate Charge
QG(TOT)
125
Threshold Gate Charge
QG(TH)
5.5
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
VGS = 10 V, VDS = 32 V,
ID = 40 A
pF
nC
12.5
55
SWITCHING CHARACTERISTICS, VGS = 10 V (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
ns
10
VGS = 10 V, VDD = 32 V,
ID = 40 A, RG = 2.5 tf
65
85
85
SWITCHING CHARACTERISTICS, VGS = 5 V (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
ns
25
VGS = 5 V, VDD = 20 V,
ID = 20 A, RG = 2.5 tf
175
46
62
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.8
TJ = 125°C
0.65
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 20 A
75
VGS = 0 V, dISD/dt = 100 A/s,
IS = 20 A
QRR
www.onsemi.com
2
V
ns
38
38
140
2. Pulse Test: pulse width ≤ 300 s, duty cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperatures.
1.1
nC
NTB5404N, NTP5404N, NVB5404N
TYPICAL PERFORMANCE CURVES
175
200
TJ = 25°C
VGS = 8 V to 10 V
7V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
200
6V
150
5V
125
4.8 V
100
4.6 V
75
4.4 V
4.2 V
4V
3.8 V
50
25
0
VDS ≥ 10 V
175
150
125
100
75
TJ = 25°C
50
25
TJ = 125°C
0
2
1
3
4
5
6
7
9
8
10
0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
8
9
3
5
6
7
4
1
2
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.01
ID = 40 A
TJ = 25°C
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
3
5
4
7
6
9
8
10
0.01
TJ = 25°C
0.009
0.008
0.007
VGS = 5 V
0.006
0.005
0.004
0.003
VGS = 10 V
0.002
0.001
20 30
40
50
60
70
80
90 100 110 120 130 140
ID, DRAIN CURRENT (AMPS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
100000
2.2
2
10
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
Figure 1. On−Region Characteristics
VGS = 0 V
ID = 40 A
VGS = 10 V
1.8
TJ = 175°C
10000
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
TJ = −55°C
0
1.6
1.4
1.2
1
1000
TJ = 100°C
100
0.8
0.6
−50
10
−25
0
25
50
75
100
125
150
175
4
8
12
16
20
24
28
32
36
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
www.onsemi.com
3
40
NTB5404N, NTP5404N, NVB5404N
TYPICAL PERFORMANCE CURVES
C, CAPACITANCE (pF)
10000
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
VDS = 0 V VGS = 0 V
TJ = 25°C
Ciss
8000
6000
Crss
Ciss
4000
Coss
2000
0
10
Crss
5
0
5
VGS VDS
10
15
20
25
30
12
QT
10
VDS
24
18
6
QGS
12
2
ID = 40 A
TJ = 25°C
0
0
20
80
100
120
40
60
QG, TOTAL GATE CHARGE (nC)
6
0
140
Figure 8. Gate−To−Source and
Drain−To−Source Voltage vs. Total Charge
Figure 7. Capacitance Variation
40
1000
100
tf
tr
IS, SOURCE CURRENT (AMPS)
td(off)
VDS = 32 V
ID = 40 A
VGS = 10 V
td(on)
10
1
10
RG, GATE RESISTANCE (OHMS)
35
VGS = 0 V
TJ = 25°C
30
25
20
15
10
5
0
0.4
100
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
0.5
0.7
0.6
0.8
0.9
1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
10 S
100
100 S
1 mS
10 mS
dc
10
1
0.1
0.01
0.001
0.1
1.1
Figure 10. Diode Forward Voltage vs. Current
1000
ID, DRAIN CURRENT (AMPS)
t, TIME (ns)
QGD
4
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
30
VGS
8
40
35
36
V DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
12000
VGS = 10 V
SINGLE PULSE
TC = 25°C
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
www.onsemi.com
4
100
NTB5404N, NTP5404N, NVB5404N
100
50% Duty Cycle
RJA (°C/W)
10
1
20%
10%
5%
2%
1%
P(pk)
0.1
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.001
0.000001
0.00001
0.0001
0.001
0.01
0.1
t, PULSE TIME (sec)
Figure 12. Thermal Response
www.onsemi.com
5
1
RJA(t) = r(t) RJA
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RJA(t)
10
100
1000
NTB5404N, NTP5404N, NVB5404N
PACKAGE DIMENSIONS
D2PAK
CASE 418B−04
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
C
E
V
W
−B−
4
A
1
2
S
3
−T−
SEATING
PLANE
K
W
J
G
D 3 PL
0.13 (0.005)
H
M
T B
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
M
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
V
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
0.080
0.110
0.018 0.025
0.090
0.110
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625
0.045 0.055
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.89
1.14
1.40
7.87
8.89
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
1.32
1.83
7.11
8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14
1.40
SOLDERING FOOTPRINT*
VARIABLE
CONFIGURATION
ZONE
10.49
L
M
8.38
16.155
F
2X
3.504
VIEW W−W
2X
1.016
5.080
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
6
NTB5404N, NTP5404N, NVB5404N
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AH
−T−
B
SEATING
PLANE
C
F
T
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
J
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.415
0.160
0.190
0.025
0.038
0.142
0.161
0.095
0.105
0.110
0.161
0.014
0.024
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
----0.080
STYLE 5:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.53
4.07
4.83
0.64
0.96
3.61
4.09
2.42
2.66
2.80
4.10
0.36
0.61
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
----2.04
GATE
DRAIN
SOURCE
DRAIN
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
www.onsemi.com
7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTB5404N/D
Similar pages