ON NUP3115UPMUTAG Transient voltage suppressor Datasheet

NUP3115UPMU
Transient Voltage
Suppressors
Low Capacitance ESD Protection for
High Speed Data
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The three−line voltage transient suppressor array is designed to protect
voltage−sensitive components that require ultra−low capacitance from
ESD and transient voltage events. This device features a common anode
design which protects three independent high speed data lines and a VCC
power line in a single six−lead UDFN low profile package.
Excellent clamping capability, low capacitance, low leakage, and fast
response time make these parts ideal for ESD protection on designs
where board space is at a premium. Because of its low capacitance, it is
suited for use in high frequency designs such as a USB 2.0 high speed.
D1
D2
D3
VCC
6.8V
16V
Features
•
•
•
•
•
•
•
•
•
•
Low Capacitance 0.8 pF
UDFN Package, 1.6 x 1.6 mm
Low Profile of 0.50 mm for Ultra Slim Design
Stand Off Voltage: 5.5 V
Low Leakage
Protects up to Three Data Lines Plus a VCC Pin
VCC Pin = 15 V Protection
D1, D2, and D3 Pins = 6.4 V Minimum Protection
IEC61000−4−2: Level 4 ESD Protection
This is a Pb−Free Device
MARKING
DIAGRAM
1
P3
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
PIN CONNECTIONS
USB 2.0 High−Speed Interface
Cell Phones
MP3 Players
SIM Card Protection
D1 1
D2 2
GND
D3 3
MAXIMUM RATINGS (TJ = 25°C, unless otherwise specified)
Symbol
P3 MG
G
(Note: Microdot may be in either location)
Typical Applications
•
•
•
•
1
UDFN6 1.6x1.6
MU SUFFIX
CASE 517AP
6
Rating
Value
Unit
IPK
Peak Pulse Current
VCC Diode
8x20 msec double exponential waveform
5.0
A
TJ
Operating Junction Temperature Range
−40 to 125
°C
Device
TSTG
Storage Temperature Range
−55 to 150
°C
NUP3115UPMUTAG
TL
Lead Solder Temperature – Maximum
(10 seconds)
260
°C
ESD
IEC 61000−4−2 Contact
8000
V
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
6
VCC
5
NC
4
NC
ORDERING INFORMATION
Package
Shipping†
UDFN6 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2009
September, 2009− Rev. 1
1
Publication Order Number:
NUP3115UPMU/D
NUP3115UPMU
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
Working Peak Reverse Voltage
VC VBR VRWM
Maximum Reverse Leakage Current @ VRWM
VBR
Test Current
IF
Forward Current
VF
Forward Voltage @ IF
Ppk
Peak Power Dissipation
V
IR VF
IT
Breakdown Voltage @ IT
IT
C
IF
Parameter
IPP
Max. Capacitance @ VR = 0 and f = 1.0 MHz
Uni−Directional TVS
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (TJ = 25°C, unless otherwise specified)
Symbol
Min
Typ
Max
Unit
Reverse Working Voltage (D1, D2, and D3)
(Note 1)
Conditions
VRWM1
−
−
5.5
V
Reverse Working Voltage (VCC)
(Note 1)
VRWM2
−
−
12
V
Breakdown Voltage (D1, D2, and D3)
IT = 1 mA, (Note 2)
VBR
6.4
6.8
8.0
V
Breakdown Voltage (VCC)
IT = 1 mA, (Note 2)
VBR2
15
16
16.8
V
Reverse Leakage Current (D1, D2, and D3)
@ VRWM1
IR
−
−
1.0
mA
Reverse Leakage Current (D1, D2, and D3)
@ 3.3 V
IR
−
−
85
nA
Reverse Leakage Current (VCC)
@ VRWM2
IR
−
−
1.0
mA
Clamping Voltage (D1, D2, and D3)
IPP = 1 A
VC
−
9.4
−
V
Clamping Voltage (VCC)
IPP = 1 A
VC
−
18.5
−
V
Clamping Voltage (VCC)
IPP = 3 A
VC
−
22
−
V
Junction Capacitance (D1, D2, and D3)
VR = 0 V, f = 1 MHz (Line to GND)
CJ
−
0.8
1.0
pF
Clamping Voltage
Per IEC 61000−4−2 (Note 4)
VC
Parameter
Figure 1 and 2
V
1. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC
or continuous peak operating voltage level.
2. VBR is measured at pulse test current IT.
3. Surge current waveform per Figure 5.
4. Typical waveform. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
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2
NUP3115UPMU
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test
Voltage
(kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
% OF PEAK PULSE CURRENT
100
PEAK VALUE IRSM @ 8 ms
tr
90
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
80
70
60
HALF VALUE IRSM/2 @ 20 ms
50
40
30
tP
20
10
0
0
20
40
t, TIME (ms)
60
Figure 5. 8 X 20 ms Pulse Waveform
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3
80
NUP3115UPMU
PACKAGE DIMENSIONS
UDFN6, 1.6x1.6, 0.5P
CASE 517AP−01
ISSUE O
A
B
D
2X
0.10 C
PIN ONE
REFERENCE
2X
E
DETAIL A
OPTIONAL
CONSTRUCTION
0.10 C
A
(A3)
DETAIL B
0.05 C
A1
0.05 C
SIDE VIEW
DETAIL A
6X
C
A1
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
D2
E2
K
L
L1
MOLD CMPD
EXPOSED Cu
TOP VIEW
6X
L
L1
ÉÉÉ
ÉÉÉ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÉÉÉ
ÉÉÉ
A3
DETAIL B
OPTIONAL
CONSTRUCTION
SOLDERMASK DEFINED
MOUNTING FOOTPRINT*
D2
L
1
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.20
0.30
1.60 BSC
1.60 BSC
0.50 BSC
1.10
1.30
0.45
0.65
0.20
−−−
0.20
0.40
0.00
0.15
1.26
3
E2
6X
6X
K
6
5
6X
0.52
b
e
0.10 C A B
BOTTOM VIEW
0.05 C
NOTE 3
0.61 1.90
1
0.50 PITCH
6X
0.32
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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