NW6003 Type II Caller ID Decoder Data Sheet, January 2000 (Ver 2.0) File No. NW6003DS(L) 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567 Features Description ♦ The NW6003 device is a single-chip, 3/5 Volt CMOS caller ID and call waiting detection circuit. It can receive signals following Bellcore GR-30-CORE & SR-TSV-002476, BT SIN227 & SIN242, and CCA TW/P&E/312 specifications. ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 1200 baud Bell 202 and ITU-T V.23 Frequency Shift Keying (FSK) Demodulation Compliant with three specifications: Bellcore GR-30-CORE & SR-TSV-002476 British Telecom (BT) SIN227 & SIN242 Cable Communication Association (CCA) TW/P&E/312 Bellcore “CPE Alerting Signal (CAS)” and British Telecom “Idle State and Loop State Tone Alert Signal” detection Ring and line reversal detection High sensitivity with -40 dBV input Tone and FSK Detection Serial data interface to microcontroller 3 V ±10% or 5 V ±10% operation Low power CMOS with powerdown mode Operating temperature range: -40 °C to +85 °C Packages available: NW6003-XS 24 pin SOIC (where ‘X’ is the revision ID) TRIGIN OSCIN OSCOUT Oscillator The NW6003 provides 1200 baud Bell 202 and ITU-T V.23 FSK demodulation. It allows a microcontroller to extract data from it via a serial interface. In addition, the NW6003 offers Idle State and Loop State Tone Alert Signal and line reversal detection capability for BT CLIP, ring burst detection for the CCA CLIP, and ring and CAS detection for Bellcore CID. The device can be used in feature or cordless phones for BT Calling Line Identity Presentation (CLIP), CCA CLIP and Bellcore Calling Identity Delivery (CID) systems. It can also be used in caller ID boxes, modem, fax machines, answering machines, database query systems and Computer Telephony Integration (CTI) systems. TRIGRC TRIGOUT Line Reverse and Ring Detector 3 V/5 V Detector Interrupt Generator 1 Guard Time VREF CAP PWDN IN+ IN- Bias Generator Dual Tone Detector + - FSK Demodulator GS Figure-1. Integrated Device Technology, Inc. FSKEN Block Diagram INT STD ST/GT EST CD Data/Timing Recovery MODE DCLK DATA DR NW6003 Type II Caller ID Decoder Pin Information IN+ 1 24 VCC IN- 2 23 ST/GT GS 3 22 EST VREF 4 21 STD CAP 5 20 INT TRIGIN 6 19 CD TRIGRC 7 18 DR TRIGOUT 8 17 DATA MODE 9 16 DCLK OSCIN 10 15 FSKEN OSCOUT 11 14 PWDN GND 12 13 TM Figure-2. Pin Assignment Name IN+ INGS Type Pin No. Description I 1 Non-inverting Input of the gain adjustable op amp. I 2 Inverting Input of the gain adjustable op amp. O 3 Gain Select Output of the gain adjustable op amp. Select the op amp gain by adjusting the resistor ratio in the feed-back resistor network. VREF O 4 Reference Voltage. This output is used to bias the input op amp. It is typically VCC/2. CAP O 5 Capacitor Connector. A 0.1µF decoupling capacitor should be connected between this pin and GND. TRIGIN I 6 Trigger Input. This is a Schmitt trigger input used for ring detection and line reversal detection. TRIGRC I/O 7 Trigger Resistor and Capacitor Connector. This pin is connected to VCC and GND through resistor and capacitor. The RC value decides the time delay from TRIGIN going inactive (low) to TRIGOUT becoming inactive (high). See Fig.6 for reference. TRIGOUT O 8 Trigger Output. This is a Schmitt trigger buffer output indicating the detection of line reversal and/or ringing. MODE I 9 Serial FSK Interface MODE Select. A low level on this pin sets the interface to mode '0', while a high level sets it to mode '1'. OSCIN I 10 Oscillator Input. A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCOUT. It can also be driven by an external clock source. OSCOUT O 11 Oscillator Output. A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and and OSCIN. When OSCIN is driven by an external clock, this pin should be left floating. GND -12 Ground. TM I 13 Test Mode. Must be connected to GND for normal operation. Page-2 NW6003 Type II Caller ID Decoder Pin Information (Continued) Name Type Pin No. Description PWDN I 14 Power Down. This is an active high Schmitt trigger input. When active, the device enters a minimal power state by disabling all internal functional circuits except TRIGIN, TRIGRC and TRIGOUT. It must be low for normal operation. FSKEN I 15 FSK Enable. When this pin is high, FSK demodulation is enabled. This pin should be set low to disable the FSK demodulator from reacting to extraneous signals such as speech, alert signal etc. DCLK I/NC 16 Data Clock. In mode '0' (MODE pin low), this pin is unused. In mode '1' (MODE pin high), this pin is an input, Data Clock is provided by microcontroller. DATA O 17 Data Output. In mode '0', data appears on this pin once demodulated. In mode '1', data is shifted out on the rising edge of DCLK, which is supplied by microcontroller. DR O/NC 18 Data Ready Output. In mode '0', this pin is unused. In mode '1', this pin indicates to the microcontroller that 8-bit data is ready. Microcontroller initializes the DCLK signal to read out the data. CD O 19 FSK Carrier Detect . This is an active low CMOS output signal to indicate the presence of in-band FSK signal. INT OD 20 Interrupt. This is an active low open drain output. This pin is used to interrupt the microcontroller when TRIGOUT or DR is low, or STD is high. It remains low until all three signals become inactive. STD O 21 Dual Tone Alert Signal Delayed Steering Output. An active high signal to indicate the detection of a "guard time qualified" Dual Tone Alert Signal. EST O 22 Dual Tone Alert Signal Early Steering Output. This pin is an active high output to indicate the detection of Dual Tone Alert Signal. ST/GT I/O 23 Dual Tone Alert Signal Steering Input/Guard Time. It's a CMOS output and an input of voltage comparator. If the voltage at this pin is greater than voltage threshold (See Fig-6), STD is asserted high to indicate that a dual tone has been detected. A voltage less than threshold enables the device to accept a new dual tone. External RC are connected to EST and VCC pins. VCC -24 3/5 V Power Supply. Abbreviation Index CAS ----------------------------------------------------------CDS ----------------------------------------------------------CID -----------------------------------------------------------CIDCW ------------------------------------------------------CLIP ---------------------------------------------------------CNAM -------------------------------------------------------CND ---------------------------------------------------------CNIC --------------------------------------------------------CO ------------------------------------------------------------CTI ----------------------------------------------------------TE -------------------------------------------------------------- CPE Alerting Signal Caller Display Service Calling Identity Delivery Calling Identity Delivery on Call Waiting Calling Line Identity Presentation Calling Name Delivery Calling Number Delivery Calling Number Identification Circuit Central Office Computer Telephony Integration Terminal Equipment Page-3 NW6003 Type II Caller ID Decoder Functional Description Caller ID Specs Supported Block Description The NW6003 is a type II Caller ID device with Call Waiting capability. It supports Bellcore, BT and CCA specifications. The major differences between above specs are as follows (refer to Fig. 13, Fig. 14, Fig. 15, Fig. 16 and Fig. 17): The NW6003 requires a 3.579545 MHz system clock and consists of four major functional blocks: Analog Input Circuit, CLIP/CID Call Arrival Detection, Dual Tone Alert Signal Dectection, and FSK Demodulation. Bellcore Analog Input Circuit Bellcore GR-30-CORE and SR-TSV-002476 define the requirement for the signaling services of Calling Number Delivery (CND), Calling Name Delivery (CNAM) and Calling Identity Delivery on Call Waiting (CIDCW). The input signal is processed by the Analog Input Circuit block, which is comprised of an operational amplifier and a bias source (VREF). VREF is the output of a low impedance voltage source used to bias the input op amp, and is typically equal to VCC/2. The gain adjustable op amp is also used to select the input gain by connecting a feedback resistor between GS and the IN- pin. Fig. 3 shows the necessary connections with the A/B line inputs. In single-ended configuration, the gain adjustable op amp is connected as shown in Fig. 4. In CND or CNAM service, information of the calling party is embedded in the silent interval between the first and second ringings. The NW6003 can detect the first ringing and then demodulate the incoming Bell-202 FSK data. In CIDCW service, information about an incoming caller is sent to the subscriber who is engaged in another call. A CPE Alerting Signal (CAS) indicates that a CIDCW data is incoming. The NW6003 can detect the alerting signal and demodulate the incoming FSK information which contains CIDCW data. The demodulated data is output onto the serial interface. VREF NW6003 R3 British Telecom BT SIN227 and SIN242 define the signal interface between the Central Office (CO) and the Terminal Equipment (TE) for the Caller Display Service (CDS). CDS provides CLIP (Calling Line Identity Presentation) that delivers to an idle state (on hook) TE the identity of an incoming caller before the first ring. A polarity reversal on the A and B wires (see Fig. 6) indicates the arrival of a CDS call. After that comes an Idle State Tone Alert Signal, and then Caller ID FSK information transmitted in ITU-T V.23 format. When the subscriber is engaged in a call, the arrival of information about another incoming call is indicated by a Loop State Tone Alert Signal. The NW6003 can detect the line reversal and tone alert signal, it can also demodulate the incoming ITU-T V.23 FSK signals. C1 R1 Page-4 IN+ A INC2 R2 R5 B Differential Input Amplifier C1=C2 R1=R2 (For unity gain R5=R2) R3=(R4R5)/(R4+R5) GS Voltage Gain Av = R5/R1 Input Impedance Zin =2√R1²+ (1/ωC)² Figure-3. Differential Input Gain Control Circuit NW6003 C IN+ IN- Rin Input Cable Communication Association The CCA caller identity specification TW/P&E/312 defines a different CDS TE interface. In this specificaiton, data is transmitted after a single burst of ringing rather than before the first ringing cycle, as specified in the BT. The Idle State Tone Alert Signal is not required in this case. The CCA specifies that data can be transmitted in either Bell-202 or ITU-T V.23 format. The NW6003 can detect the ring burst, and then demodulate either of the FSK format. R4 Rf Voltage Gain Av = Rf / Rin GS VREF Figure-4. Single-ended Input Gain Control Circuit NW6003 Type II Caller ID Decoder CLIP/CID Call Arrival Detection Fig. 6 shows the typical application circuit to detect the CLIP/ CID call arrival signals. The diode bridge works for both single ended and balanced ring signals. R1 and R2 are used to set the maximum loading and must be of some value to achieve balanced loading. The ring signal is attenuated by R1, R3 and R4 resistor devider before being applied to pin TRIGIN. The attenuation value is determined by the detection of minimal ring voltage and maximum noise tolerance between Ring/Tip and ground. When no signal is applied to telephone line, TRIGIN will be at ground and pin TRIGOUT will stay inactive high. If TRIGIN increases from ground to VT+ (Schmitt trigger high going threshold voltage), C3 gets discharged, TRIGRC becomes low and TRIGOUT is asserted. The low going TRIGOUT can be used to interrupt or wake up the microcontroller. When TRIGIN signal drops below VT- (Schmitt trigger low going threshold voltage), C3 will start to charge up through R5C3 time constant. After TRIGRC pin reaches above the threshhold voltage (VT+), TRIGOUT becomes inactive high and it stops to interrupt the microcontroller. To ensure the minimum TRIGOUT low interval and to filter the ring signal to get a smooth envelope output, the RC time constant should be greater than the maximum cycle time of the Ring Signal. Ring Detection for Bellcore: Bellcore recommends that the CID FSK data be transmitted between first and second ringings. The circuit in Fig. 6 will generate a ring envelope signal at pin TRIGOUT for the ring voltage of 40 Vrms or greater. R5 and C3 are used to filter the ring signal to provide the envelope output. C1= 0.1 µF Ring Signal TRIGIN VT+ VT- TRIGRC VT+ TRIGOUT Figure- 5. TRIGIN, TRIGRC and TRIGOUT Operation Line Reversal Detection for BT: British Telecom uses the line polarity reverse (+15 V to -15V between the two lines slewing in 30 ms) to indicate the arrival of an incoming CDS call. When line reverse occurs, TRIGIN increases over VT+ and TRIGOUT signal becomes active low. When reversal is over, TRIGIN falls below VT- and TRIGOUT returns inactive high. Ring Burst Detection for CCA: The CCA requires the TE to detect a single burst of ringing followed by the FSK data. The ring pulse may varies from 30 to 75 Vrms with pulse duration 200 - 450 ms. R1 = 500K Tip/A NW6003 R3 = 200K TRIGIN Note: Minimal triggerable ring voltage (peak to peak) is: Vpp(max ring)= 2(VT+(max)(R1+R3+R4)/R4+0.7) R4 = 300K C2= 0.1 µF R2 = 500K R5 = 330K Ring/B TRIGRC N C3 = 0.22 µF Tolerance to noise between Tip/Ring and Vss is: Vmax noise= VT+(min)(R1+R3+R4)/R4+0.7 Suggested RC component value: 10K Ω < R5 < 500K Ω. 47 nF < C3 < 0.68 µF To Microcontroller Figure-6. TRIGOUT Time constant is: T=R5×C3×In(VCC/(VCC-VT+)) VT+(min) = 0.7 VCC VT+(max) = 0.5 VCC CLIP/CID Call Arrival Detection Circuit Page-5 NW6003 Type II Caller ID Decoder BT specifies a Dual Tone Alert Signal in both idle (on-hook) state and loop (off-hook) state, while Bellcore specifies a similar Dual Tone Alert Signal called CPE Alerting Signal (CAS) in off-hook state. The low and high tone frequencies of two different systems are as follows: Low Tone Frequency High Tone Frequency BT 2130 Hz ± 1.1% Bellcore 2130 Hz ± 0.5% 2750 Hz ± 1.1% 2750 Hz ± 0.5% The incoming Alert Signal goes through anti-alias filter and then is separated into high band and low band by two bandpass filters. The tone detection algorithm examines the filter outputs to validate the arrival of the Dual Tone Alert Signal. The EST pin becomes active when both tones are detected. The EST is only the preliminary indication, it must be qualified by the “guard time” as required by Bellcore and BT (a minimum duration for valid signals). STD is the guard time qualified CAS/Dual Tone Alert Signal detection output, it indicates the correct detection. Fig. 7 shows the operation of the guard time circuit and Fig. 8 shows the waveform of the EST, ST/GT and STD pins. The total recognition time is tREC = tDP + tGP, where tDP is the tone present detection time and tGP is the tone present guard time. The total absent time is tABS = tDA + tGA, where tDA is the tone absent detection time and tGA is the tone absent guard time. The guard time is the RC time constant for the capacitor charge to VCC or discharge to GND. To get the unequal present and absent guard time, a diode can be connected as shown in Fig. 9 to provide different RC time constant (varying resistance value) during charging and discharging. VCC C NW6003 Dual Tone Alert Signal Detection ST/GT R1 R2 EST VCC VCC VCC Dual tone detected Q1 P NW6003 C NW6003 tGP < tGA tGP=RPCIn((VCC-Vd(RP/R2))/ (VCC-VTGT-Vd(RP/R2))) tGA=R1CIn(VCC/VTGT) RP=R1R2/(R1+R2) Vd=diode forward voltage ST/GT R1 R2 tGP > tGA tGP=R1CIn(VCC/(VCC-VTGT)) tGA=RPCIn((VCC-Vd(RP/R2))/ (VTGT-Vd(RP/R2))) RP=R1R2/(R1+R2) Vd=diode forward voltage EST + - ST/GT VTGT Figure-9. Guard Time Circuits with Unequal Present and Absent Times Comparator Q2 N EST STD Figure-7. Guard Time Circuit of Dual Tone Alert Signal Detection Tip/ Ring Alerting Signal tDP EST tDA tGP tGA VTGT ST/GT VTGT tABS tREC STD Q1 Switch Q2 Switch ON ON Figure-8. Guard Time Waveform Page-6 ON NW6003 Type II Caller ID Decoder FSK Demodulation The key part among the functions offered by NW6003 is FSK demodulation. This function is implemented by several stages: first, the carrier detector provides an indication of the presence of signal at the bandpass filter output; second, the device’s dual mode serial interface allows convenient extraction of the 8-bit data words in the demodulated FSK bit stream. The FSK characteristics are different in BT and Bellcore specifications. The BT’s signal frequencies correspond to ITU-T V.23; the Bellcore frequencies correspond to Bell 202. The CCA requires that TE be able to receive both ITU-T V.23 and Bell 202 signals. The NW6003 is compatible with both formats. It also meets the signal characteristics by setting the input op amp at unity gain in 5 V operation. Mark Freq. (‘1’) Space Freq. (‘0’) ITU-T V.23 1300 Hz ± 1.5% Bell 202 1200 Hz ± 1% 2100 Hz ± 1.5% 2200 Hz ± 1% The Dual Tone Alert Signal, speech and DTMF tones are in the same frequency band as FSK, they will be demodulated and generate false data. To avoid it, FSKEN pin is used to disable the FSK modulation when FSK signal is not expected. FSK Carrier Detection The carrier detector provides an indication of the presence of a signal in the FSK frequency band. It detects the presence of a signal of sufficient amplitude at the output of the FSK bandpass filter. If the signal is qualified by a digital algorithm, the CD output becomes low to indicate carrier detection. An 8 ms hysteresis is provided to allow for momentary signal drop out once CD has been activated. And when there is no activity at the FSK bandpass filter output for 8 ms, CD is released. to external devices. This interface provides the mechanism to extract the 8-bit data words in the demodulated FSK bit stream. Two modes are selectable via control of the device’s MODE pin: Mode ‘0’ (MODE pin is low), where data transfer is initiated by the NW6003; Mode ‘1’ (MODE pin is high), where the data transfer is initiated by an external microcontroller. Mode ‘0’ In this mode, data transfer is initiated by the NW6003. The device demodulates the incoming FSK signal, and output the data directly to the DATA pin. Fig. 24 shows the timing diagram of Mode ‘0’ operation. Mode ‘1’ In this mode, the microcontroller supplies read pulses (DCLK) to shift the 8-bit data words out of the NW6003, onto the DATA pin. The NW6003 asserts DR to denote the word boundary and indicate to the microprocessor that a new word has become available. Internal to the device, the demodulated data bits are sampled and stored. After the 8th bit, the word is parallelly loaded into an 8-bit shift register and DR goes low. The contents of shift register are shifted out to DATA pin on DCLK’s rising edge with LSB (Least Significant Bit) out first. If DCLK begins while DR is low, DR will return to high upon the first DCLK. This feature allows the associated interrupt to be cleared by the first read pulse. Otherwise, DR stays low for half a nominal bit time (1/2400 sec) and then returns to high. After the last bit (Most Significant Bit) has been read, additional DCLKs are ignored. Fig. 22 shows the timing diagram of Mode ‘1’ operation. When CD is inactive (high), the raw output of the FSK demodulator is ignored by the FSK data output interface. In mode ‘0’, the DATA pin is forced high. In mode ‘1’, the internal shift register is not updated. No DR is generated. If DCLK is clocked, DATA is undefined. Serial FSK interface The three wire DATA, DCLK and DR form the data interface of the FSK demodulation. The DATA pin is the serial data pin that outputs data to external devices. The DCLK pin is the data clock which is generated by an external device. The DR pin is the data ready signal, also an output from the NW6003 Page-7 NW6003 Type II Caller ID Decoder Other Functions Power-down Mode The device provides the power down feature to reduce the power consumption. By activating the PWDN pin (high), the gain adjustable op amp, oscillator and all other internal circuits besides the ring detection circuit are all disabled. The TRIGIN, TRIGRC and TRIGOUT pins are not affected, the device can still react to call arrival indicator and activate the interrupt to wake up the microcontroller. Crystal Oscillator A 3.579545 MHz crystal oscillator or other external clock source is required for NW6003. The crystal can be directly connected between OSCIN and OSCOUT pins without any external component. If an external clock source is used, OSCIN pin should be driven by the clock source and OSCOUT pin is left floating or is used to drive other devices. Fig. 10 shows some applications. (a) Connection of One Device with Crystal Oscillator NW6003 OSCIN OSCOUT 12 12 12 12 12 12 3.579545MHz (b) Common Crystal Connection of Several Devices Sharing One Timing Source NW6003 OSCIN OSCOUT NW6003 OSCIN NW6003 OSCOUT OSCIN OSCOUT 12 12 12 12 12 3.579545MHz to the next device Figure-10. Applicaiton of Clock Driven Circuit Interrupt The NW6003 provides an open drain interrupt output INT to interrupt the microcontroller. Either TRIGOUT low, STD high or DR low will activate the INT and it will remain active ‘low’ until all of these three pins return to an inactive state. The microcontroller should read these pins through input ports to detect the interrupt type (TRIGOUT, STD or DR) and to make the correspondent response. Page-8 When the system is first powered up, TRIGOUT will be low (C3 at TRIGRC has no initial charge) and STD will be high if PWDN is low (no charge across the capacitor at ST/GT pin in Fig. 7), interrupt signal will be generated. The microcontroller should ignore interrupts from these sources on the initial power up until there is sufficient time to charge the capacitors. Also, by asserting PWDN high immediately after system power up, STD will become low and no interrupt will be generated. In power-down mode, EST and comparator output are forced low, the charging switch will turn on, and the capacitor at ST/GT pin will charge up more rapidly. Bias Voltage Generator The bias voltage generator provides a low impedance voltage source equal to VCC/2 on pin VREF and is used to bias the op amp. To reduce the noise, a 0.1 µF capacitor should be connected between CAP and GND pins. NW6003 Type II Caller ID Decoder data transmission, and Fig. 14 shows Bellcore off-hook data transmission. The BT operations are shown in Fig. 15 and Fig. 16, and the CCA operation in Fig. 17. Application Information Application Circuits 1.0 Fig. 11 shows the typical NW6003 application circuit. For 5 V operation, the gain ratio of the op amp is set to unity to optimize the electrical characteristics. As the power supply voltage drops, the threshold of tone and FSK detectors will be lower. To meet the BT and Bellcore tone reject level requirements, the gain of the op amp should be adjusted according to the graph in Fig. 12. Gain Ratio 0.9 0.8 0.7 0.678 It should be noted that the glitch with sufficient amplitude appears on the tip and ring interface will be falsely detected. One way to avoid such false detection is to use the photocoupler LED between the diode bridge and TRIGIN pin. 0.6 0.5 3 2 4 5 6 7 Nominal VCC(Volts) Bellcore/BT/CCA Applications Gain Ratio of op amp The NW6003 supports three specifications: Bellcore, BT and CCA. Fig. 13 shows the timing diagram of Bellcore on-hook = 464kΩ R1 + R4 Figure-12. Gain Ratio as a Function of Nominal VCC VCC VCC Tip/A 22 nF 5% R1 1% R4 1% NW6003 0.1 µF C 22 nF 5% R1' 1% VCC IN- ST/GT GS EST VCC VCC Ring/B IN+ 60K4 1% R4' 1% 53K6 1% 464K 1% R3 VREF STD CAP INT TRIGIN CD TRIGRC DR 0.1 µF R2 100K 0.1 µF 5% VCC 330K 500K 200K 0.1 µF 5% 500K 300K 0.22 µF 1234 1234 ♦ ♦ ♦ ♦ ♦ ♦ For VCC = 5V ±10%, R1 = R1’ = 430 kΩ, R4 = R4’ = 34 kΩ. For VCC = 3V ±10%, R1 = R1’ = 620 kΩ, R4 = R4’ = 63 k4. Resistor tolerance 5% and capacitor tolerance 10% unless otherwise specified. Crystal frequency 3.579545 MHz with 0.1%tolerance. For BT application, C = 0.1 µF ±5%, R2 = R3 = 422K ±1%. For Bellcore application, C = 0.1 µF ±5%, R2 = 266K ±1%, R3= 825K ±1%. TRIGOUT DATA MODE DCLK OSCIN FSKEN OSCOUT PWDN GND MICROCONTROLLER VCC TM Figure-11. Typical Application Circuit Page-9 NW6003 Type II Caller ID Decoder 1st Ringing Alerting Signal Ch. Seizure Mark Message 2nd Ringing A/B Wires A B C D E F Note 1 TRIGOUT INT ... PWDN Note 2 FSKEN Note 5 ... Note 2 Note 4 Note 3 CD DR ... ... DCLK DATA ..101010.. Data Figure-13. Bellcore On-hook Data Transmission Timing Diagram Notes: 1) A= 2 sec typ., B= 250 - 500 ms, C= 250 ms, D= 150ms, E depends on data length, Max C+D+E = 2.9 - 3.7 sec, F ≥ 200 ms. 2) In a battery operated CPE, NW6003 may be enabled only after the end of ringing to conserve power. 3) The microcontroller in the CPE powers down the NW6003 after CD goes inactive. 4) The microcontroller times out if CD is not activated on the 2nd ring and puts the device into Power-down mode. 5) FSKEN may be set always high while the CPE is on-hook. To prevent the FSK demodulator from reacting to other inband signals such as speech, CAS or DTMT tones. The designer may choose to set FSKEN low during the period that FSK signal is not expected. Page-10 NW6003 Type II Caller ID Decoder CPE mutes handset and disable keypad CPE off-hook A/B wires Note 2 CPE sends ACK CAS A CPE unmutes handset and enable keypad B C D Mark Message E F G Note 1 Note 3 PWDN Note 5 FSKEN Note 6 Note 4 STD INT ... CD DR ... DCLK DATA Data Figure-14. Bellcore Off-hook Data Transmission Timing Diagram Notes: 1) A= 75 - 85 ms, B= 0 -100 ms, C= 55 - 65 ms, D= 0 - 500 ms, E= 58 - 75ms, F depends on data length, G≤ 50 ms. 2) If AC power is not available, the designer may use the line power when the CPE goes off-hook and use battery power while on-hook. The CPE should also be CID (on-hook) capable . 3) If the end office fails to send the FSK signal, the CPE should disable FSKEN to unmute the handset and enable the keypad after this interval. 4) When FSK signal is not expected, the FSKEN pin should be set low to disable the FSK demodulator. 5) FSKEN should be high as soon as the CPE has finished sending the acknowledgement signal ACK. 6) FSKEN should be low when CD become inactive. Page-11 NW6003 Type II Caller ID Decoder Line Reversal Alerting Signal A/B Wires A B C Ch. Seizure Mark Message D E F Ring G Note 1 TRIGOUT INT ... ... PWDN STD TE DC load TE AC load 15 ±1 ms <120 µ A 20 ±5 ms Current Wetting Pulse 50 - 150 ms < 0.5 mA (optional) Note 2 Note 3 Zss Note 4 FSKEN CD DR ... ... DCLK DATA ..101010.. Data Figure-15. BT Idle State (on-hook) Data Transmission Timing Diagram Notes: 1) A≥ 100ms, B=88 - 110 ms, C≥ 45 ms (up to 5 sec), D= 80 -262 ms, E= 45 - 75 ms, F≤ 2.5 sec (typ. 500 ms), G≥ 200 ms. 2) By choosing tGA=15 ms, tABS will be 15-25 ms (refer to Fig. 8). Current wetting pulse and AC/DC load should be applied right after the STD falling edge. 3) AC and DC loads should be removed between 50-150 ms after the end of the FSK signal. The NW6003 may go to power down mode to save power. 4) FSKEN should be set low to disable the FSK demodulator, when the FSK signal is not expected. Page-12 NW6003 Type II Caller ID Decoder TE in loop state (off-hook) Speech path disabled Speech path restored Start Point A/B wires Alert Signal Note 2 A B ACK C D E Mark Message F G H Note 1 Note 3 PWDN Note 5 FSKEN Note 4 Note 6 STD INT ... CD DR ... DCLK DATA Data Figure-16. BT Loop State (Off-hook) Data Transmission Timing Diagram Notes: 1) A= 40 - 50 ms, B= 80 - 85 ms, C≤ 100 ms, D= 65 - 75 ms, E= 5- 100ms, F = 45 - 75 ms, G depends on data length, H ≤ 100 ms. 2) If AC power is not available, the designer may use the line power when the TE goes into loop state (off-hook) and use battery power while on-hook. 3) If the end office fails to send the FSK signal, the TE should disable FSKEN to unmute the handset and enable the keypad after this interval. 4) When FSK signal is not expected, the FSKEN pin should be set low to disable the FSK demodulator. 5) FSKEN should be high as soon as the TE has finished sending the acknowledgement signal ACK. 6) FSKEN should be low when CD become inactive. Page-13 NW6003 Type II Caller ID Decoder 1st Ring Ring Burst Alerting Signal Ch. Seizure Mark C D Data Packet A/B Wires A B E F Note 1 TRIGOUT Note 2 Note 2 INT PWDN 50 - 150 ms TE DC load 250 - 400 ms Note 3 TE AC load Note 4 FSKEN < 25 ms > 8 ms CD DR ... ... DCLK DATA ..100110.. Data Figure-17. CCA Caller Display Service Timing Diagram Notes: 1) A = 200 - 450 ms, B ≥ 500 ms, C= 80 - 262 ms, D= 45 -262 ms, E≤ 2.5 s (typ. 500 ms), F ≥ 200 ms. 2) TRIGout indicates the ring envelope. 3) AC and DC loads should be applied between 250 - 400 ms after the ring burst and should be removed between 50 to 150 ms after the end of FSK signal 4) FSKEN should be set low when FSK signal is not expected. Page-14 NW6003 Type II Caller ID Decoder Maximum Rating - Exceeding the following listed values may cause permament damage. Power Supply Voltage: -0.3 V to 7 V Voltage on any pin other than supplies: GND - 0.3 V to VCC + 1 V Current at any pin other than supplies: ≤ 20 mA Storage Temperature: -65 °C to +150 °C Recommended Operating Conditions Operating Temperature: -40 °C to +85 °C Power Supply Voltage: 3 V ± 10% or 5 V ± 10% Clock Frequency: 3.579545 MHz ± 0.1% Input Voltage: 0 V to VCC Crystal Specifications Frequency: 3.579545 MHz Resonancy tolerance: ± 0.1%( -40°C to +85°C) Resonance mode: Parallel Load capacitance: 18 pF Maximum series resistance: 150 Ω Maximum drive level(mW): 2 mW DC Electrical Characteristics Parameter Pin ICCS ICC VCC VT+ VTVHYS VIH VIL IOH TRIGIN TRIGRC PWDN DCLK MODE FSKEN TRIGOUT, DCLK DATA, DR, CD, STD EST, ST/GT Description Power Supply Standby Current Operating Supply Current VCC = 5 V ± 10% VCC = 3 V ± 10% Schmitt Trigger Input High Threshold Schmitt Trigger Input Low Threshold Schmitt Hysteresis CMOS Input High Voltage CMOS Input Low Voltage Output High Sourcing Current Min Typ Max Units 0.5 10 µA Test Conditions Test 1 Test2 2.5 1.8 0.5VCC 3.8 2.7 0.7VCC mA mA V 0.3VCC 0.5VCC V 0.2 0.7VCC VCC V V GND 0.3VCC V -0.8 mA VOH=0.9VCC Test 1: All inputs are VCC/GND except for oscillator pins. No analog input. Output unloaded. PWDN = VCC. Test 2: All inputs are VCC/GND except for oscillator pins. No analog input. Ouput unloaded. PWDN = GND, FEKEN = VCC. Page-15 NW6003 Type II Caller ID Decoder DC Electrical Characteristics (Continued) Parameter IOL IOZ1 Pin TRIGOUT, DCLK DATA, DR, CD STD, EST, ST/GT TRIGRC, INT IN+, IN-, TRIGIN PWDN, DCLK MODE, FSKEN TRIGRC IOZ2 IOZ3 VREF ST/GT INT VREF RREF VTGT ST/GT Iin1 Iin2 Description Output Low Sinking Current Max Units mA Test Conditions VOL = 0.1VCC Input Current Input Current 1 10 µA µA Vin = VCC to GND Output High Impedance Current 1 µA 5 10 0.5VCC+ 0.05 2 0.5VCC+ 0.05 µA µA V Output Voltage Output Resistance Comparator Threshold Voltage Min 2 Typ 0.5VCC0.05 0.5VCC0.05 Vout = VCC to GND No Load kΩ V AC Electrical Characteristics Dual Tone Alert Signal Detection Parameter FL FH FDA Description Low Tone Frequency High Tone Frequency Frequency Deviation Accept 1.1% FDR Frequency Deviation Reject 3.5% SIGAC Accept Signal Level per tone -40 -37.78 SIGRJ Reject Signal Level per tone TA Positive and Negative Twist Accept # Signal to Noise Ratio SNR # Twist = 20 log ( fH amplitude / fL amplitude ). Page-16 Min Typ 2130 2750 Max Units Hz Hz -2 0.22 -46 -43.78 7 dBV dBm dBV dBm dB 20 dB Notes Nominal frequency Nominal frequency Within this range, tones are accepted. Outside this range, tones are rejected. The gain setting as in Fig. 11. Production tested at 3 V ±10%, or 5V ±10%. Both tones have the same amplitude and at nominal frequencies. Band limited random noise 300-3400 Hz. Measurement valid only when tone is present. NW6003 Type II Caller ID Decoder AC Electrical Characteristics (Continued) Gain Adjustable Op Amp Parameter IIN RIN VOS PSRR CMRR AVOL fC VO CL RL VCM Description Input Leakage Current Input Resistance Input Offset Voltage Power Supply Rejection Ratio Common Mode Rejection DC Open Loop Voltage Gain Unity Gain Bandwidth Output Voltage Swing Maximum Capacitive Load (GS) Maximum Resistive Load (GS) Common Mode Range Voltage Min Typ Max 0.8 15 25 45 40 40 0.3 0.4 VCC -0.4 100 50 1.0 Units µA MΩ mV dB dB dB MHz V pF kΩ Test Conditions GND ≤ VIN ≤ VCC 1kHz ripple on VCC VCMmin ≤ VIN ≤ VCMmax Load ≥ 50 kΩ VCC-1.0 FSK Detection Parameter ID TR FMARK FSPACE FMARK FSPACE SNR Description Input Detection Level Min -40 -37.78 10.0 Typ Max -8 -5.78 398.1 Units dBV dBm mVrms Transmission Rate Input Frequency Detection Bell 202 ‘1’ (mark) Input Frequency Detection Bell 202 ‘0’ (space) Input Frequency Detection ITU-T V.23 ‘1’ (mark) Input Frequency Detection ITU-T V.23 0 (space) Signal to Noise Ratio 1188 1188 1200 1200 1212 1212 baud Hz 2178 2200 2222 Hz 1280.5 1300 1319.5 Hz 2068.5 2100 2131.5 Hz 20 dB Notes Production tested at VCC =3V ±10%, or 5V ±10%. Both mark and space have the same amplitude. Both mark and space have the same amplitude and at nominal frequencies. Band limited random noise: 200-3400 Hz. Present only when FSK signal is present. # # BT band is 200-3400 Hz, while Bellcore band is 0-4 kHz. Notes: dBV = decibels above or below a reference voltage of 1 Vrms. dBm = decibels above or below a reference power of 1 mW into 600 ohms, 0 dBm = 0.7746 Vrms. Page-17 NW6003 Type II Caller ID Decoder AC Timing Characteristics Power Up/Down and FSK Detection Parameter t1 t2 t3 t4 t5 Description Power Up Time Power Down Time Input FSK to CD low delay Input FSK to CD high delay Hysteresis Min Typ Max 50 1 25 Units ms ms ms ms ms Test Conditions Typ Max 10 8 Units ms ms Test Conditions 8 8 Dual Tone Alert Signal Parameter t6 t7 Description Alert Signal Present Detect Time Alert Signal Absent Detect Time Min 0.5 0.1 PWDN OSCOUT t1 t2 Figure-18. Power Up/Down Timing Tip/Ring FSK Signal CD t3 t4 Figure-19. FSK Detection Time Tip/Ring Alert Signal EST t6 Figure-20. Dual Tone Alert Signal Detection Time Page-18 t7 NW6003 Type II Caller ID Decoder AC Timing Characteristics (Continued) Serial Interface (Mode ‘1’) Parameter t11 t12 t13 t14 t15 t16 t17 Description DCLK Cycle Time DCLK High Time DCLK Low Time DCLK Rise Time DCLK Fall Time DCLK Low Setup to DR DCLK Low Hold Time after DR Min 1 0.3 0.3 Typ Max Units µs µs µs ns ns ns ns 20 20 500 500 t13 Test Conditions t12 DCLK t14 t15 t11 Figure-21. DCLK Timing in Mode ‘1’ Nth byte Internal Demodulated Bit Stream b7 (N+1)th byte stop DR t16 start b0 b1 b2 b3 b4 b5 note 1 b6 b7 stop start note 2 t17 DCLK DATA b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 Nth byte (N-1)th byte Figure-22. Serial Data Interface Timing in MODE ‘1’ Notes: 1. DCLK clears DR. 2. DR not cleared by DCLK, low for a maximum time of 1/2 bit width. Page-19 NW6003 Type II Caller ID Decoder Serial Interface (Mode ‘0’) Parameter DR t21 t22 t23 Description Data Rate Input FSK to DATA Delay DATA Rise Time DATA Fall Time Min 1188 Typ 1200 1 Max 1212 5 200 200 Units baud ms ns ns Test Conditions 1 2 2 Test conditions: 1. FSK input data at 1200 ± 12 buad. 2. Load of 50 pF. DATA t22 t23 Figure-23. DATA Output Timing in Mode ‘0’ TIP/RING b7 start Nth byte 0 b0 b1 b2 b3 b4 b5 b6 b7 1 (N+1)th byte stop start 1 0 b0 b1 b2 b3 b4 b5 b6 b7 stop start 1 0 b0 b1 t21 start DATA b7 Nth byte start b0 b1 b2 b3 b4 b5 b6 b7 (N+1)th byte b0 b1 b2 b3 b4 b5 b6 b7 stop Figure-24. Serial Data Interface Timing in MODE ‘0’ Page-20 start b0 b1 b2 stop NW6003 Type II Caller ID Decoder 0.406 ± 0.010 in Millimeters 0.298 ± 0.003 Physical Dimensions Notes: 1) All dimensions in inches 2) Form radius MIN. .010 but not to exceed .030 3) Lead tip coplanarityafter form to be within .004 4) REF. JEDEC MS-13 0.018 Typ. 0.015 × 45 DEG 0.604 ± 0.005 0.008 ± 0.003 0.101 ± 0.003 5 DEG Ty p. Typ. 0.016 Min. 0.050 Max. Figure-25. NW6003-XS 24 Pin SOIC Package Diagram Page-21