ETC NX25P40 1m bit 2m bit and 4m bit serial flash memory with 10mhz spi Datasheet

PRELIMINARY
APRIL 2005
1M-BIT, 2M-BIT AND 4M-BIT
Serial Flash Memory with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
1
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Table of Contents
NX25P10, NX25P20 AND NX25P40
1M-BIT, 2M-BIT AND 4M-BIT Serial Flash Memory with 40MHz SPI ........................................................................... 1
FEATURES ..................................................................................................................................................................... 4
GENERAL DESCRIPTION ............................................................................................................................................. 4
8-Pin SOIC 150-mil (Package Code N) .......................................................................................................................... 4
Figure 1. NX25P10, NX25P20 and NX25P40 Block Diagram .................................................................................... 5
PIN DESCRIPTIONS ...................................................................................................................................................... 6
Package Types ......................................................................................................................................................... 6
Serial Data Input (DI) ................................................................................................................................................ 6
Serial Data Output (DO) ............................................................................................................................................ 6
Serial Clock (CLK) .................................................................................................................................................... 6
Chip Select (CS) ....................................................................................................................................................... 6
Hold (HOLD) ............................................................................................................................................................. 6
Write Protect (WP) .................................................................................................................................................... 6
Figure 2. NX25P10, NX25P20 and NX25P40 Pin Assignments, 8-pin SOIC (Package Code N) ................................ 6
Table 1. Pin Descriptions .......................................................................................................................................... 6
SPI OPERATION ............................................................................................................................................................ 7
SPI Modes ............................................................................................................................................................... 7
Hold Function ........................................................................................................................................................... 7
WRITE PROTECTION .................................................................................................................................................... 7
Write Protect Features .............................................................................................................................................. 7
STATUS REGISTER ....................................................................................................................................................... 8
BUSY ....................................................................................................................................................................... 8
Write Enable Latch (WEL) ......................................................................................................................................... 8
Figure 3. Status Register Bit Locations ..................................................................................................................... 8
Block Protect Bits (BP2, BP1, BP0) ......................................................................................................................... 8
Reserved Bits ........................................................................................................................................................... 8
Status Register Protect (SRP) .................................................................................................................................. 8
Table 2: Status Register Memory Protection ............................................................................................................. 9
INSTRUCTIONS ........................................................................................................................................................... 10
Table 3: Instruction Set ........................................................................................................................................... 10
Table 4: Manufacturer and Device Identification ...................................................................................................... 10
Write Enable (06h) .................................................................................................................................................... 11
Figure 4. Write Enable Instruction Sequence Diagram ............................................................................................. 11
Write Disable (04h) ................................................................................................................................................... 11
Figure 5. Write Disable Instruction Sequence Diagram ............................................................................................ 11
Read Status Register (05h) ...................................................................................................................................... 12
Figure 6. Read Status Register Instruction Sequence Diagram ............................................................................... 12
Write Status Register (01h) ...................................................................................................................................... 13
Figure 7. Write Status Register Instruction Sequence Diagram ............................................................................... 13
Read Data (03h) ........................................................................................................................................................ 14
Figure 8. Read Data Instruction Sequence Diagram ................................................................................................ 14
2
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Table of Contents
Fast Read (0Bh) ........................................................................................................................................................ 15
Figure 9. Fast Read Instruction Sequence Diagram ................................................................................................ 15
Page Program (02h) ................................................................................................................................................. 16
Figure 10. Page Program Instruction Sequence Diagram ........................................................................................ 16
Sector Erase (D8h) ................................................................................................................................................... 17
Figure 11. Sector Erase Instruction Sequence Diagram .......................................................................................... 17
Bulk Erase (C7h) ...................................................................................................................................................... 18
Figure 12. Bulk Erase Instruction Sequence Diagram ............................................................................................. 18
Power-down (B9h) .................................................................................................................................................... 19
Figure 13. Deep Power-down Instruction Sequence Diagram ................................................................................... 19
Release Power-down / Device ID (ABh) ................................................................................................................... 20
Figure 14. Release Power-down Instruction Sequence ............................................................................................ 20
Figure 15. Release Power-down / Device ID Instruction Sequence Diagram ............................................................ 20
Read Manufacturer / Device ID (90h) ....................................................................................................................... 21
Figure 16. Read Manufacturer / Device ID Diagram ................................................................................................ 21
SPECIFICATIONS AND TIMING DIAGRAMS ............................................................................................................... 22
Table 5. Absolute Maximum Ratings ....................................................................................................................... 22
Table 6. Operating Ranges ...................................................................................................................................... 22
Table 7. Power-up Timing and Write Inhibit Threshold .............................................................................................. 22
Figure 17. Power-up Timing and Voltage Levels ....................................................................................................... 22
Table 8. DC Electrical Characteristics (Preliminary) ................................................................................................ 23
Table 9. AC Measurement Conditions ..................................................................................................................... 23
Figure 18. AC Measurement I/O Waveform ............................................................................................................. 23
Table 10. AC Electrical Characteristics (Preliminary) ............................................................................................... 24
Figure 19. Serial Output Timing ............................................................................................................................... 25
Figure 20. Input Timing ........................................................................................................................................... 25
Figure 21. Hold Timing ............................................................................................................................................ 25
PACKAGING INFORMATION ........................................................................................................................................ 26
8-Pin SOIC 150-mil (Package Code N) ....................................................................................................................... 26
PRELIMINARY DESIGNATION .................................................................................................................................... 27
1
2
3
4
5
6
7
8
9
IMPORTANT NOTICE ................................................................................................................................................... 27
ORDERING INFORMATION ......................................................................................................................................... 27
LIFE SUPPORT POLICY ............................................................................................................................................. 27
10
TRADEMARKS ............................................................................................................................................................. 27
Document Revision History ........................................................................................................................................ 28
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12
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
3
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
FEATURES
GENERAL DESCRIPTION
•
The NX25P10 (1M-bit), NX25P20 (2M-bit) and NX25P40
(4M-bit) Serial Flash memories provide a storage solution
for systems with limited space, pins and power. They are
ideal for code download applications as well as storing
voice, text and data. The devices operate on a single 2.7V
to 3.6V power supply with current consumption as low as
4mA active and 1µA for power-down. All devices are offered
in space-saving 8-pin SOIC type packages as shown
below. Contact NexFlash for availability of alternate packages. As part of a family of Serial Flash products,
NexFlash also provides a compatible migration path to 8M/
16M/32M-bit densities.
1M / 2M / 4M-bit Serial Flash Memories
• Family of Serial Flash Memories
– NX25P10: 1M-bit / 128K-byte (131,072 ) 512 pages
– NX25P20: 2M-bit / 256K-byte (262,144 ) 1024 pages
– NX25P40: 4M-bit / 512K-byte (524,288 ) 2048 pages
– 256-bytes per programmable page
– Compatible migration path to 8M/16M/32M-bit
• 4-pin SPI Serial Interface
– Clock, Chip Select, Data In, Data Out
– Easily interfaces to popular microcontrollers
– Compatible with SPI Modes 0 and 3
– Optional Hold function for SPI flexibility
• Low Power Consumption, Wide Temperature Range
– Single 2.7 to 3.6V supply
– 4mA active current, 1µA Power-down (typ)
– -40° to +85°C operating range
• Fast and Flexible Serial Data Access
– Clock operation to 40MHz Fast Read, 33MHz
Standard Read
– Byte-addressable Read and Program
– Auto-increment Read capability
– Manufacturer and Device ID
• Programming Features
– Page program up to 256 bytes <2ms
– Sector Erase (64K-byte) 2 seconds
– Chip erase: 3 seconds (25P10/20),
5 seconds (25P40)
– 100,000 erase/write cycles
– Twenty year data retention
• Software and Hardware Write Protection
– Write-Protect all or portion of memory via software
– Enable/Disable protection with WP pin
The NX25P10/20/40 array is organized into 512/1024/2048
programmable pages of 256-bytes each. A single byte or,
up to 256 bytes, can be programmed at a time using the
Page Program instruction. Pages are grouped into 2/4/8
erasable sectors of 256 pages (64K-byte) each as shown in
figure 1. Both Sector Erase and Bulk (full chip) Erase
instructions are supported.
The Serial Peripheral Interface (SPI) consists of four pins
(Serial Clock, Chip Select, Serial Data In and Serial Data
Out) that support high speed serial data transfers up to
40MHz. A Hold pin, Write Protect pin and programmable
write protect features provide further control flexibility.
Additionally, the device can be queried for manufacturer
and device ID. Special customer ID (for copy authentication) and factory programming is available, contact NexFlash for more information.
8-Pin SOIC 150-mil
(Package Code N)
• Space Saving Package
– Tiny 8-pin SOIC
• Ideal for systems with limited pins, space, and power
– ASIC and Controller-based serial code-download
– Microcontroller systems storing data, text or voice
– Battery-operated and portable products
4
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
1
Serial Flash Memory Array
07FF00h
07FFFFh
2
Sector 7
070000h
0700FFh
06FF00h
06FFFFh
Sector 6
060000h
0600FFh
05FF00h
05FFFFh
3
0500FFh
04FF00h
04FFFFh
4
Sector 4
040000h
0400FFh
03FF00h
03FFFFh
5
NX25P40
Row Decode
Write Protect Logic
Sector 5
050000h
Sector 3
Write Control
Logic
02FFFFh
6
0200FFh
01FF00h
01FFFFh
7
NX25P20
020000h
Sector 1
High-voltage
Generators
HOLD
CS
02FF00h
Sector 2
Status
Register
CLK
0300FFh
Page Address
Latch / Counter
SPI
Comand and
Control Logic
010000h
0100FFh
00FF00h
00FFFFh
Sector 0*
000000h
8
NX25P10
WP
030000h
0000FFh
Begining
Page Address
9
Ending
Page Address
10
Column Decode
and 256 Byte Page Buffer
Data
DI
Byte Address
Latch / Counter
DO
11
* Every Sector Consists of 256 Pages of 256 Bytes Each
12
Figure 1. NX25P10, NX25P20 and NX25P40 Block Diagram
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
5
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
PIN DESCRIPTIONS
Package Types
The standard package for the NX25P10/20/40 is an 8-pin
plastic SOIC with 150 mil body (NexFlash package code N).
It also allows a package migration path to higher density
Serial Flash devices. The pinout for the “N” package is
shown in Figure 2. Package diagrams and dimensions are
illustrated at the end of this data sheet. Optional 8-contact
MLP packages may be available. Please contact NexFlash
for further MLP package information.
Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for
instructions, addresses and data to be serially written to
(shifted into) the device. Data is latched on the rising edge
of the Serial Clock (CLK) input pin.
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for
data and status to be serially read from (shifted out of) the
device. Data is shifted out on the falling edge of the Serial
Clock (CLK) input pin.
WP
Write Protect (WP
WP)
The Write Protect (WP) pin can be used to prevent the
Status Register from being written. Used in conjunction with
the Status Register’s Block Protect (BP0 and BP1) bits and
Status Register Protect (SRP) bits, a portion or the entire
memory array can be hardware protected. The WP pin is
active low.
CS
1
8
VCC
DO
2
7
HOLD
WP
3
6
CLK
GND
4
5
DI
Figure 2. NX25P10, NX25P20 and NX25P40 Pin
Assignments, 8-pin SOIC (Package Code N)
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for
serial input and output operations. ("See SPI "Operations")
Table 1. Pin Descriptions
CS
Chip Select (CS
CS)
The SPI Chip Select (CS) pin enables and disables device
operation. When CS is high the device is deselected and the
Serial Data Output (DO) pin is at high impedance. When
deselected, the devices power consumption will be at
standby levels unless an internal erase, program or status
register cycle is in progress. When CS is brought low the
device will be selected, power consumption will increase to
active levels and instructions can be written to and data read
from the device. After power-up, CS must transition from
high to low before a new instruction will be accepted. The CS
input must track the Vcc supply level at power-up (see
“Write Protection” and figure 17). If needed a pull-up resister
on CS can be used to accomplish this.
DI
DO
CLK
CS
WP
HOLD
Vcc, GND
Data Input
Data Output
Serial Clock Input
Chip Select Input
Write Protect Input
Hold Input
Power Supply
HOLD
Hold (HOLD
HOLD)
The HOLD pin allows the device to be paused while it is
actively selected. When HOLD is brought low, while CS is
low, the DO pin will be at high impedance and signals on the
DI and CLK pins will be ignored (don’t care). When
HOLD is brought high, device operation can resume. The
hold function can be useful when multiple devices are
sharing the same SPI signals. (“See Hold function”)
6
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
SPI OPERATION
SPI Modes
The NX25P10/20/40 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip
Select (CS), Serial Data Input (DI) and Serial Data Output
(DO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1) are
supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when
the SPI bus master is in standby and data is not being
transferred to the Serial Flash. For Mode 0 the CLK signal
is normally low. For Mode 3 the CLK signal is normally high.
In either case data input on the DI pin is sampled on the
rising edge of the CLK. Data output on the DO pin is clocked
out on the falling edge of CLK.
Write Protect Features
Hold Function
The HOLD signal allows the NX25P10/20/40 operation to be
paused while it is actively selected (when CS is low). The
hold function may be useful in cases where the SPI data and
clock signals are shared with other devices. For example,
consider if the page buffer was only partially written when a
priority interrupt requires use of the SPI bus. In this case the
hold function can save the state of the instruction and the
data in the buffer so programming can resume where it left
off once the bus is available again.
Upon power-up or at power-down the NX25P10/20/40 will
maintain a reset condition while Vcc is below the threshold
value of VWI, (See Power-up Timing and Voltage Levels:
Table 7 and Figure 17). While reset, all operations are
disabled and no instructions are recognized. During powerup and after the Vcc voltage exceeds VWI, all program and
erase related instructions are further disabled for a time
delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Bulk Erase and the Write Status
Register instructions. Note that the chip select pin (CS)
must track the Vcc supply level at power-up until the Vccmin level and tVSL time delay is reached. If needed a pull-up
resister on CS can be used to accomplish this.
To initiate a hold condition, the device must be selected with
CS low. A hold condition will activate on the falling edge of
the HOLD signal if the CLK signal is already low. If the CLK
is not already low the hold condition will activate after the
next falling edge of CLK. The hold condition will terminate
on the rising edge of the hold signal if the CLK signal is
already low. If the CLK is not already low the hold condition
will terminate after the next falling edge of CLK.
During a hold condition, the Serial Data Output (DO) is high
impedance, and Serial Data Input (DI) and Serial Clock
(CLK) are ignored. The Chip Select (CS) signal should be
kept active (low) for the full duration of the hold operation to
avoid resetting the internal logic state of the device.
WRITE PROTECTION
Applications that use non-volatile memory must take into
consideration the possibility of noise and other adverse
system conditions that may compromise data integrity. To
address this concern the NX25P10/20/40 provides several
means to protect data from inadvertent writes.
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
1
• Device resets when Vcc is below threshold.
• Time delay write disable after Power-up.
• Write enable/disable instructions.
2
• Automatic write disable after program and erase.
• Software write protection using Status Register.
• Hardware write protection using Status Register and
WP pin.
3
• Write Protection using Power-down instruction.
After power-up the device in automatically placed in a writedisabled state with the Status Register Write Enable Latch
(WEL) set to a 0. A Write Enable instruction must be issued
before a Page Program, Sector Erase, Bulk Erase or Write
Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable
Latch (WEL) is automatically cleared to a write-disabled state
of 0.
Software controlled write protection is facilitated using the
Write Status Register instruction and setting the Status
Register Protect (SRP) and Block Protect (BP0, BP2) bits.
These Status Register bits allow a portion or all of the
memory to be configured as read only. Used in conjunction
with the Write Protect (WP) pin, changes to the Status
Register can be enabled or disabled under hardware control.
See Status Register for further information.
Additionally, the Power-down instruction offers an extra
level of write protection as all instructions are ignored
except for the Release Power-down instruction.
7
4
5
6
7
8
9
10
11
12
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
STATUS REGISTER
The Read Status Register instruction can be used to provide
status on the availability of the Flash memory array, if the
device is write enabled or disabled, and the state of write
protection. The Write Status Register instruction can be
used to configure the devices write protection features. See
Figure 3.
BUSY
BUSY is a read only bit in the status register (S0) that is set
to a 1 state when the device is executing a Page Program,
Sector Erase, Bulk Erase or Write Status Register instruction. During this time the device will ignore further instructions except for the Read Status Register instruction (see
tW, tPP, tSE and tBE in AC Characteristics). When the
program, erase or write status register instruction has
completed, the BUSY bit will be cleared to a 0 state
indicating the device is ready for further instructions.
Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status
register (S1) that is set to a 1 after executing a Write Enable
Instruction. The WEL status bit is cleared to a 0 when the
device is write disabled. A write disable state occurs upon
power-up or after any of the following instructions: Write
Disable, Page Program, Sector Erase, Bulk Erase and
Write Status Register.
S7
SRP
S6
Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile
read/write bits in the status register (S4, S3, S2) that provide
Write Protection control and status. Block Protect bits can
be set using the Write Status Register Instruction (see tW
in AC characteristics). All, none or a portion of the memory
array can be protected from Program and Erase instructions
(see table 2). The factory default setting for the Block
Protection Bits is 0, none of the array protected. The Block
Protect bits can not be written to if the Status Register
Protect (SRP) bit is set to 1 and the Write Protect (WP) pin
is low. The NX25P20 and NX25P10 do not use BP2.
Reserved Bits
Status register bit locations 5 and 6 are reserved for future
use. Current devices will read 0 for these bit locations. It is
recommended to mask out the reserved bit when testing the
Status Register. Doing this will ensure compatibility with
future devices.
Status Register Protect (SRP)
The Status Register Protect (SRP) bit is a non-volatile read/
write bit in the status register (S7) that can be used in
conjunction with the Write Protect (WP) pin to disable writes
to the status register. When the SRP bit is set to a 0 state
(factory default) the WP pin has no control over the status
register. When the SRP pin is set to a 1, the Write Status
Register instruction is locked out while the WP pin is low.
When the WP pin is high the Write Status Register instruction is allowed.
S5
(Reserved)
S4
S3
S2
BP2
BP1
BP0
S1
S0
WEL BUSY
Status RegisterProtect
(Non-volatile)
Block Protect Bits
(Non-volatile)
Write Enable Latch
Device Busy
Erase Program or Write in Progress
Figure 3. Status Register Bit Locations
8
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Table 2: Status Register Memory Protection
Status Register (1)
BP2 BP1 BP0
Sector(s)
0
0
0
NONE
NONE
NONE
NONE
0
0
1
7
070000h - 07FFFFh
512K-bit
Upper 1/8
0
1
0
6 and 7
060000h - 07FFFFh
1M-bit
Upper 1/4
0
1
1
4 thru 7
040000h - 07FFFFh
2M-bit
Upper 1/2
1
x
x
ALL
000000h - 07FFFFh
4M-bit
ALL
NX25P40 (4M-bit) Memory Protection
Addresses
Density
1
Portion
2
3
Status Register (1)
BP2 BP1 BP0
Sector(s)
x
0
0
NONE
NONE
NONE
NONE
x
0
1
3
030000h - 03FFFFh
512K-bit
Upper 1/4
x
1
0
2 and 3
020000h - 03FFFFh
1M-bit
Upper 1/2
x
1
1
ALL
000000h - 03FFFFh
2M-bit
ALL
5
Portion
6
NX25P20 (2M-bit) Memory Protection
Addresses
Density
Portion
Status Register (1)
BP2 BP1 BP0
Sector(s)
x
0
x
NONE
NONE
NONE
NONE
x
1
0
NONE
NONE
NONE
NONE
x
1
1
ALL
000000h - 01FFFFh
1M-bit
ALL
NX25P10 (1M-bit) Memory Protection
Addresses
Density
4
7
Notes:
1. x = don't care.
8
9
10
11
12
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
9
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
INSTRUCTIONS
The instruction set of the NX25P10/20/40 consists of
twelve basic instructions that are fully controlled through the
SPI bus (see Table 3). Instructions are initiated with the
falling edge of Chip Select (CS). The first byte of data
clocked into the DI input provides the instruction code. Data
on the DI input is sampled on the rising edge of clock with
most significant bit (MSB) first.
feature further protects the device from inadvertent writes.
Additionally, while the memory is being programmed or
erased, or when the Status Register is being written, all
instructions except for Read Status Register will be ignored
until the program or erase cycle has completed.
Instructions vary in length from a single byte to several
bytes and may be followed by address bytes, data bytes,
dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising edge of edge
CS. Clock relative timing diagrams for each instruction are
included in figures 5 through 17. All read instructions can be
completed after any clocked bit. However, all instructions
that Write, Program or Erase must complete on a byte
boundary (CS driven high after a full 8-bits have been
clocked) otherwise the instruction will be terminated. This
Table 4: Manufacturer and Device Identification
Manufacturer ID
(M7-M0)
NexFlash
EFh
Device ID
(ID7-ID0)
NX25P10
10h
NX25P20
11h
NX25P40
12h
Table 3: Instruction Set (1)
Instruction Name
Byte 1
Code
Write Enable
Write Disable
Read Status Register
Write Status Register
Read Data
Fast Read
06h
04h
05h
01h
03h
0Bh
Page Program
Sector Erase
Bulk Erase
Power-down
Release Power-down
and Device ID
Manufacturer/Device ID
Byte 2 (5)
Byte 3
Byte 4
Byte 5
Byte 6
(S7–S0)(1)
S7–S0
A23–A16
A23–A16
A15–A8
A15–A8
A7–A0
A7–A0
(D7–D0)
dummy
(Next byte)
(D7–D0)
02h
D8h
C7h
B9h
ABh
A23–A16
A23–A16
A15–A8
A15–A8
A7–A0
A7–A0(6)
(D7–D0)
(Next byte)
dummy
dummy
dummy
(ID7-ID0)
90h
dummy
dummy
00h
(M7-M0)
n-Bytes
(2)
continuous
(Next Byte)
continuous
up to 256 bytes
(3)
(ID7-ID0)
(4)
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from
the device on the DO pin.
2. The Status Register contents will repeat continuously until CS terminate the instruction.
3. The Device ID will repeat continuously until CS terminate the instruction.
4. The Manufacturer ID and Device ID bytes will repeat continuously until CS terminate the instruction.
5. Unused upper address bits must be set to a 0 for the NX25P10.
6. The lowest 16 address bits (A15-A0) must be set to 0.
10
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Write Enable (06h)
The Write Enable instruction is entered by driving CS low,
shifting the instruction code “06h” into the Data Input (DI) pin
on the rising edge of CLK, and then driving CS high.
The Write Enable instruction (Figure 4) sets the Write
Enable Latch (WEL) bit in the Status Register to a 1. The
WEL bit must be set prior to every Page Program, Sector
Erase, Bulk Erase and Write Status Register instruction.
1
2
CS
Mode 3
CLK
0
1
2
3
4
5
6
3
7
Mode 0
Instruction (06h)
4
DI
High Impedance
DO
5
Figure 4. Write Enable Instruction Sequence Diagram
6
7
Write Disable (04h)
driving CS high. Note that the WEL bit is automatically reset
after Power-up and upon completion of the Write Status
Register, Page Program, Sector Erase, and Bulk Erase
instructions.
The Write Disable instruction (Figure 5) resets the Write
Enable Latch (WEL) bit in the Status Register to a 0. The
Write Disable instruction is entered by driving CS low,
shifting the instruction code “04h” into the DI pin and then
8
9
CS
10
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 0
11
Instruction (04h)
DI
High Impedance
12
DO
Figure 5. Write Disable Instruction Sequence Diagram
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
11
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Read Status Register (05h)
The Read Status Register instruction allows the 8-bit Status
Register to be read. The instruction is entered by
driving CS low and shifting the instruction code “05h” into the
DI pin on the rising edge of CLK. The status register bits are
then shifted out on the DO pin at the falling edge of CLK with
most significant bit (MSB) first as shown in figure 6. The
Status Register bits are shown in figure 3 and include the
BUSY, WEL, BPO-BP2, and STP bits (see description of
the Status Register earlier in this data sheet).
The Status Register instruction may be used at any time,
even while a Program, Erase or Write Status Register cycle
is in progress. This allows the BUSY status bit to be
checked to determine when the cycle is complete and if the
device can accept another instruction. The Status Register
can be read continuously, as shown in Figure 6. The
instruction is completed by driving CS high.
CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16
17 18
19 20 21 22 23
Mode 0
Instruction (05h)
DI
Status Register Out
DO
High Impedance
7
*
*
6
5
4
3
2
Status Register Out
1
0
7
6
5
4
3
2
1
0
7
*
= MSB
Figure 6. Read Status Register Instruction Sequence Diagram
12
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
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1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Write Status Register (01h)
The Write Status Register instruction allows the Status
Register to be written. A Write Enable instruction must
previously have been executed for the device to accept the
Write Status Register Instruction (Status Register bit WEL
must equal 1). Once write enabled, the instruction is entered
by driving CS low, sending the instruction code “01h”, and
then writing the status register data byte as illustrated in
figure 7. The Status Register bits are shown in figure 3 and
described earlier in this data sheet.
While the Write Status Register cycle is in progress, the
Read Status Register instruction may still accessed to
check the status of the BUSY bit. The BUSY bit is a 1 during
the Write Status Register cycle and a 0 when the cycle is
finished and ready to accept other instructions again. After
the Write Register cycle has started the Write Enable Latch
(WEL) bit in the Status Register will be cleared to 0.
The Write Status Register instruction allows the Block
Protect bits (BP2, BP1 and BP0) to be set for protecting all,
a portion, or none of the memory from erase and program
instructions. Protected areas become read-only (see table
2). The Write Status Register instruction also allows the
Status Register Protect bit (SRP) to be set. This bit is used
in conjunction with the Write Protect (WP) pin to disable
writes to the status register. When the SRP bit is set to a 0
state (factory default) the WP pin has no control over the
status register. When the SRP pin is set to a 1, the Write
Status Register instruction is locked out while the WP pin
is low. When the WP pin is high the Write Status Register
instruction is allowed.
For the NX25P40, only non-volatile Status Register bits
STP, BP2, BP1 and BP0 (bits 7, 4, 3 and 2) can be written
to. For the NX25P20 and NX25P10 only Status Register bits
STP, BP1 and BP0 (bits 7, 3 and 2) can be written to. All
other Status Register bit locations are read-only and will not
be affected by the Write Status Register instruction.
The CS pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Write Status
Register instruction will not be executed. After CS is driven
high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics).
1
2
3
4
5
6
CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
7
11 12 13 14 15
CLK Mode 0
DI
8
Status Register In
Instruction (01h)
7
6
5
4
3
2
1
0
*
High Impedance
DO
9
* = MSB
10
Figure 7. Write Status Register Instruction Sequence Diagram
11
12
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PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
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13
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Read Data (03h)
The Read Data instruction allows one or more data bytes to
be sequentially read from the memory. The instruction is
initiated by driving the CS pin low and then shifting the
instruction code “03h” followed by a 24-bit address (A23-A0)
into the DI pin. The code and address bits are latched on the
rising edge of the CLK pin. After the address is received, the
data byte of the addressed memory location will be shifted
out on the DO pin at the falling edge of CLK with most
significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of
data is shifted out allowing for a continuous stream of data.
This means that the entire memory can be accessed with
a single instruction as long as the clock continues. The
instruction is completed by driving CS high. The Read Data
instruction sequence is shown in figure 8. If a Read Data
instruction is issued while an Erase, Program or Write cycle
is in process (BUSY=1) the instruction is ignored and will not
have any effects on the current cycle. The Read Data
instruction allows clock rates from D.C. to a maximum of fR
( see AC Electrical Characteristics).
CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
Mode 0
24-Bit Addess
Instruction (03h)
DI
23 22 21
3
2
1
0
*
DO
Data Out 1
Data Out 2
High Impedance
7
6
5
4
3
2
1
0
7
*
* = MSB
Figure 8. Read Data Instruction Sequence Diagram
14
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PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
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1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data
instruction except that it can operate at the highest possible
frequency of FR (see AC Electrical Characteristics). This is
accomplished by adding a “dummy” byte after the 24-bit
address as shown in figure 9. The dummy byte allows the
devices internal circuits additional time for setting up the
initial address. The dummy byte data value on the DI pin is
a “don’t care”.
2
CS
0
Mode 3
CLK
1
1
2
3
4
5
6
7
8
9
10
28 29 30 31
3
Mode 0
24-Bit Address
Instruction (0Bh)
DI
23 22 21
3
2
1
4
0
DO
5
CS
32 33 34 35 36 37 38 39 40 41
6
42 43 44 45 46 47
CLK
7
Dummy Byte
DI
7
6
5
4
3
2
1
0
Data Out 1
DO
7
*
6
5
4
3
Data Out 2
2
1
0
7
6
5
*
4
3
2
1
0
8
7
*
9
* = MSB
Figure 9. Fast Read Instruction Sequence Diagram
10
11
12
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04/04/05 ©
15
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Page Program (02h)
The Page Program instruction allows from one byte to 256
bytes of data to be programmed at memory locations
previously erased to all 1s (FFh). A Write Enable instruction
must be executed before the device will accept the Page
Program Instruction (Status Register bit WEL must equal
1). The instruction is initiated by driving the CS pin low then
shifting the instruction code “02h” followed by a 24-bit
address (A23-A0) and at least one data byte, into the DI pin.
The CS pin must be driven low for the entire length of the
instruction while data is being sent to the device. The Page
Program instruction sequence is shown in figure 10.
to the device the addressing will wrap to the beginning of the
page and overwrite previously sent data.
As with the write and erase instructions, the CS pin must be
driven high after the eighth bit of the last byte has been
latched. If this is not done the Page Program instruction will
not be executed. After CS is driven high, the self-timed
Page Program instruction will commence for a time duration
of tpp (See AC Characteristics). While the Page Program
cycle is in progress, the Read Status Register instruction
may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Page Program cycle and
becomes a 0 when the cycle is finished and the device is
ready to accept other instructions again. After the Page
Program cycle has started the Write Enable Latch (WEL) bit
in the Status Register is cleared to 0. The Page Program
instruction will not be executed if the addressed page is
protected by the Block Protect (BP2, BP1, BP0) bits (see
Table 2).
If an entire 256 byte page is to be programmed, the last
address byte (the 8 least significant address bits) should be
set to 0. If the last address byte is not zero, and the number
of clocks exceed the remaining page length, the addressing
will wrap to the beginning of the page. Less than 256 bytes
can be programmed without having any effect on other
bytes within the same page. If more than 256 bytes are sent
CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32
33 34
35 36 37 38 39
Mode 0
24-Bit Address
Instruction (02h)
23 22
DI
21
3
2
Data Byte 1
1
*
7
0
6
5
4
3
2
1
0
*
2079
2078
2077
2076
2075
51 52 53 54 55
2074
49 50
2073
40 41 42 43 44 45 46 47 48
2072
CS
CLK
Data Byte 2
DI
7
*
6
5
4
3
2
Data Byte 3
1
0
7
*
6
5
4
3
2
Data Byte 256
1
0
7
6
5
4
3
2
1
0
*
* = MSB
Figure 10. Page Program Instruction Sequence Diagram
16
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PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
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1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Sector Erase (D8h)
instruction will not be executed. After CS is driven high, the
self-timed Sector Erase instruction will commence for a time
duration of tSE (See AC Characteristics). While the Sector
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Sector Erase cycle and
becomes a 0 when the cycle is finished and the device is ready
to accept other instructions again. After the Sector Erase cycle
has started the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0. The Sector Erase instruction will not
be executed if the addressed page is protected by the Block
Protect (BP2, BP1, BP0) bits (see Table 2).
The Sector Erase instruction sets all memory within a
specified sector to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will
accept the Erase Sector Instruction (Status Register bit
WEL must equal 1). The instruction is initiated by driving the
CS pin low and shifting the instruction code “D8h” followed
a 24-bit sector address (A23-A0) (see Figure 1). The lowest
16 address bits (A15-A0) must be set to 0. The Sector Erase
instruction sequence is shown in figure 11.
The CS pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Sector Erase
1
2
3
4
CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
5
29 30 31
Mode 0
24-Bit Address
Instruction (D8h)
DI
23 22
2
1
6
0
*
High Impedance
DO
7
*
= MSB
Figure 11. Sector Erase Instruction Sequence Diagram
8
9
10
11
12
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1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Bulk Erase (C7h)
The Bulk Erase instruction sets all memory within the
device to the erased state of all 1s (FFh). A Write Enable
instruction must be executed before the device will accept
the Bulk Erase Instruction (Status Register bit WEL must
equal 1). The instruction is initiated by driving the CS pin low
and shifting the instruction code “C7h”. The Bulk Erase
instruction sequence is shown in figure 12.
Erase instruction will commence for a time duration of tBE
(See AC Characteristics). While the Bulk Erase cycle is in
progress, the Read Status Register instruction may still be
accessed to check the status of the BUSY bit. The BUSY
bit is a 1 during the Bulk Erase cycle and becomes a 0 when
finished and the device is ready to accept other instructions
again. After the Bulk Erase cycle has started the Write
Enable Latch (WEL) bit in the Status Register is cleared to
0. The Bulk Erase instruction will not be executed if any
page is protected by the Block Protect (BP2, BP1, BP0) bits
(see Table 2).
The CS pin must be driven high after the eighth bit has been
latched. If this is not done the Bulk Erase instruction will not
be executed. After CS is driven high, the self-timed Bulk
CS
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 0
Instruction (C7h)
DI
DO
High Impedance
Figure 12. Bulk Erase Instruction Sequence Diagram
18
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1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Power-down (B9h)
Although the standby current during normal operation is
relatively low, standby current can be further reduced with
the Power-down instruction. The lower power consumption
makes the Power-down instruction especially useful for
battery powered applications (See ICC1 and ICC2 in AC
Characteristics). The instruction is initiated by driving the
CS pin low and shifting the instruction code “B9h” as shown
in figure 13.
The CS pin must be driven high after the eighth bit has been
latched. If this is not done the Power-down instruction will
not be executed. After CS is driven high, the power-down
state will entered within the time duration of tDP (See AC
Characteristics). While in the power-down state only the
Release from Power-down / Device ID instruction, which
restores the device to normal operation, will be recognized.
All other instructions are ignored. This includes the Read
Status Register instruction, which is always available
during normal operation. Ignoring all but one instruction
makes the Power Down state a useful condition for securing
maximum write protection. The device always powers-up in
the normal operation with the standby current of ICC1.
1
2
3
4
CS
tDP
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 0
5
Instruction (B9h)
DI
6
High Impedance
DO
Stand-by Current
Power-down Current
7
Figure 13. Deep Power-down Instruction Sequence Diagram
8
9
10
11
12
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1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Release Power-down / Device ID (ABh)
The Release from Power-down / Device ID instruction is a
multi-purpose instruction. It can be used to release the
device from the power-down state, obtain the devices
electronic identification (ID) number or do both.
first as shown in figure 15. The Device ID values for the
NX25P10, NX25P20, and NX25P40 are listed in Table 4.
The Device ID can be read continuously. The instruction is
completed by driving CS high.
When used only to release the device from the power-down
state, the instruction is issued by driving the CS pin low,
shifting the instruction code “ABh” and driving CS high as
shown in figure 14. After the time duration of tRES1 (See AC
Characteristics) the device will resume normal operation
and other instructions will be accepted. The CS pin must
remain high during the tRES1 time duration.
When used to release the device from the power-down state
and obtain the Device ID, the instruction is the same as
previously described, and shown in figure 13, except that
after CS is driven high it must remain high for a time duration
of tRES2 (See AC Characteristics). After this time duration
the device will resume normal operation and other instructions will be accepted.
When used only to obtain the Device ID while not in the
power-down state, the instruction is initiated by driving the
CS pin low and shifting the instruction code “ABh” followed
by 3-dummy bytes. The Device ID bits are then shifted out
on the falling edge of CLK with most significant bit (MSB)
If the Release from Power-down / Device ID instruction is
issued while an Erase, Program or Write cycle is in process
(when BUSY equals 1) the instruction is ignored and will not
have any effects on the current cycle.
CS
tRES1
0
Mode 3
1
2
3
4
5
6
7
Mode 0
CLK
Instruction (ABh)
DI
High Impedance
DO
Power-down Current
Stand-by Current
Figure 14. Release Power-down Instruction Sequence
CS
0
Mode 3
CLK
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37
38
Mode 0
Instruction (ABh)
DI
High Impedance
DO
tRES2
3 Dummy Bytes
23 22
21
3
2
1
0
*
7
6
Device ID
**
5
3
4
2
1
0
*
Power-down Current
Stand-by Current
* = MSB
** = See Table 4
Figure 15. Release Power-down / Device ID Instruction Sequence Diagram
20
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
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1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Read Manufacturer / Device ID (90h)
turer ID for NexFlash (EFh) and the Device ID are shifted out
on the falling edge of CLK with most significant bit (MSB)
first as shown in figure 16. The Device ID values for the
NX25P10, NX25P20, and NX25P40 are listed in Table 4. If
the 24-bit address is initially set to 000001h the Device ID
will be read first and then followed by the Manufacturer ID.
The Manufacturer and Device IDs can be read continuously,
alternating from one to the other. The instruction is completed by driving CS high.
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction
that provides both the JEDEC assigned manufacturer ID
and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar
to the Release from Power-down / Device ID instruction.
The instruction is initiated by driving the CS pin low and
shifting the instruction code “90h” followed by a 24-bit
address (A23-A0) of 000000h. After which, the Manufac-
CLK
0
1
2
3
4
5
2
3
CS
Mode 3
1
6
7
8
9
10
4
28 29 30 31
Mode 0
Instruction (90h)
Address (000000h)
23 22
DI
High Impedance
21
3
2
1
5
0
*
DO
6
CS
32 33 34 35 36 37 38
7
39 40 41 42 43 44 45
CLK
8
DI
**)
Device ID (
Manufacturer ID (EFh)
7
DO
6
5
4
3
2
1
0
*
9
* = =MSB
** See Table 4
10
Figure 16. Read Manufacturer / Device ID Diagram
11
12
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1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
SPECIFICATIONS AND TIMING DIAGRAMS
Table 5. Absolute Maximum Ratings (1)
Symbol
Vcc
VIO
TSTG
TLEAD
Parameters
Supply Voltage
Voltage Applied to Any Pin
Storage Temperature
Lead Temperature
Conditions
Relative to Ground
Range
–0.6 to +4.0
–0.6 to Vcc + 0.4
–65 to +150
See Note 2
VESD
Electrostatic Discharge Voltage
Human Body Model(3)
–2000 to +2000
Unit
V
V
°C
°C
V
Note:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is
not guaranteed. Exposure beyond absolute maximum ratings (listed above) may cause permanent damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive
on restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).
Table 6. Operating Ranges
Symbol
Vcc
Parameter
Supply Voltage(1)
TA
Ambient Temperature, Operating
Conditions
FR = 33MHz, fR = 20MHz
FR = 40MHz, fR = 33MHz
Industrial
Min
2.7
3.0
–40
Max
3.6
3.6
+85
Unit
V
V
°C
Note:
1. Vcc voltage during Read can operate across the min and max range but should not exceed ±10% of the programming
(erase/write) voltage.
Table 7. Power-up Timing and Write Inhibit Threshold
Symbol
tVSL(1)
tPUW(1)
VWI(1)
Parameter
VCC(min) to CS Low
Time Delay Before Write Instruction
Write Inhibit Threshold Voltage
Min
10
1
1
Max
10
2
Unit
µs
ms
V
Note:
1. These parameters are characterized only.
Vcc
Vcc
(max)
Program, Erase and Write Instructions are Ignored
CS Must Track Vcc
Vcc
(min)
Reset
State
tVSL
Read Instructions
Allowed
Device is Fully
Accessible
VWI
tPUW
Time
Figure 17. Power-up Timing and Voltage Levels
22
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1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Table 8. DC Electrical Characteristics (Preliminary) (1)
Symbol
CIN(2)
Cout(2)
ILI
ILO
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
VIL
VIH
VOL
VOH
Parameter
Input Capacitance
Output Capacitance
Input Leakage
I/O Leakage
Standby Current
Power-down Current
Current Read Data 1MHz
Current Read Data 20MHz
Current Read Data 33MHz
Current Page Program
Current Write Status Register
Current Sector Erase
Current Bulk Erase
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Conditions
VIN = 0V(2)
VOUT = 0V(2)
Min
Typ
CS = VCC, VIN = GND or VCC
CS = VCC, VIN = GND or VCC
C = 0.1VCC / 0.9 VCC DO = Open
C = 0.1VCC / 0.9 VCC DO = Open
C = 0.1VCC / 0.9 VCC DO = Open
CS = VCC
CS = VCC
CS = VCC
CS = VCC
25
<1
4
10
14
15
8
15
17
–0.5
Vccx0.7
IOL = 1.6 mA
IOH = –100 µA
VCC–0.2
Max
6
8
±2
±2
50
5
7
14
18
20
20
25
25
Vccx0.3
Vcc +0.4
0.4
Unit
pf
pf
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
Notes:
1. See Preliminary Designation.
2. Tested on sample basis and specified through design and characterization data. TA=25° C, Vcc 3V, Frequency 20MHz.
1
2
3
4
5
6
7
Table 9. AC Measurement Conditions
Symbol
CL
TR, TF
VIN
OUT
Parameter
Load Capacitance
Input Rise and Fall Times
Input Pulse Voltages
Output Timing Reference Voltages
Min
30
Max
30
5
0.8VCC
0.7VCC
0.2VCC to
0.3VCC to
Unit
pF
ns
V
V
8
9
Note:
1. Output Hi-Z is defined as the point where data out is no longer driven.
10
Input Levels
Input and Output
Timing Reference Levels
0.8 Vcc
11
0.7 Vcc
12
0.3 Vcc
0.2 Vcc
Figure 18. AC Measurement I/O Waveform
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04/04/05 ©
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1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Table 10. AC Electrical Characteristics (Preliminary)
Symbol
FR
Alt
fC
fR
tCLH, tCLL(1)
tCRLH, tCRLL(1)
tCLCH(2)
tCHCL(2)
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tSHQZ(2)
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX(2)
tHLQZ(2)
tWHSL(4)
tSHWL(4)
tDP(2)
tRES1(2)
tRES2(2)
tW
tPP
tSE
tBE
tCSS
tDSU
tDH
tCSH
tDIS
tV
tHO
tLZ
tHZ
Description
Min
Clock frequency, for Fast Read (0Bh) and all other
instructions except Read Data (03h) 2.7V-3.6V Vcc
D.C.
3.0V-3.6V Vcc
D.C.
Clock freq. Read Data instruction (03h) 2.7V-3.6V Vcc
D.C.
3.0V-3.6V Vcc
D.C.
Clock High, Low Time, for Fast Read (0Bh)
11
and all other instructions except Read Data (03h)
Clock High, Low Time for Read Data instruction (20 / 33-40MHz) 18 / 11
Clock Rise Time peak to peak
0.1
Clock Fall Time peak to peak
0.1
CS Active Setup Time relative to CLK (20 / 33-40MHz)
10 / 5
CS Not Active Hold Time relative to CLK (20 / 33-40MHz)
10 / 5
Data In Setup Time (20 / 33-40MHz)
5/2
Data In Hold Time
5
CS Active Hold Time relative to CLK (20 / 33-40MHz)
10 / 5
CS Not Active Setup Time relative to CLK (20 / 33-40MHz)
10 / 5
CS Deselect Time
100
Output Disable Time (20 / 33-40MHz)
Clock Low to Output Valid (20 / 33-40MHz)
Output Hold Time
0
HOLD Active Setup Time relative to CLK (20 / 33-40MHz)
10 / 5
HOLD Active Hold Time relative to CLK (20 / 33-40MHz)
10 / 5
HOLD Not Active Setup Time relative to CLK (20 / 33-40MHz) 10 / 5
HOLD Not Active Hold Time relative to CLK (20 / 33-40MHz)
10 / 5
HOLD to Output Low-Z (20 / 33-40MHz)
HOLD to Output High-Z (20 / 33-40MHz)
Write Protect Setup Time Before CS Low
20
Write Protect Hold Time After CS High
100
CS High to Power-down Mode
CS High to Standby Mode without Electronic
Signature Read
CS High to Standby Mode with Electronic
Signature Read
Write Status Register Cycle Time
Page Program Cycle Time
Sector Erase Cycle Time
Bulk Erase Cycle Time 25P10 and 25P20
Bulk Erase Cycle Time 25P40
Typ
Max
Unit
33
40
20
33
MHz
MHz
MHz
MHz
ns
3
3
ns
V / ns
V / ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
1.8
µs
15
5
3
6
10
ms
ms
s
s
s
15 / 9
15 / 10
15 / 9
20 / 9
10
2
0.7
3
5
Notes:
1. Clock high + Clock low must be less than or equal to 1/fC.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set at 1.
24
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
1
CS
tCH
CLK
tCLQV
tCLQV
tCLQX
tCL
tSHQZ
2
tCLQX
DO
LSB OUT
tQLQH
tQHQL
DI
3
*
* LEAST SIGNIFICANT ADDRESS BIT (LSB) IN
4
Figure 19. Serial Output Timing
5
tSHSL
CS
tCHSL
CLK
tSLCH
tCHSH
6
tDVCH
DO
tCHCL
tCLCH
tCHDX
DI
tSHCH
MSB IN
LSB IN
7
(High Impedance)
8
Figure 20. Input Timing
9
CS
tCHHL
tHLCH
tHHCH
10
CLK
tCHHH
tHLQZ
tHHQX
DO
11
DI
12
HOLD
Figure 21. Hold Timing
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
25
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
PACKAGING INFORMATION
8-Pin SOIC 150-mil (Package Code N)
SEATING PLANE
A2 A
E1 E
CP
b
A1
e
1
D
L
α
C
Package Dimensions(1)
Symbol
A
A1
A2
b
C
D(3)
E
E1(3)
e(2)
L
α
CP
26
Millimeters
Min Typ. Max
1.47 1.60 1.72
0.10
0.24
1.45
0.33 0.41 0.50
0.19 0.20 0.25
4.80 4.85 4.95
5.80 6.00 6.19
3.80 3.90 4.00
1.27 BSC
0.40 0.71 1.27
0o
8o
0.10
Min
0.058
0.004
0.013
0.0075
0.189
0.228
0.150
0.015
0o
Inches
Typ.
0.063
0.057
0.016
0.008
0.191
0.236
0.154
0.050 BSC
0.028
Max
0.068
0.009
0.020
0.0098
0.195
0.244
0.157
0.050
8o
0.004
Notes:
1. Controlling dimensions: inches,
unless otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should
be measured from the bottom of the
package.
4. Formed leads shall be planar with
respect to one another within .0004
inches at the seating plane.
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
PRELIMINARY DESIGNATION
LIFE SUPPORT POLICY
The “Preliminary” designation on a NexFlash data sheet
indicates that the product is not fully characterized. The
specifications are subject to change and are not guaranteed. NexFlash or an authorized sales representative
should be consulted for current information before using this
product.
NexFlash does not recommend the use of any of it's
products in life support applications where the failure or
malfunction of the product can reasonably be expected to
cause failure in the life support system or to significantly
affect its safety or effectiveness. Products are not
authorized for use in such applications unless NexFlash
receives written assurances, to it’s satisfaction, that:
IMPORTANT NOTICE
NexFlash reserves the right to make changes to the
products contained in this publication in order to improve
design, performance or reliability. NexFlash assumes no
responsibility for the use of any circuits described herein,
conveys no license under any patent or other right, and
makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect
representative operating parameters, and may vary depending upon a user’s specific application. While the
information in this publication has been carefully checked,
NexFlash shall not be liable for any damages arising as a
result of any error or omission.
(a)
the risk of injury or damage has been minimized;
(b)
the user assumes all such risks; and
(c)
potential liability of NexFlash is adequately protected under the circumstances.
1
2
3
4
TRADEMARKS
NexFlash and spiFlash are trademarks of NexFlash
Technologies, Inc. All other marks are the property of their
respective owner.
ORDERING INFORMATION
5
6
NX 25P xx - V x
I - xx..
Company Prefix
7
NX = NexFlash
Product Family
25P = spiFlash Serial Flash Memory
8
Product Number / Density
10 = 1M-bit
20 = 2M-bit
40 = 4M-bit
9
Supply Voltage
V = 2.7V to 3.6V
Package Type
10
N = 8-pin SOIC 150-mil
P = 8-contact MLP 6x5mm*
Temperature Range
11
I = Industrial (–40˚C to +85˚C)
Special Options
(Blank) Standard Package
G = Green Package (Lead-Free, RoHS compliant)
C = Customer Specification (For factory programming and other custom specifications)
T = Tape and Reel
12
* Contact NexFlash for availability of this package.
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©
27
1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI
NX25P10, NX25P20 AND NX25P40
Document Revision History
Date
Rev
Description of Revision
04/29/03
A
Document Written
09/12/03
B
Incorporated spiFlash trademark for NX25P10, 20 and 40 product
family. Adjusted data for consistency
03/09/04
C
Adjusted pages 10, 11, 14, 16 and 24 for technical clarity. Updated
Special Options and Ordering Information
03/24/04
D
MLP metal die pad notification; Under "Package Types," figure 3 and
packaging information.
05/11/04
E
Corrected dimensions in Packaging Information section for 6x5mm MLP.
Updated Characterization information DC (Table 8) & AC (Table 10).
06/16/04
F
Modified dimensional data in the Packaging Information for the 6x5mm
MLP package
11/23/04
G
Added FR = 40MHz @ 3.0V to 3.6V Vcc. Added fR = 33MHz @ 3.0V
to 3.6V Vcc. Modified tLEAD in Absolute Maximum Ratings (Table 5) to
reference JEDEC Standard information. Added FR and fR conditions to
Operating Ranges (Table 6). Updated ICC3 and ICC5 data in DC Electrical Characteristics (Table 8). Added 20/33MHz call outs and updated
min, max and typ data in AC Electrical Characteristics (Table 10).
12/08/04
H
Updated 8-pin 150mil SOIC package information.
04/04/05
I
Removed 8-contact 6x5 MLP package from document.
28
NexFlash Technologies, Inc.
PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405
04/04/05 ©