AD OP481 Ultralow power, rail-to-rail output operational amplifier Datasheet

Ultralow Power, Rail-to-Rail Output
Operational Amplifiers
OP281/OP481
OUT A 1
–IN A 2
TOP VIEW
+IN A 3
(Not to Scale)
V– 4
Fabricated on Analog Devices’ CBCMOS process, the
OP281/OP481 feature a precision bipolar input and an output
that swings to within millivolts of the supplies, continuing to
sink or source current up to a voltage equal to the supply voltage.
Applications for these amplifiers include safety monitoring,
portable equipment, battery and power supply control, and
signal conditioning and interfacing for transducers in very low
power systems.
The output’s ability to swing rail-to-rail and not increase supply
current when the output is driven to a supply voltage enables
the OP281/OP481 to be used as comparators in very low power
systems. This is enhanced by their fast saturation recovery time.
Propagation delays are 250 μs.
The OP281/OP481 are specified over the extended industrial
temperature range (−40°C to +85°C). The OP281 dual amplifier
is available in 8-lead SOIC surface-mount and TSSOP packages.
The OP481 quad amplifier is available in narrow 14-lead SOIC
and TSSOP packages.
V+
7
OUT B
6
–IN B
5
+IN B
1
8
V+
–IN A
2
OP281
7
OUT B
+IN A
3
TOP VIEW
(Not to Scale)
6
–IN B
V–
4
5
+IN B
00291-002
OUT A
Figure 2. 8-Lead TSSOP
(RU Suffix)
GENERAL DESCRIPTION
The OP281 and OP481 are dual and quad ultralow power
single-supply amplifiers featuring rail-to-rail outputs. Each
operates from supplies as low as 2.0 V and is specified at +3 V
and +5 V single supplies as well as ±5 V dual supplies.
8
Figure 1. 8-Lead
Narrow-Body SOIC
(R Suffix)
APPLICATIONS
Comparator
Battery-powered instrumentation
Safety monitoring
Remote sensors
Low voltage strain gage amplifiers
OP281
00291-001
PIN CONFIGURATIONS
OUT A 1
14
OUT D
–IN A 2
13
–IN D
12
+IN D
+IN A 3
OP481
11 V–
TOP VIEW
(Not to Scale)
10 +IN C
+IN B 5
V+ 4
–IN B 6
9
–IN C
OUT B 7
8
OUT C
00291-003
Low supply current: 4 μA/amplifier maximum
Single-supply operation: 2.7 V to 12 V
Wide input voltage range
Rail-to-rail output swing
Low offset voltage: 1.5 mV
No phase reversal
Figure 3. 14-Lead
Narrow-Body SOIC
(R Suffix)
OUT A
1
14
OUT D
–IN A
2
13
–IN D
+IN A
3
V+
4
+IN B
5
10
+IN C
–IN B
6
9
–IN C
OUT B
7
8
OUT C
OP481
+IN D
TOP VIEW
11 V–
(Not to Scale)
12
00291-004
FEATURES
Figure 4. 14-Lead TSSOP
(RU Suffix)
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1996–2008 Analog Devices, Inc. All rights reserved.
OP281/OP481
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation .................................................................. 13
Applications ....................................................................................... 1
Input Overvoltage Protection ................................................... 13
Pin Configurations ........................................................................... 1
Input Offset Voltage ................................................................... 13
General Description ......................................................................... 1
Input Common-Mode Voltage Range ..................................... 13
Revision History ............................................................................... 2
Capacitive Loading..................................................................... 14
Specifications..................................................................................... 3
Micropower Reference Voltage Generator.............................. 14
Electrical Specifications ............................................................... 3
Window Comparator ................................................................. 14
Absolute Maximum Ratings............................................................ 6
Low-Side Current Monitor ....................................................... 15
Thermal Resistance ...................................................................... 6
Low Voltage Half-Wave and Full-Wave Rectifiers ................. 15
ESD Caution .................................................................................. 6
Battery-Powered Telephone Headset Amplifier..................... 15
Typical Performance Characteristics ............................................. 7
Outline Dimensions ....................................................................... 17
Applications ..................................................................................... 13
Ordering Guide .......................................................................... 18
REVISION HISTORY
9/08—Rev. C to Rev. D
2/03—Rev. 0 to Rev. A
Changes to Figure 40 ...................................................................... 14
Changes to Low-Side Current Monitor Section ......................... 15
Changes to Figure 42 ...................................................................... 15
Updated Format .................................................................. Universal
Deleted OP181 .................................................................... Universal
Updated Package Options ................................................. Universal
Deleted OP181 Pin Configurations ................................................1
Deleted Epoxy DIP Pin Configurations .........................................1
Changes to Absolute Maximum Ratings ........................................5
Changes to Ordering Guide .............................................................5
Changes to Input Offset Voltage................................................... 10
Deleted Former Figure 33 ............................................................. 10
Deleted Overdrive Recovery Time Section ................................. 11
Deleted Former Figure 36 ............................................................. 11
Deleted 8-Lead and 14-Lead Plastic DIP (N-8 and N-14)
Outline Dimensions ....................................................................... 14
Updated Outline Dimensions ....................................................... 14
10/07—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Offset Voltage Drift Condition .................................. 3
Changes to Slew Rate Symbol ......................................................... 5
Changes to Figure 8 .......................................................................... 7
Deleted SPICE Macro-Model Section ......................................... 13
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 18
3/03—Rev. A to Rev. B
Changes to Features.......................................................................... 1
Rev. D | Page 2 of 20
OP281/OP481
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VS = 3.0 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT CHARACTERISTICS
Offset Voltage 1
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Large-Signal Voltage Gain
Symbol
Condition
Min
Typ
VOS
IB
IOS
CMRR
AVO
VCM = 0 V to 2.0 V, −40°C ≤ TA ≤ +85°C
RL = 1 MΩ, VO = 0.3 V to 2.7 V
−40°C ≤ TA ≤ +85°C
−40°C to +85°C
3
0.1
0
65
5
2
Unit
1.5
2.5
10
7
2
mV
mV
nA
nA
V
dB
V/mV
V/mV
μV/°C
pA/°C
pA/°C
95
13
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Limit
VOH
VOL
ISC
RL = 100 kΩ to GND, −40°C ≤ TA ≤ +85°C
RL = 100 kΩ to V+, −40°C ≤ TA ≤ +85°C
2.925
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
PSRR
ISY
VS = 2.7 V to 12 V, −40°C ≤ TA ≤ +85°C
VO = 0 V
−40°C ≤ TA ≤ +85°C
76
SR
RL = 100 kΩ, CL = 50 pF
AV = 1, VO = 1 V
AV = 20, VO = 1 V
25
40
50
65
95
70
V/ms
μs
μs
μs
kHz
Degrees
0.1 Hz to 10 Hz
f = 1 kHz
10
75
<1
μV p-p
nV/√Hz
pA/√Hz
DYNAMIC PERFORMANCE
Slew Rate
Turn-On Time
Saturation Recovery Time
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
1
ΔVOS/∆T
ΔIB/ΔT
ΔIOS/ΔT
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +85°C
Max
GBP
φM
en p-p
en
in
VOS is tested under a no load condition.
Rev. D | Page 3 of 20
10
20
2
2.96
25
±1.1
95
3
75
4
5
V
mV
mA
dB
μA
μA
OP281/OP481
VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage 1
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Large-Signal Voltage Gain
Symbol
Condition
Min
VOS
IB
IOS
CMRR
AVO
ΔVOS/ΔT
ΔIB/ΔT
ΔIOS/ΔT
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +85°C
VCM = 0 V to 4.0 V, −40°C ≤ TA ≤ +85°C
RL = 1 MΩ, VO = 0.5 V to 4.5 V
−40°C ≤ TA ≤ +85°C
−40°C to +85°C
Typ
Max
Unit
0.1
1.5
2.5
10
7
4
mV
mV
nA
nA
V
dB
V/mV
V/mV
μV/°C
pA/°C
pA/°C
3
0.1
0
65
5
2
90
15
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Limit
VOH
VOL
ISC
RL = 100 kΩ to GND, −40°C ≤ TA ≤ +85°C
RL = 100 kΩ to V+, −40°C ≤ TA ≤ +85°C
4.925
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
PSRR
ISY
VS = 2.7 V to 12 V, −40°C ≤ TA ≤ +85°C
VO = 0 V
−40°C ≤ TA ≤ +85°C
76
SR
RL = 100 kΩ, CL = 50 pF
27
120
100
74
V/ms
μs
kHz
Degrees
0.1 Hz to 10 Hz
f = 1 kHz
10
75
<1
μV p-p
nV/√Hz
pA/√Hz
DYNAMIC PERFORMANCE
Slew Rate
Saturation Recovery Time
Gain Bandwidth Product
Phase Margin
GBP
φM
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
1
VOS is tested under a no load condition.
Rev. D | Page 4 of 20
10
20
2
4.96
25
±3.5
95
3.2
75
4
5
V
mV
mA
dB
μA
μA
OP281/OP481
VS = ±5.0 V, TA = +25°C, unless otherwise noted.
Table 3.
Parameter
INPUT CHARACTERISTICS
Offset Voltage 1
IB
IOS
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
ΔVOS/ΔT
ΔIB/ΔT
ΔIOS/ΔT
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Condition
Min
VOS
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection
Large-Signal Voltage Gain
OUTPUT CHARACTERISTICS
Output Voltage Swing
Short-Circuit Limit
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
1
Symbol
CMRR
AVO
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
VCM = –5.0 V to +4.0 V, –40°C ≤ TA ≤ +85°C
RL = 1 MΩ, VO = ±4.0 V,
–40°C ≤ TA ≤ +85°C
–40°C to +85°C
Typ
Max
Unit
0.1
1.5
2.5
10
7
+4
10
20
2
mV
mV
nA
nA
V
dB
V/mV
V/mV
μV/°C
pA/°C
pA/°C
V
mA
3
0.1
–5
65
5
2
95
13
VO
ISC
RL = 100 kΩ to GND, –40°C ≤ TA ≤ +85°C
±4.925
±4.98
12
PSRR
ISY
VS = ±1.35 V to ±6 V, –40°C ≤ TA ≤ +85°C
VO = 0 V
–40°C ≤ TA ≤ +85°C
76
95
3.3
SR
GBP
φM
RL = 100 kΩ, CL = 50 pF
28
105
75
V/ms
kHz
Degrees
en p-p
en
0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
10
85
75
<1
μV p-p
nV/√Hz
nV/√Hz
pA/√Hz
in
VOS is tested under a no load condition.
Rev. D | Page 5 of 20
5
6
dB
μA
μA
OP281/OP481
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature Range (Soldering, 60 sec)
Rating
16 V
GND to VS + 10 V
±3.5 V
Indefinite
−65°C to +150°C
−40°C to +85°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5. Thermal Resistance
Package Type
8-Lead SOIC (R Suffix)
8-Lead TSSOP (RU Suffix)
14-Lead SOIC (R Suffix)
14-Lead TSSOP (RU Suffix)
1
θJA1
158
240
120
240
θJC
43
43
36
43
Unit
°C/W
°C/W
°C/W
°C/W
θJA is specified for the worst-case conditions, that is, θJA is specified for device
soldered in circuit board for TSSOP and SOIC packages.
ESD CAUTION
Rev. D | Page 6 of 20
OP281/OP481
TYPICAL PERFORMANCE CHARACTERISTICS
45
0
VS = 2.7V
TA = 25°C
40
–1.0
INPUT BIAS CURRENT (nA)
30
25
20
15
10
5
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
0
0.2
0.4
0.6
0.8
1.0
INPUT OFFSET VOLTAGE (mV)
–5.0
–40
00291-005
–1.0 –0.8 –0.6 –0.4 –0.2
Figure 5. Input Offset Voltage Distribution
50
1.0
INPUT BIAS CURRENT (nA)
30
25
20
15
10
120
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
5
0
0.2
0.4
0.6
0.8
1.0
–3.5
00291-006
–1.0 –0.8 –0.6 –0.4 –0.2
INPUT OFFSET VOLTAGE (mV)
0.5
VS = 5V
1800
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
COMMON-MODE VOLTAGE (V)
4.5
5.0
VS = 5V
0.4
INPUT OFFSET CURRENT (nA)
1600
1400
1200
1000
800
600
400
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–20
0
60
80
20
40
TEMPERATURE (°C)
100
120
00291-007
200
0
–40
0
Figure 9. Input Bias Current vs. Common-Mode Voltage
Figure 6. Input Offset Voltage Distribution
INPUT OFFSET VOLTAGE (µV)
100
00291-009
QUANTITY (Amplifiers)
35
2000
60
80
20
40
TEMPERATURE (°C)
VS = 5V
TA = 25°C
0.5
40
0
0
Figure 8. Input Bias Current vs. Temperature
VS = 5V
TA = 25°C
45
–20
00291-008
–4.5
Figure 7. Input Offset Voltage vs. Temperature
–0.4
–40
–20
0
60
80
20
40
TEMPERATURE (°C)
100
Figure 10. Input Offset Current vs. Temperature
Rev. D | Page 7 of 20
120
00291-010
QUANTITY (Amplifiers)
35
0
VS = 5V
–0.5
OP281/OP481
10000
70
VS = 3V
TA = 25°C
SOURCE
SINK
10
1
10
100
1000
LOAD CURRENT (µA)
30
20
90
10
135
0
180
–10
225
–20
270
–30
100
00291-011
1
0
45
10k
1M
100k
FREQUENCY (Hz)
Figure 11. Output Voltage to Supply Rail vs. Load Current
1000
1k
00291-014
OPEN-LOOP GAIN (dB)
OUTPUT VOLTAGE (mV)
100
40
PHASE SHIFT (Degrees)
50
1000
0.1
VS = 5V
TA = 25°C
RL = 100kΩ
60
Figure 14. Open-Loop Gain and Phase vs. Frequency
70
VS = 5V
TA = 25°C
VS = 3V
TA = 25°C
RL = 100kΩ
60
10
1
0.1
1
10
100
1000
LOAD CURRENT (µA)
0
30
45
20
90
10
135
0
180
–10
225
–20
270
–30
100
10k
1M
100k
FREQUENCY (Hz)
Figure 12. Output Voltage to Supply Rail vs. Load Current
1000
1k
PHASE SHIFT (Degrees)
SINK
40
00291-015
OPEN-LOOP GAIN (dB)
SOURCE
00291-012
OUTPUT VOLTAGE (mV)
50
100
Figure 15. Open-Loop Gain and Phase vs. Frequency
70
VS = ±5V
TA = 25°C
VS = 2.7V
TA = 25°C
RL = 100kΩ
60
10
1
0.1
1
10
100
LOAD CURRENT (µA)
1000
Figure 13. Output Voltage to Supply Rail vs. Load Current
0
30
45
20
90
10
135
0
180
–10
225
–20
270
–30
100
1k
10k
100k
FREQUENCY (Hz)
Figure 16. Open-Loop Gain and Phase vs. Frequency
Rev. D | Page 8 of 20
1M
PHASE SHIFT (Degrees)
SINK
40
00291-016
OPEN-LOOP GAIN (dB)
SOURCE
00291-013
OUTPUT VOLTAGE (mV)
50
100
OP281/OP481
70
90
VS = ±5V
TA = 25°C
RL = 100kΩ TO GROUND
60
70
0
30
45
20
90
10
135
0
180
–10
225
–20
270
CMRR (dB)
PHASE SHIFT (Degrees)
10
0
1M
100k
30
–10
FREQUENCY (Hz)
1k
100
20
80
PSRR (dB)
120
30
10
0
60
40
–10
20
–20
0
–30
–20
10
100
1k
10k
10M
100k
VS = ±5V, +5V, +3V, +2.7V
TA = 25°C
RL = ∞
140
1M
FREQUENCY (Hz)
–40
00291-018
CLOSED-LOOP GAIN (dB)
160
40
–40
1M
Figure 20. CMRR vs. Frequency
VS = 5V
TA = 25°C
RL = ∞
50
100k
FREQUENCY (Hz)
Figure 17. Open-Loop Gain and Phase vs. Frequency
60
10k
10
100
1k
10k
100k
1M
00291-021
10k
VS = +3V
40
1000
00291-022
1k
50
20
00291-017
–30
100
VS = +5V
60
00291-020
40
FREQUENCY (Hz)
Figure 18. Closed-Loop Gain vs. Frequency
Figure 21. PSRR vs. Frequency
50
VS = 5V
TA = 25°C
MARKER @ 67nV/√Hz
SMALL SIGNAL OVERSHOOT (%)
45
(50nV/√Hz/DIV)
40
VS = +5V
VIN = ±50mV
RL = 100kΩ
TA = 25°C
–OS
+OS
35
30
25
20
15
10
5
0
2
4
6
8
FREQUENCY (kHz)
10
0
10
00291-019
OPEN-LOOP GAIN (dB)
50
TA = 25°C
VS = ±5V
80
100
LOAD CAPACITANCE (pF)
Figure 19. Voltage Noise Density vs. Frequency
Figure 22. Small-Signal Overshoot vs. Load Capacitance
Rev. D | Page 9 of 20
OP281/OP481
4.5
VS = 5V
VIN = 4V p-p
TA = 25°C
RL = ∞
4
VS = 5V
4.0
SUPPLY CURRENT/AMPLIFIER (µA)
MAXIMUM OUTPUT SWING (V p-p)
5
3
2
1
3.5
3.0
2.5
2.0
1.5
1.0
0.5
1k
100k
10k
0
–40
FREQUENCY (Hz)
20
40
60
80
100
120
Figure 26. Supply Current/Amplifier vs. Temperature
3.50
VS = 3V
VIN = 2V p-p
TA = 25°C
RL = ∞
TA = 25°C
3.25
SUPPLY CURRENT/AMPLIFIER (µA)
MAXIMUM OUTPUT SWING (V p-p)
0
TEMPERATURE (°C)
Figure 23. Maximum Output Swing vs. Frequency
3
–20
00291-026
100
00291-023
0
10
2
1
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
1k
100k
10k
FREQUENCY (Hz)
0
00291-024
100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (±V)
Figure 27. Supply Current/Amplifier vs. Supply Voltage
Figure 24. Maximum Output Swing vs. Frequency
4.0
A2
VS = ±2.5V
AV = 1
RL = 100kΩ
CL = 50pF
TA = 25°C
0mV
100
3.0
90
2.5
2.0
1.5
1.0
10
0
–40
50mV
–20
0
20
40
60
80
100
TEMPERATURE (°C)
120
100µs
Figure 28. Small-Signal Transient Response
Figure 25. Supply Current/Amplifier vs. Temperature
Rev. D | Page 10 of 20
00291-028
0%
0.5
00291-025
SUPPLY CURRENT/AMPLIFIER (µA)
VS = 3V
3.5
00291-027
0.25
0
10
OP281/OP481
100
90
A2
100
90
10
10
0%
0%
50mV
500mV
00291-029
100µs
Figure 29. Small-Signal Transient Response
A2
100
90
2.5V
1V
1V
VS = 5V
TA = 25°C
90
10
0%
00291-030
10
100µs
A2
100
0%
1V
100µs
Figure 31. Large-Signal Transient Response
VS = 5V
AV = 1
RL = 100kΩ
CL = 50pF
TA = 25°C
2.5V
VS = 2.75V
AV = 1
RL = 100kΩ
CL = 50pF
TA = 25°C
0.5V
00291-031
VS = ±1.35V
AV = 1
RL = 100kΩ
CL = 50pF
TA = 25°C
0mV
Figure 30. Large-Signal Transient Response
200µs
Figure 32. No Phase Reversal
Rev. D | Page 11 of 20
00291-032
A2
OP281/OP481
120
A2
VIN = ±1V p-p
AT = 2kHz
VS = 5V
TA = 25°C
RL = ∞
105
CHANNEL SEPARATION (dB)
0V
VS = ±1.35V
RL = ∞
100
90
10
90
75
60
45
30
15
0
0%
50µs
–30
100
1k
10k
100k
FREQUENCY (Hz)
Figure 33. Saturation Recovery Time
A2
0V
100
Figure 35. Channel Separation vs. Frequency
CIRCUIT = AVOL
VS = 2.5V
TA = 25°C
RL = ∞
90
10
1V
500mV
100µs
00291-034
0%
Figure 34. Saturation Recovery Time
Rev. D | Page 12 of 20
1M
00291-035
500mV
00291-033
–15
500mV
OP281/OP481
APPLICATIONS
The OPx81 family of op amps is comprised of extremely low
powered, rail-to-rail output amplifiers, requiring less than 4 μA of
quiescent current per amplifier. Many other competitors’ devices
may be advertised as low supply current amplifiers but draw
significantly more current as the outputs of these devices are driven
to a supply rail. The supply current of the OPx81 remains under
4 μA even when the output is driven to either supply rail. Supply
currents should meet the specification as long as the inputs and
outputs remain within the range of the power supplies.
Figure 36 shows a simplified schematic of a single channel for
the OPx81. A bipolar differential pair is used in the input stage.
PNP transistors are used to allow the input stage to remain
linear with the common-mode range extending to ground. This
is an important consideration for single-supply applications.
The bipolar front end also contributes less noise than a MOS
front end with only nanoamps of bias currents. The output of
the op amp consists of a pair of CMOS transistors in a common
source configuration. This setup allows the output of the
amplifier to swing to within millivolts of either supply rail. The
headroom required by the output stage is limited by the amount
of current being driven into the load. The lower the output
current, the closer the output can go to either supply rail.
Figure 11, Figure 12, and Figure 13 show the output voltage
headroom vs. the load current. This behavior is typical of railto-rail output amplifiers.
VCC
to the lowest possible input signal excursion and can be found
using the following formula:
R=
V EE − V IN , MIN
0.5 × 10 −3
where:
VEE is the negative power supply for the amplifier.
VIN, MIN is the lowest input voltage excursion expected.
For example, a single channel of the OPx81 should be used with a
single-supply voltage of +5 V if the input signal may go as low as
−1 V. Because the amplifier is powered from a single supply, VEE is
the ground; therefore, the necessary series resistance should be 2 kΩ.
INPUT OFFSET VOLTAGE
The OPx81 family of op amps was designed for low offset
voltages (less than 1 mV).
100kΩ
+3V
100kΩ
VOUT
100kΩ
–0.27V
+
–
OP281
VIN = 1kHz AT
400mV p-p
100kΩ
–0.1V
00291-037
THEORY OF OPERATION
Figure 37. Single OPx81 Channel Configured as a Difference Amplifier
Operating at VCM < 0 V
INPUT COMMON-MODE VOLTAGE RANGE
The OPx81 is rated with an input common-mode voltage range
from VEE to 1 V less than VCC. However, the op amp can operate
with a common-mode voltage that is slightly less than VEE.
Figure 37 shows a single OPx81 channel configured as a difference
amplifier with a single-supply voltage of 3 V. Negative dc voltages
are applied at both input terminals, creating a common-mode
voltage that is less than ground. A 400 mV p-p input signal is
then applied to the noninverting input. Figure 38 shows the
resulting input and output waves. Notice how the output of the
amplifier also drops slightly negative without distortion.
OUT
+IN
VEE
00291-036
–IN
0.2ms
Figure 36. Simplified Schematic of a Single OPx81 Channel
100
VOUT
90
INPUT OVERVOLTAGE PROTECTION
This can be done by simply placing a resistor in series with the
input to the device. The size of the resistor should be proportional
Rev. D | Page 13 of 20
0V
VIN
10
0%
0.1V
Figure 38. Input and Output Signals with VCM < 0 V
00291-038
The input stage to the OPx81 family of op amps consists of a
PNP differential pair. If the base voltage of either of these input
transistors drops to more than 0.6 V below the negative supply,
the input ESD protection diodes become forward-biased, and
large currents begin to flow. In addition to possibly damaging the
device, this creates a phase reversal effect at the output. To prevent
this, the input current should be limited to less than 0.5 mA.
OP281/OP481
CAPACITIVE LOADING
WINDOW COMPARATOR
Most low supply current amplifiers have difficulty driving
capacitive loads due to the higher currents required from the
output stage for such loads. Higher capacitance at the output
will increase the amount of overshoot and ringing in the amplifier’s
step response and may affect the stability of the device. However,
through careful design of the output stage and its high phase
margin, the OPx81 family can tolerate some degree of capacitive
loading. Figure 39 shows the step response of a single channel
with a 10 nF capacitor connected at the output. Notice that the
overshoot of the output does not exceed more than 10% with
such a load, even with a supply voltage of only 3 V.
The extremely low power supply current demands of the OPx81
family make it ideal for use in long-life battery-powered
applications such as a monitoring system. Figure 41 shows a
circuit that uses the OP281 as a window comparator.
3V
3V
3V
R1
VH
D1
A1
R2
VIN
5.1kΩ
OP281-A
10kΩ
VOUT
Q1
5.1kΩ
2kΩ
3V
3V
R3
100
90
D2
VL
A2
00291-041
OP281-B
R4
Figure 41. Using the OP281 as a Window Comparator
10
00291-039
0%
Figure 39. Ringing and Overshoot of the Output of the Amplifier
MICROPOWER REFERENCE VOLTAGE GENERATOR
Many single-supply circuits are configured with the circuit biased
to half of the supply voltage. In these cases, a false ground reference
can be created by using a voltage divider buffered by an amplifier.
Figure 40 shows the schematic for such a circuit.
The two 1 MΩ resistors generate the reference voltage while
drawing only 1.5 μA of current from a 3 V supply. A capacitor
connected from the inverting terminal to the output of the op amp
provides compensation to allow a bypass capacitor to be
connected at the reference output. This bypass capacitor helps
to establish an ac ground for the reference output. The entire
reference generator draws less than 5 μA from a 3 V supply source.
3V TO 12V
The threshold limits for the window are set by VH and VL,
provided that VH > VL. The output of the first OP281 (A1) will
stay at the negative rail, in this case ground, as long as the input
voltage is less than VH. Similarly, the output of the second
OP281 (A2) will stay at ground as long the input voltage is
higher than VL. As long as VIN remains between VL and VH, the
outputs of both op amps will be 0 V. With no current flowing in
either D1 or D2, the base of Q1 will stay at ground, putting the
transistor in cutoff and forcing VOUT to the positive supply rail.
If the input voltage rises above VH, the output of A2 stays at
ground, but the output of A1 goes to the positive rail and D1
conducts current. This creates a base voltage that turns on Q1
and drives VOUT low. The same condition occurs if VIN falls
below VL with A2’s output going high and D2 conducting
current. Therefore, VOUT is high if the input voltage is between
VL and VH, but low if the input voltage moves outside of that range.
The R1 and R2 voltage divider sets the upper window voltage,
and the R3 and R4 voltage divider sets the lower voltage for the
window. For the window comparator to function properly, VH
must be a greater voltage than VL.
10kΩ
0.022µF
2
1MΩ
3
4
1
100Ω
VREF
1.5V TO 6V
1µF
00291-040
1MΩ
1µF
R2
R1 + R2
VL =
R4
R3 + R4
The 2 kΩ resistor connects the input voltage of the input
terminals to the op amps. This protects the OP281 from
possible excess current flowing into the input stages of the
devices. D1 and D2 are small-signal switching diodes (1N4446
or equivalent), and Q1 is a 2N2222 or an equivalent NPN
transistor.
8
OP281
VH =
Figure 40. Single Channel Configured as a Micropower Bias Voltage Generator
Rev. D | Page 14 of 20
OP281/OP481
In the design of power-supply control circuits, a great deal of
design effort is focused on ensuring the long-term reliability of
a pass transistor over a wide range of load current conditions.
As a result, monitoring and limiting device power dissipation is
of primary importance in these designs. Figure 42 shows an
example of a 5 V, single-supply current monitor that can be
incorporated into the design of a voltage regulator with foldback current limiting or a high current power supply with
crowbar protection. The design capitalizes on the OPx81’s
common-mode range extending to ground. Current is
monitored in the power-supply return path, where a 0.1 Ω
shunt resistor, RSENSE, creates a very small voltage drop. The
voltage at the inverting terminal becomes equal to the voltage at
the noninverting terminal through the feedback of Q1, which is
a 2N2222 or an equivalent NPN transistor. This makes the
voltage drop across R1 equal to the voltage drop across RSENSE.
Therefore, the current through Q1 becomes directly
proportional to the current through RSENSE, and the output
voltage is given by the following equation:
R1
R2
100kΩ
100kΩ
3V
3V
2kΩ
VIN = 2V p-p
A2
A1
OP281-A
OP281-B
HALF-WAVE
RECTIFIED
OUTPUT
Figure 43. Single-Supply Full-Wave and Half-Wave Rectifiers Using an OP281
100
90
SCALE
0.1V/DIV
10
SCALE
0.1ms/DIV
0%
00291-044
R2
× R SENSE × I L ⎞⎟
VOUT = VCC − ⎛⎜
⎝ R1
⎠
The voltage drop across R2 increases as IL increases; therefore,
VOUT decreases if a higher supply current is sensed. For the
element values shown, the VOUT transfer characteristic is
−2.5 V/A, decreasing from VCC.
VCC
R2
2.49kΩ
VOUT
Q1
VCC
0.1Ω
RSENSE
SINGLE
CHANNEL
OPx81
RETURN TO
GROUND
00291-042
R1
100Ω
FULL-WAVE
RECTIFIED
OUTPUT
00291-043
LOW-SIDE CURRENT MONITOR
Figure 44. Full-Wave Rectified Signal
Amplifier A1 is used as a voltage follower that tracks the input
voltage only when it is greater than 0 V. This provides a halfwave rectification of the input signal to the noninverting
terminal of Amplifier A2. When A1’s output is following the
input, the inverting terminal of A2 also follows the input from
the virtual ground between the inverting and noninverting
terminals of A2. With no potential difference across R1, no
current flows through either R1 or R2; therefore, the output of
A2 also follows the input. When the input voltage goes below
0 V, the noninverting terminal of A2 becomes 0 V. This makes
A2 work as an inverting amplifier with a gain of 1 and provides
a full-wave rectified version of the input signal. A 2 kΩ resistor
in series with A1’s noninverting input protects the device when
the input signal becomes less than ground.
BATTERY-POWERED TELEPHONE HEADSET
AMPLIFIER
Figure 42. Low-Side Load Current Monitor
LOW VOLTAGE HALF-WAVE AND FULL-WAVE
RECTIFIERS
Because of its quick overdrive recovery time, an OP281 can be
configured as a full-wave rectifier for low frequency (<500 Hz)
applications. Figure 43 shows the schematic.
Figure 45 shows how the OP281 can be used as a two-way
amplifier in a telephone headset. One side of the OP281 can be
used as an amplifier for the microphone, and the other side can
be used to drive the speaker. A typical telephone headset uses a
600 Ω speaker and an electret microphone that requires a
supply voltage and a biasing resistor.
Rev. D | Page 15 of 20
OP281/OP481
0.1µF
11kΩ
3V
3V
2.2kΩ
3V
1µF
1µF 1MΩ
MIC OUT
OP281-A
ELECTRET 1MΩ
MIC
1µF 10kΩ
audio bandwidth. A 2.2 kΩ resistor is used to bias the electret
microphone. This resistor value may vary depending on the
specifications of the microphone. The output of the microphone is
ac-coupled to the noninverting terminal of the op amp. Two 1 MΩ
resistors are used to provide the dc offset for single-supply use.
300kΩ
50kΩ
3V
20kΩ
3V
Q1
INPUT 1µF
3V
1µF
10kΩ
POT.
OP281-B
1µF
1MΩ
20kΩ
600Ω
SPEAKER
00291-045
Q2
1MΩ
Figure 45. Two-Way Amplifier in a Battery-Powered Telephone Headset
The OP281-A op amp provides about 29 dB of gain for audio
signals coming from the microphone. The gain is set by the
300 kΩ and 11 kΩ resistors. The gain bandwidth product of the
amplifier is 95 kHz, which yields a −3 dB rolloff at 3.4 kHz for
the set gain of 28. This is acceptable because telephone audio is
band limited for 300 kHz to 3 kHz signals. If higher gain is
required for the microphone, an additional gain stage should be
used, because adding more gain to the OP281 would limit the
The OP281-B amplifier (see Figure 45) can provide up to 15 dB of
gain for the headset speaker. Incoming audio signals are ac-coupled
to a 10 kΩ potentiometer that is used to adjust the volume. Again,
two 1 MΩ resistors provide the dc offset with a 1 μF capacitor
establishing an ac ground for the volume-control potentiometer.
Because the OP281 is a rail-to-rail output amplifier, it would have
difficulty driving a 600 Ω speaker directly. Here, a Class AB buffer
is used to isolate the load from the amplifier and to provide the
necessary current to drive the speaker. By placing the buffer in
the feedback loop of the op amp, crossover distortion can be
minimized. Q1 and Q2 should have minimum betas of 100. The
600 Ω speaker is ac-coupled to the emitters to prevent quiescent
current from flowing into the speaker. The 1 μF coupling capacitor
makes an equivalent high-pass filter cutoff at 265 Hz with a 600 Ω
load attached. Again, this does not pose a problem because it is
outside the frequency range for telephone audio signals.
The circuit in Figure 45 draws around 250 μA of current. The
Class AB buffer has a quiescent current of 140 μA, and roughly
100 μA is drawn by the microphone itself. A CR2032 3 V
lithium battery has a life expectancy of 160 mA hours, which
means this circuit can run continuously for 640 hours on a
single battery.
Rev. D | Page 16 of 20
OP281/OP481
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
4.00 (0.1574)
3.80 (0.1497)
Figure 46. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
8
14
1
7
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 47. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
Rev. D | Page 17 of 20
060606-A
4.00 (0.1575)
3.80 (0.1496)
OP281/OP481
3.10
3.00
2.90
8
5
4.50
4.40
4.30
1
6.40 BSC
4
PIN 1
0.65 BSC
0.15
0.05
1.20
MAX
COPLANARITY
0.10
0.30
0.19
SEATING 0.20
PLANE
0.09
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AA
Figure 48. 8-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-8)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
1.05
1.00
0.80
0.65
BSC
1.20
MAX
0.15
0.05
0.30
0.19
0.20
0.09
SEATING
COPLANARITY
PLANE
0.10
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 49. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model
OP281GRU-REEL
OP281GRUZ-REEL 1
OP281GS
OP281GS-REEL
OP281GS-REEL7
OP281GSZ1
OP281GSZ-REEL1
OP281GSZ-REEL71
OP481GRU-REEL
OP481GRUZ-REEL1
OP481GS
OP481GS-REEL
OP481GS-REEL7
OP481GSZ1
OP481GSZ-REEL1
OP481GSZ-REEL71
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
8-Lead TSSOP
8-Lead TSSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
14-Lead TSSOP
14-Lead TSSOP
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
Z = RoHS Compliant Part.
Rev. D | Page 18 of 20
Package Option
RU-8
RU-8
R-8
R-8
R-8
R-8
R-8
R-8
RU-14
RU-14
R-14
R-14
R-14
R-14
R-14
R-14
OP281/OP481
NOTES
Rev. D | Page 19 of 20
OP281/OP481
NOTES
©1996–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00291-0-9/08(D)
Rev. D | Page 20 of 20
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