® OPA111 Low Noise Precision Difet ® OPERATIONAL AMPLIFIER FEATURES APPLICATIONS ● LOW NOISE: 100% Tested, 8nV√Hz max (10kHz) ● PRECISION INSTRUMENTATION ● DATA ACQUISITION ● TEST EQUIPMENT ● ● ● ● ● LOW BIAS CURRENT: 1pA max LOW OFFSET: 250µV max LOW DRIFT: 1µV/°C max HIGH OPEN-LOOP GAIN: 120dB min HIGH COMMON-MODE REJECTION: 100dB min ● OPTOELECTRONICS ● MEDICAL EQUIPMENT—CAT SCANNER ● RADIATION HARD EQUIPMENT DESCRIPTION The OPA111 is a precision monolithic dielectrically isolated FET (Difet ®) operational amplifier. Outstanding performance characteristics allow its use in the most critical instrumentation applications. Case and Substrate +VCC 8 7 Noise, bias current, voltage offset, drift, open-loop gain, common-mode rejection, and power supply rejection are superior to BIFET® amplifiers. –In 2 +In 3 Noise-Free Cascode* Very low bias current is obtained by dielectric isolation with on-chip guarding. Laser trimming of thin-film resistors gives very low offset and drift. Extremely low noise is achieved with patented circuit design techniques. A new cascode design allows high precision input specifications and reduced susceptibility to flicker noise. Standard 741 pin configuration allows upgrading of existing designs to higher performance levels. Output 6 Trim 10kΩ 1 Trim 10kΩ 5 *Patented 2kΩ 2kΩ 2kΩ 2kΩ –VCC 4 BIFET® National Semiconductor Corp., Difet ® Burr-Brown Corp. SBOS138 International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1984 Burr-Brown Corporation PDS-526K Printed in U.S.A. August, 1995 SPECIFICATIONS ELECTRICAL At VCC = ±15VDC and TA = +25°C unless otherwise noted. OPA111AM PARAMETER CONDITION MIN OPA111BM TYP MAX 40 15 8 6 0.7 1.6 9.5 0.5 MIN OPA111SM TYP MAX 80 40 15 8 1.2 3.3 15 0.8 30 11 7 6 0.6 1.2 7.5 0.4 ±100 ±2 110 ±3 ±500 ±5 MIN TYP MAX UNITS 60 30 12 8 1 2.5 12 0.6 40 15 8 6 0.7 1.6 9.5 0.5 80 40 15 8 1.2 3.3 15 0.8 nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms µVp-p fAp-p fA/√Hz ±250 ±1 ±10 ±100 ±2 110 ±3 ±500 ±5 ±31 ±50 ±0.5 110 ±3 ±31 µV µV/°C dB µV/V INPUT NOISE Voltage, fO = 10Hz fO = 100Hz fO = 1kHz fO = 10kHz fB = 10Hz to 10kHz fB = 0.1Hz to 10Hz Current, fB = 0.1Hz to 10Hz fO = 0.1Hz thru 20kHz 100% 100% 100% 100% 100% Tested Tested Tested Tested Tested (1) (1) (1) VOLTAGE(2) OFFSET Input Offset Voltage Average Drift Supply Rejection VCM = 0VDC TA = TMIN to TMAX VCC = ±10V to ±18V 90 100 90 CURRENT(2) BIAS Input Bias Current VCM = 0VDC ±0.8 ±2 ±0.5 ±1 ±0.8 ±2 pA OFFSET CURRENT(2) Input Offset Current VCM = 0VDC ±0.5 ±1.5 ±0.25 ±0.75 ±0.5 ±1.5 pA IMPEDANCE Differential Common-Mode 1013 || 1 1014 || 3 VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection 1013 || 1 1014 || 3 1013 || 1 1014 || 3 Ω || pF Ω || pF VIN = ±10VDC ±10 90 ±11 110 ±10 100 ±11 110 ±10 90 ±11 110 V dB RL ≥ 2kΩ 114 125 120 125 114 125 dB 20Vp-p, RL = 2kΩ VO = ±10V, RL = 2kΩ Gain = –1, RL = 2kΩ 10V Step 16 1 2 32 2 6 10 MHz kHz V/µs µs µs 5 µs ±12 ±10 100 1000 40 V mA Ω pF mA ±15 VDC OPEN-LOOP GAIN, DC Open-Loop Voltage Gain FREQUENCY RESPONSE Unity Gain, Small Signal Full Power Response Slew Rate Settling Time, 0.1% 0.01% Overload Recovery, 50% Overdrive(3) Gain = –1 2 32 2 6 10 16 1 5 2 32 2 6 10 16 1 5 RATED OUTPUT Voltage Output Current Output Output Resistance Load Capacitance Stability Short Circuit Current RL = 2kΩ VO = ±10VDC DC, Open Loop Gain = +1 ±11 ±5.5 10 ±12 ±10 100 1000 40 ±11 ±5.5 10 ±12 ±10 100 1000 40 ±11 ±5.5 10 POWER SUPPLY Rated Voltage Voltage Range, Derated Performance Current, Quiescent ±15 ±15 ±5 IO = 0mADC ±18 3.5 ±5 +85 +125 +150 –25 –55 –65 2.5 2.5 ±18 3.5 ±5 +85 +125 +150 –55 –55 –65 2.5 ±18 3.5 VDC mA +125 +125 +150 °C °C °C °C/W TEMPERATURE RANGE Specification Operating Storage θ Junction-Ambient Ambient Temp. Ambient Temp. Ambient Temp. –25 –55 –65 200 200 200 NOTES: (1) Sample tested—this parameter is guaranteed. (2) Offset voltage, offset current, and bias current are measured with the units fully warmed up. (3) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURRBROWN product for use in life support devices and/or systems. ® OPA111 2 ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) At VCC = ±15VDC and TA = TMIN to TMAX unless otherwise noted. OPA111AM PARAMETER CONDITION MIN Ambient Temp. –25 TYP OPA111BM MAX MIN +85 –25 TYP OPA111SM MAX MIN +85 –55 TYP MAX UNITS +125 °C ±1500 ±5 ±50 µV µV/°C dB µV/V TEMPERATURE RANGE Specification Range INPUT OFFSET VOLTAGE(1) Input Offset Voltage Average Drift Supply Rejection VCM = 0VDC VCC = ±10V to ±18V 86 ±220 ±2 100 ±10 ±1000 ±5 ±500 ±1 ±50 ±110 ±0.5 100 ±10 ±32 ±300 ±2 100 ±10 90 86 CURRENT(1) BIAS Input Bias Current VCM = 0VDC ±50 ±250 ±30 ±130 ±820 ±4100 pA OFFSET CURRENT(1) Input Offset Current VCM = 0VDC ±30 ±200 ±15 ±100 ±510 ±3100 pA VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection VIN = ±10VDC ±10 86 ±11 100 ±10 90 ±11 100 ±10 86 ±11 100 V dB RL ≥ 2kΩ 110 120 114 120 110 120 dB RL = 2kΩ VO = ±10VDC VO = 0VDC ±10.5 ±5.25 10 ±11 ±10 40 ±11 ±5.25 10 ±11.5 ±10 40 ±11 ±5.25 10 ±11.5 ±10 40 V mA mA OPEN-LOOP GAIN, DC Open-Loop Voltage Gain RATED OUTPUT Voltage Output Current Output Short Circuit Current POWER SUPPLY Current, Quiescent IO = 0mADC 2.5 3.5 2.5 3.5 2.5 3.5 mA NOTES: (1) Offset voltage, offset current, and bias current are measured with the units fully warmed up. CONNECTION DIAGRAM Top View ABSOLUTE MAXIMUM RATINGS Supply ........................................................................................... ±18VDC Internal Power Dissipation(1) ......................................................... 750mW Differential Input Voltage(2) .......................................................... ±36VDC Input Voltage Range(2) ................................................................ ±18VDC Storage Temperature Range ......................................... –65°C to +150°C Operating Temperature Range ..................................... –55°C to +125°C Lead Temperature (soldering, 10s) ............................................... +300°C Output Short Circuit Duration(3) .............................................. Continuous Junction Temperature .................................................................... +175°C Substrate and Case 8 Offset Trim 1 –In 2 7 +VCC OPA111 6 4 5 Offset Trim +In 3 Output NOTES: (1) Packages must be derated based on θJC = 150°C/W or θJA = 300°C/W. (2) For supply voltages less than ±18VDC, the absolute maximum input voltage is equal to +18V > VIN > –VCC – 6V. See Figure 2. (3) Short circuit may be to power supply common only. Rating applies to +25°C ambient. Observe dissipation limit and TJ. –V CC PACKAGE INFORMATION PACKAGE DRAWING MODEL OPA111AM OPA111BM OPA111SM PACKAGE NUMBER(1) TO-99 TO-99 TO-99 001 001 001 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL OPA111AM OPA111BM OPA111SM TEMPERATURE OFFSET VOLTAGE, PACKAGE RANGE MAX (µV) TO-99 TO-99 TO-99 –25°C to +85°C –25°C to +85°C –55°C to +125°C ±500 ±250 ±500 ® 3 OPA111 DICE INFORMATION PAD FUNCTION 1 2 3 4 5 6 7 8 Offset Trim –In +In –VS Offset Trim Output +VS Substrate Substrate Bias: This Dielectrically-Isolated Substrate is normally connected to common. MECHANICAL INFORMATION Die Size Die Thickness Min. Pad Size OPA111AD DIE TOPOGRAPHY MILS (0.001") MILLIMETERS 95 x 71 ±5 20 ±3 4x4 2.41 x 1.80 ±0.13 0.51 ±0.08 0.10 x 0.10 Backing: Transistor Count: None 44 TYPICAL PERFORMANCE CURVES TA = +25°C, VCC = ±15VDC unless otherwise noted. INPUT CURRENT NOISE SPECTRAL DENSITY INPUT VOLTAGE NOISE SPECTRAL DENSITY 1k Voltage Noise (nV/ Hz) Current Noise (fA/√Hz 100 10 1 BM 0.1 100 AM, SM BM 10 1 1 10 100 1k 10k 100k 1M 1 Frequency (Hz) 100 1k Frequency (Hz) ® OPA111 10 4 10k 100k 1M TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC unless otherwise noted. TOTAL* INPUT VOLTAGE NOISE SPECTRAL DENSITY vs SOURCE RESISTANCE TOTAL* INPUT VOLTAGE NOISE (PEAK-TO-PEAK) vs SOURCE RESISTANCE 1k 1k Voltage Noise (nV/ Hz) RS = 10MΩ Voltage Noise (µVp-p) RS = 1MΩ 100 RS = 100kΩ BM 10 RS = 100Ω *Includes contribution from source resistance. *Includes contribution from source resistance. 100 BM fB = 0.1Hz to 10Hz 10 1 1 0.1 1 10 100 1k 10k 104 100k 105 106 107 108 Frequency (Hz) Source Resistance (Ω) VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs TEMPERATURE BIAS AND OFFSET CURRENT vs TEMPERATURE 1k 100 12 109 1010 1k fO = 1kHz 0.1 6 4 –75 –50 –25 0 25 50 75 100 10 1 1 0.1 –50 –25 0 25 50 75 Temperature (°C) Ambient Temperature (°C) BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE POWER SUPPLY REJECTION vs FREQUENCY 1 Bias Current Offset Current 0.1 0.1 0.01 0.01 –10 –5 0 5 10 100 0.01 125 1M 10M 140 Power Supply Rejection (dB) 1 Offset Current (pA) Bias Current (pA) BM 10 0.01 10 –15 100 0.1 0.01 125 10 Bias Current (pA) Current Noise (fA/√Hz) 1 8 Offset Current (pA) Voltage Noise (nV/√Hz) 100 10 10 120 100 80 60 40 20 0 15 1 Common-Mode Voltage (V) 10 100 1k 10k 100k Frequency (Hz) ® 5 OPA111 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC unless otherwise noted. COMMON-MODE REJECTION vs FREQUENCY COMMON-MODE REJECTION vs INPUT COMMON MODE VOLTAGE 120 120 Common-Mode Rejection (dB) 100 80 60 40 20 110 100 90 80 0 1 70 –15 Frequency (Hz) –5 0 5 Common-Mode Voltage (V) OPEN-LOOP FREQUENCY RESPONSE GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE 10 100 1k 10k 100k 1M 10M 140 10 15 4 4 3 3 2 2 1 1 –45 80 –90 Phase Margin ≈ 65°C 60 Gain 40 –135 Gain Bandwidth (MHz) 100 Phase Shift (Degrees) Voltage Gain (dB) 120 –10 20 0 –180 1 10 100 1k 10k 100k 1M –75 –50 –25 Frequency (Hz) 0 25 50 75 0 125 100 125 Ambient Temperature (°C) GAIN-BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE OPEN-LOOP GAIN vs TEMPERATURE 3 3 2 2 140 1 1 Voltage Gain (dB) 130 Slew Rate (V/µs) Gain Bandwidth (MHz) 100 0 10M 120 110 0 0 0 5 10 15 100 –75 20 ® OPA111 –50 –25 0 25 50 Ambient Temperature (°C) Supply Voltage (±VCC) 6 75 Slew Rate (V/µs) Common-Mode Rejection (dB) 140 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC unless otherwise noted. COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE MAXIMUM UNDISTORTED OUTPUT VOLTAGE vs FREQUENCY 120 Common-Mode Rejection (dB) Output Voltage (Vp-p) 30 20 10 10k 100k 100 90 80 70 –15 0 1k 110 1M –10 Frequency (Hz) 15 100 40 Settling Time (µs) 80 20 0 –20 60 0.01% 40 0.1% 20 –40 0 –60 0 1 2 3 5 4 1 10 Time (µs) 100 1k Closed-Loop Gain (V/V) SUPPLY CURRENT vs TEMPERATURE INPUT OFFSET VOLTAGE WARM-UP DRIFT 4 20 Offset Voltage Change (µV) Output Voltage (mV) 10 SETTLING TIME vs CLOSED-LOOP GAIN SMALL SIGNAL TRANSIENT RESPONSE 60 Supply Current (mA) –5 0 5 Common-Mode Voltage (V) 3 2 1 0 10 0 –10 –20 –75 –50 –25 0 25 50 75 100 125 0 Ambient Temperature (°C) 1 2 3 4 5 6 Time From Power Turn-On (Minutes) ® 7 OPA111 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC unless otherwise noted. INPUT OFFSET VOLTAGE CHANGE DUE TO THERMAL SHOCK Offset Voltage Change (µV) 150 AM 75 BM 0 25°C 85°C TA = 25°C to TA = 85°C Air Environment –75 –150 –1 0 1 2 3 4 5 Time From Thermal Shock (Minutes) APPLICATIONS INFORMATION 2 I IN OFFSET VOLTAGE ADJUSTMENT Input Current (mA) The OPA111 offset voltage is laser-trimmed and will require no further trim for most applications. As with most amplifiers, externally trimming the remaining offset can change drift performance by about 0.3µV/°C for each 100µV of adjusted offset. Note that the trim (Figure 1) is similar to operational amplifiers such as 741 and AD547. The OPA111 can replace most other amplifiers by leaving the external null circuit unconnected. 0 Maximum Safe Current –2 –15 –10 –5 0 5 10 15 Input Voltage (V) FIGURE 2. Input Current vs Input Voltage with ±VCC Pins Grounded. Static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers (both bipolar and FET types), this may cause a noticeable degradation of offset voltage and drift. Static protection is recommended when handling any precision IC operational amplifier. +VCC 7 2 OPA111 Maximum Safe Current V –1 INPUT PROTECTION Conventional monolithic FET operational amplifiers require external current-limiting resistors to protect their inputs against destructive currents that can flow when input FET gate-to-substrate isolation diodes are forward-biased. Most BIFET amplifiers can be destroyed by the loss of –VCC. 3 1 6 1 FIGURE 1. Offset Voltage Trim. GUARDING AND SHIELDING As in any situation where high impedances are involved, careful shielding is required to reduce “hum” pickup in input leads. If large feedback resistors are used, they should also be shielded along with the external input circuitry. Unlike BIFET amplifiers, The Difet OPA111 requires input current limiting resistors only if its input voltage is greater than 6V more negative than –VCC. A 10kΩ series resistor will limit input current to a safe level with up to ±15V input levels, even if both supply voltages are lost. Leakage currents across printed circuit boards can easily exceed the bias current of the OPA111. To avoid leakage problems, it is recommended that the signal input lead of the OPA111 be wired to a Teflon standoff. If the OPA111 is to be soldered directly into a printed circuit board, utmost care must be used in planning the board layout. A “guard” pattern 5 4 –VCC 10kΩ to 1M trim potentiometer (100kΩ recommended). ±10mV typical trim range. ® OPA111 8 should completely surround the high impedance input leads and should be connected to a low impedance point which is at the signal input potential. Voltage Noise Spectral Density, EO Typical at 1kHz (nV/ Hz) 1k The amplifier case should be connected to any input shield or guard via pin 8. This insures that the amplifier itself is fully surrounded by guard potential, minimizing both leakage and noise pickup (see Figure 3). If guarding is not required, pin 8 (case) should be connected to ground. Non-Inverting RS 100 EO = eN2 + (INRS)2 + 4kTRS 10 OPA111 + Resistor Resistor Noise Only OP-27 + Resistor 1 100 Buffer OP-27 + Resistor OPA111 + Resistor Resistor Noise Only EO 1k 10k 100k BM 1M 10M Source Resistance, RS (Ω) 2 OPA111 In 2 8 6 8 Out OPA111 3 In FIGURE 4. Voltage Noise Spectral Density vs Source Resistance. Out 6 3 80 TO-99 Bottom View 4 In 3 2 OPA111 3 6 5 Input Bias Current (pA) Inverting 6 Out 7 8 2 8 1 Board layout for input guarding: guard top and bottom of board. Alternate: use Teflon® standoff for sensitive input pins. Teflon® E. I. Du Pont de Nemours & Co. TA = 25°C; curves taken from manufacturers' published typical data. 60 LF156/157 40 20 0 LF155 AD547 OPA111 OP-15/16/17 "Perfect Bias Current Cancellation" –20 –15 –10 –5 0 5 10 15 Common-Mode Voltage (VDC) FIGURE 3. Connection of Input Guard. FIGURE 5. Input Bias Currrent vs Common-Mode Voltage. NOISE: FET VERSUS BIPOLAR Low noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in many cases, so consider the effect of source resistance on overall operational amplifier noise performance. At low source impedances, the lower voltage noise of a bipolar operational amplifier is superior, but at higher impedances the high current noise of a bipolar amplifier becomes a serious liability. Above about 15kΩ, the OPA111 will have a lower total noise than an OP-27 (see Figure 4). 1000pF Polystyrene 1000MΩ 2 3 Pyroelectric Detector BIAS CURRENT CHANGE VERSUS COMMON-MODE VOLTAGE The input bias current of most popular BIFET operational amplifiers are affected by common-mode voltage (Figure 5). Higher input FET gate-to-drain voltage causes leakage and ionization (bias) currents to increase. Due to its cascode input stage, the extremely low bias current of the OPA111 is not compromised by common-mode voltage. 1000MΩ 8 OPA111 6 Output NOTE: Pyroelectric detectors respond to rate-of-change (AC signal) only. FIGURE 6. Pyroelectric Infrared Detector. APPLICATIONS CIRCUITS Figures 6 through 18 are circuit diagrams of various applications for the OPA111. ® 9 OPA111 –46dBm to –20dBm RF Input 1000pF RFC <1pF to prevent gain peaking. 10kΩ 100Ω 1000MΩ 2 OPA111 3 H-P HSCH-3486 eO 6 DC Output +15V 0.1µF Guard 1MΩ 8 2 eO ≈ 1200mVDC/µW H-P 5082-4204 Pin Photodiode Video bandwidth: DC to 50kHz Output 6 5 x 108V/W 0.1µF 3 0.01µF FIGURE 7. Zero-Bias Schottky Diode Square-Law RF Detector. 7 OPA111 4 1000MΩ –15V Circuit must be well shielded. FIGURE 10. Sensitive Photodiode Amplifier. RF 500pA IIN 100MΩ 2 6 OPA111 3 Offset voltage = 255µVDC maximum with no offset adjust. eO = 50mV 2 6 eO = –IIN RF 5.34MΩ* OPA111BM 5.34MΩ* Output Pin Photodiode 3 Input 1000pF Light Rays Q Scintillation Crystal X-Rays (Pencil Beam) 2kΩ 2.67MΩ* 500pF *For 50Hz use: 3.16MΩ and 6.37MΩ 500pF FIGURE 11. 60Hz Reject Filter. CF 100pF 1010Ω RF Collimator 2 X-Ray Tube 8 FIGURE 8. Computerized Axial Tomography (CAT) Scanner Channel Amplifier. Output 6 OPA111 eO ∆Q 3 100pF 1010Ω eO = –∆Q/CF Low frequency cutoff = 1/(2 π RFCF) = 0.16Hz 500Ω 9.5kΩ Guard +15V 8 2 7 OPA111 3 6 FIGURE 12. Piezoelectric Transducer Charge Amplifier. 1VDC Output 4 5 1 pH Probe R ≈ 500MΩ 50mV Output Offset Trim 100kΩ –15V 1µF 2 375.1kΩ 187.5kΩ 1µF 3 8 OPA111 6 ® 10 Out FC = 0.6Hz –80dB at 60Hz FIGURE 13. 0.6Hz Second-Order Low-Pass Filter. FIGURE 9. High Impedance (1014Ω) Amplifier. OPA111 375.1kΩ In 10.5kΩ 0.03µF <1pF to prevent peaking Overload ≈ 0.1µW input 0.01µF 200MΩ +5VDC 73.2kΩ 365Ω 2 2 365Ω 6 Input 3 1µF 3 OPA111 6 20kΩ OPA111 0.01µF RT Pin Diode* Output 100kΩ 2 10kΩ 7 LM211 TTL Output 1 0.1µF *Silicon Detector Corp. SD-041-11-21-011 CT 3 Digital Common G = 26dB Midband FIGURE 15. High Sensitivity (under 1nW) Fiber Optic Receiver for 9600 Baud Manchester Data. FIGURE 14. RIAA Equalized Phono Preamplifier. 100Ω 10kΩ 2 Input 3 100Ω 6 10kΩ 6 10kΩ 6 10kΩ OPA111 10kΩ 2 3 100Ω AV = –1010 eN = 1.9nV/√Hz typ* at 10kHz BW = 30kHz typ GBW = 30.3MHz typ VOS = ±16µV typ* ∆VOS/∆T = ±0.16µV/°C typ* IB = 10pA max ZIN ≈ 1012Ω || 30pF OPA111 10kΩ 2 3 100Ω OPA111 10kΩ * Theoretical performance achievable from OPA111BM with uncorrelated random distribution of parameters. 2 3 100Ω 6 10kΩ 6 10kΩ OPA111 10kΩ 2 3 10kΩ OPA111 2 6 3 Output OPA37 N = 10 OPA111BM FIGURE 16. ‘N’ Stage Parallel-Input Amplifier for Reduced Relative Amplifier Noise at the Output. ® 11 OPA111 IB = 1pA Gain = 100 CMRR ≈ 106dB RIN = 1013Ω 3 –In 6 OPA111 2 RF 2 25kΩ 3 25kΩ 25kΩ 5 5kΩ RG 101Ω 6 RF 5kΩ Burr-Brown INA105 Differential Amplifier 25kΩ 2 6 OPA111 3 +In Output 1 Differential Voltage Gain = 1 + 2RF/RG FIGURE 17. FET Input Instrumentation Amplifier. ≈10pF 10kΩ 1MΩ 2 8 IN914* 2 Input 3 2N4117* 3507J OPA111 6 Output 6 IN914* 8 30pF *Reverse polarity for negative peak detection. FIGURE 18. Low-Droop Positive Peak Detector. ® OPA111 3 12 0.01µF Polystyrene Droop ≈ 100µV/s PACKAGE OPTION ADDENDUM www.ti.com 19-Apr-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty OPA111AM NRND TO-99 LMC 8 20 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA111BM NRND TO-99 LMC 8 1 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA111SM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI OPA111SMQ OBSOLETE TO-99 LMC 8 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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