Burr-Brown OPA3832IDG4 Triple, low-power, high-speed, fixed-gain operational amplifier Datasheet

 OP
A3
832
OPA
3832
OPA3832
®
SBOS370 – DECEMBER 2006
Triple, Low-Power, High-Speed, Fixed-Gain Operational Amplifier
FEATURES
•
•
•
•
•
•
•
Using complementary common-emitter outputs
provides an output swing to within 30mV of ground
and 60mV of the positive supply. The high output
drive current and low differential gain and phase
errors also make it ideal for single-supply consumer
video products.
HIGH BANDWIDTH: 80MHz (G = +2)
LOW SUPPLY CURRENT: 3.9mA/ch (VS = +5V)
FLEXIBLE SUPPLY RANGE:
±1.5V to ±5.5V Dual Supply
+3V to +11V Single Supply
INPUT RANGE INCLUDES GROUND ON
SINGLE SUPPLY
4.9VPP OUTPUT SWING ON +5V SUPPLY
HIGH SLEW RATE: 350V/µs
LOW INPUT VOLTAGE NOISE: 9.3nV/√Hz
Low distortion operation is ensured by high
bandwidth (80MHz) and slew rate (350V/µs), making
the OPA3832 an ideal input buffer stage to 3V and
5V CMOS converters. Unlike earlier low-power,
single-supply amplifiers, distortion performance
improves as the signal swing is decreased. A low
9.3nV/√Hz input voltage noise supports wide
dynamic range operation.
APPLICATIONS
•
•
•
•
The OPA3832 is available in an industry-standard
SO-14 package or a small TSSOP-14 package.
SINGLE-SUPPLY VIDEO LINE DRIVERS
CCD IMAGING CHANNELS
LOW-POWER ULTRASOUND
PORTABLE CONSUMER ELECTRONICS
RELATED PRODUCTS
DESCRIPTION
SINGLES
DUALS
TRIPLES
QUADS
Rail-to-Rail Output
OPA830
OPA2830
—
OPA4830
DESCRIPTION
Rail-to-Rail Fixed-Gain
OPA832
OPA2832
—
—
The OPA3832 is a triple, low-power, high-speed,
fixed-gain amplifier designed to operate on a single
+3V to +11V supply. Operation on ±1.5V to ±5.5V
supplies is also supported. The input range extends
below ground and to within 1.7V of the positive
supply.
General-Purpose
(1800V/µs slew rate)
OPA690
OPA2690
OPA3690
—
Low-Noise,
High dc Precision
OPA820
OPA2822
—
OPA4820
V1
100W
1/3
OPA3832
4.99kW
400W
V2
0.1mF
400W
100W
1/3
OPA3832
400W
0.1mF
4.99kW
REFT
+3.5V
0.1mF
REFB
+1.5V
+In
400W
ADS826
10-Bit
60MSPS
100pF
-In
CM
V3
100W
1/3
OPA3832
400W
400W
0.1mF
Selection
Logic
Multiplexed Converter Driver
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
OPA3832
www.ti.com
SBOS370 – DECEMBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
OPA3832
SO-14 (2)
D
–40°C to +85°C
OPA3832
OPA3832
TSSOP-14
PW
–40°C to +85°C
OPA3832
(1)
(2)
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA3832ID
Rails, 50
OPA3832IDR
Tape and Reel, 2500
OPA3832IPW
Rails, 90
OPA3832IPWR
Tape and Reel, 2000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Available Q1 '07.
ABSOLUTE MAXIMUM RATINGS (1)
Power Supply
12VDC
Internal Power Dissipation
See Thermal
Characteristics
Differential Input Voltage (2)
±1.2V
Input Voltage Range
–0.5V to ±VS + 0.3V
Storage Voltage Range: D, PW
–40°C to +125°C
Lead Temperature (soldering, 10s)
+300°C
Maximum Junction Temperature (TJ)
+150°C
Maximum Junction Temperature: Continuous Operation, Long Term Reliability
+140°C
ESD Rating:
Human Body Model (HBM)
2000V
Charge Device Model (CDM)
1000V
Machine Model (MM)
(1)
(2)
200V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Noninverting input to internal inverting mode.
PIN ASSIGNMENT
D, PW PACKAGES
SO-14, TSSOP-14
(TOP VIEW)
2
DIS A
1
DIS B
2
DIS C
3
+VS
4
+Input A
5
-Input A
6
Output A
7
14 Output B
400W
400W
B
13 -Input B
12 +Input B
11 -VS
A
400W
400W
10 +Input C
C
400W
400W
Submit Documentation Feedback
9
-Input C
8
Output C
OPA3832
www.ti.com
SBOS370 – DECEMBER 2006
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted.
OPA3832ID, IPW
PARAMETER
CONDITIONS
+25°C
G = +1, VO ≤ 0.5VPP
250
+25°C (1)
0°C to
+70°C (2)
–40°C to
+85°C (2)
UNITS
MIN/
MAX
TEST
LEVEL (3)
MHz
typ
C
B
AC PERFORMANCE
Small-Signal Bandwidth
G = +2, VO ≤ 0.5VPP
80
55
54
54
MHz
min
G = –1, VO ≤ 0.5VPP
110
57
56
55
MHz
min
B
VO ≤ 0.5VPP
6
dB
typ
C
Slew Rate
G = +2, 2V Step
325
220
210
200
V/µs
min
B
Rise Time
0.5V Step
5.0
5.8
6.0
6.0
ns
max
B
Fall Time
0.5V Step
5.0
5.8
6.0
6.0
ns
max
B
Settling Time to 0.1%
G = +2, 1V Step
45
63
65
66
ns
max
B
Harmonic Distortion
VO = 2VPP, 5MHz
RL = 150Ω
–57
–54
–52
–50
dBc
max
B
RL = 500Ω
–65
–62
–61
–60
dBc
max
B
RL = 150Ω
–60
–50
–49
–48
dBc
max
B
RL = 500Ω
–75
–64
–60
–57
dBc
max
B
f > 1MHz
9.2
nV/√Hz
typ
C
Peaking at a Gain of +1
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Input Current Noise
f > 1MHz
2.2
pA/√Hz
typ
C
NTSC Differential Gain
RL = 150Ω
0.10
%
typ
C
NTSC Differential Phase
RL = 150Ω
0.16
°
typ
C
2 Channels Driven at 5MHz, 1VPP
3rd Channel Measured
–55
dBc
typ
C
G = +2
±0.3
±1.5
±1.6
±1.7
%
min
A
G = –1
±0.2
±1.5
±1.6
±1.7
%
max
B
Maximum
400
455
460
462
Ω
max
B
Minimum
400
345
340
338
Ω
max
B
±0.1
±0.1
%/°C
max
B
±9.3
±9.7
mV
max
A
±27
±27
µV/°C
max
B
+12
+13
µA
max
A
±45
±45
nA/°C
max
B
±2
±2.5
µA
max
A
±10
±10
nA/°C
max
B
All Hostile Crosstalk, Input Referred
DC PERFORMANCE (4)
Gain Error
Internal RF and RG
Average Drift
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
±1.4
±8.0
—
+5.5
+10
—
±0.1
±1.5
—
INPUT
Negative Input Voltage Range
–5.4
–5.2
–5.0
–4.9
V
max
B
Positive Input Voltage Range
3.2
3.1
3.0
2.9
V
min
B
Input Impedance
(1)
(2)
(3)
(4)
Differential Mode
10 | | 2.1
kΩ | | pF
typ
C
Common-Mode
400 | | 1.2
kΩ | | pF
typ
C
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +13°C at high temperature limit for over
temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
Current is considered positive out of node.
Submit Documentation Feedback
3
OPA3832
www.ti.com
SBOS370 – DECEMBER 2006
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted.
OPA3832ID, IPW
PARAMETER
CONDITIONS
+25°C
+25°C (1)
0°C to
+70°C (2)
–40°C to
+85°C (2)
UNITS
MIN/
MAX
TEST
LEVEL (3)
RL = 1kΩ to GND
±4.9
±4.8
±4.75
±4.75
V
max
A
RL = 150Ω to GND
±4.6
±4.5
±4.45
±4.4
V
max
A
±82
±63
±58
±53
mA
min
A
OUTPUT
Output Voltage Swing
Current Output, Sinking and Sourcing
Short-Circuit Current
Closed-Loop Output Impedance
Output Shorted to Either Supply
120
mA
typ
C
G = +2, f ≤ 100kHz
0.2
Ω
typ
C
VDIS = 0, All Channels
0.95
mA
max
A
VIN = 1VDC
40
µs
typ
C
DISABLE (Disabled LOW)
Power Down Supply Current (+VS)
DIsable Time
2.5
2.6
2.7
Enable Time
VIN = 1VDC
20
ns
typ
C
Off Isolation
G = +2V/V, 5MHz
-75
dB
typ
C
pF
typ
C
Output Capacitance in Disable
Turn-On Glitch
G = +2V/V, RL = 150Ω, VIN = 0V
8
mV
typ
C
Turn-Off Glitch
G = +2V/V, RL = 150Ω, VIN = 0V
2
mV
typ
C
Enable Voltage
4.5
4.5
4.5
V
min
A
Disable Voltage
3.0
3.0
3.0
V
max
A
300
350
400
µA
max
A
Control Pin Input Bias Current (DIS)
VDIS = 0V, Each Channel
125
POWER SUPPLY
Minimum Operating Voltage
±1.4
V
min
B
Maximum Operating Voltage
—
±5.5
±5.5
±5.5
V
max
A
Maximum Quiescent Current
All Channels, VS = ±5V
12.75
14.4
16.1
17.9
mA
max
A
Minimum Quiescent Current
All Channels, VS = ±5V
12.75
12
10.8
9.3
mA
min
A
Input-Referred
66
61
60
59
dB
min
A
–40 to +85
°C
typ
C
Power-Supply Rejection Ratio
(-PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IPW
Thermal Resistance
4
D
SO-14
85
°C/W
typ
C
PW
TSSOP-14
100
°C/W
typ
C
Submit Documentation Feedback
OPA3832
www.ti.com
SBOS370 – DECEMBER 2006
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted.
OPA3832ID, IPW
PARAMETER
CONDITIONS
+25°C
G = +1, VO ≤ 0.5VPP
210
+25°C (1)
0°C to
+70°C (2)
–40°C to
+85°C (2)
UNITS
MIN/
MAX
TEST
LEVEL (3)
MHz
typ
C
B
AC PERFORMANCE
Small-Signal Bandwidth
G = +2, VO ≤ 0.5VPP
80
56
55
55
MHz
min
G = –1, VO ≤ 0.5VPP
105
60
58
58
MHz
min
B
VO ≤ 0.5VPP
7
dB
typ
C
Slew Rate
G = +2, 2V Step
350
230
220
220
V/µs
min
B
Rise Time
0.5V Step
5.2
5.8
5.8
5.9
ns
max
B
Fall Time
0.5V Step
5.2
5.8
5.8
5.9
ns
max
B
Settling Time to 0.1%
G = +2, 1V Step
46
64
66
67
ns
max
B
Harmonic Distortion
VO = 2VPP, 5MHz
RL = 150Ω
–54
–51
–50
–49
dBc
max
B
RL = 500Ω
–60
–57
–55
–54
dBc
max
B
RL = 150Ω
–57
–50
–49
–47
dBc
max
B
RL = 500Ω
–79
–65
–62
–58
dBc
max
B
f > 1MHz
9.3
nV/√Hz
typ
C
Peaking at a Gain of +1
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Input Current Noise
f > 1MHz
2.3
pA/√Hz
typ
C
NTSC Differential Gain
RL = 150Ω
0.11
%
typ
C
NTSC Differential Phase
RL = 150Ω
0.14
°
typ
C
G = +2
±0.3
±1.5
±1.6
±1.7
%
min
A
G = –1
±0.2
±1.5
±1.6
±1.7
%
max
B
400
455
460
462
Ω
max
A
400
345
DC PERFORMANCE (4)
Gain Error
Internal RF and RG, Maximum
Minimum
Average Drift
Input Offset Voltage
±1.5
Average Offset Voltage Drift
Input Bias Current
—
VCM = 2.0V
Input Bias Current Drift
Input Offset Current
±6.5
+5.5
+10
—
VCM = 2.0V
Input Offset Current Drift
±0.1
±1.5
—
340
338
Ω
max
A
±0.1
±0.1
%/°C
max
B
±7.5
±8.0
mV
max
A
±25
±25
µV/°C
max
B
+12
+13
µA
max
A
±45
±45
nA/°C
max
B
±2
±2.5
µA
max
A
±10
±10
nA/°C
max
B
B
INPUT
Least Positive Input Voltage
–0.5
–0.2
0
+0.1
V
max
Most Positive Input Voltage
3.3
3.2
3.1
3.0
V
min
B
Input Impedance, Differential Mode
10 | | 2.1
kΩ | | pF
typ
C
Common-Mode
400 | | 1.2
kΩ | | pF
typ
C
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
RL = 1kΩ to 2.0V
0.03
0.16
0.18
0.20
V
max
A
RL = 150Ω to 2.0V
0.18
0.3
0.35
0.40
V
max
A
RL = 1kΩ to 2.0V
4.94
4.8
4.6
4.4
V
min
A
RL = 150Ω to 2.0V
4.86
4.6
4.5
4.4
V
min
A
±75
±58
±53
±50
mA
min
A
Current Output, Sinking and Sourcing
Short-Circuit Output Current
Closed-Loop Output Impedance
(1)
(2)
(3)
(4)
Output Shorted to Either Supply
100
mA
typ
C
G = +2, f ≤ 100kHz
0.2
Ω
typ
C
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +6°C at high temperature limit for over
temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
Current is considered positive out of node.
Submit Documentation Feedback
5
OPA3832
www.ti.com
SBOS370 – DECEMBER 2006
ELECTRICAL CHARACTERISTICS: VS = +5V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted.
OPA3832ID, IPW
PARAMETER
CONDITIONS
+25°C
+25°C (1)
0°C to
+70°C (2)
–40°C to
+85°C (2)
UNITS
MIN/
MAX
TEST
LEVEL (3)
VDIS = 0, All Channels
0.7
1.4
1.5
1.5
mA
max
A
VIN = 1VDC
40
µs
typ
C
DISABLE (Disabled LOW)
Power Down Supply Current (+VS)
DIsable Time
Enable Time
VIN = 1VDC
20
ns
typ
C
Off Isolation
G = +2V/V, 5MHz
-75
dB
typ
C
pF
typ
C
Output Capacitance in Disable
Turn-On Glitch
G = +2V/V, RL = 150Ω, VIN = 0V
2
mV
typ
C
Turn-Off Glitch
G = +2V/V, RL = 150Ω, VIN = 0V
6
mV
typ
C
Enable Voltage
4.5
4.5
4.5
V
min
A
Disable Voltage
3.0
3.0
3.0
V
max
A
300
350
400
µA
max
A
Control Pin Input Bias Current (DIS)
VDIS = 0V, Each Channel
125
POWER SUPPLY
Minimum Operating Voltage
+2.8
V
typ
C
Maximum Operating Voltage
—
+11
+11
+11
V
max
A
Maximum Quiescent Current
All Channels, VS = +5V
11.7
12.6
14.7
16.8
mA
max
A
Minimum Quiescent Current
All Channels, VS = +5V
11.7
11.1
10.5
9
mA
min
A
Input-Referred
66
61
60
59
dB
min
A
–40 to +85
°C
typ
C
Power-Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IPW
Thermal Resistance
6
D
SO-14
85
°C/W
typ
C
PW
TSSOP-14
100
°C/W
typ
C
Submit Documentation Feedback
OPA3832
www.ti.com
SBOS370 – DECEMBER 2006
ELECTRICAL CHARACTERISTICS: VS = +3.3V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 0.75V, unless otherwise noted.
OPA3832ID, IPW
PARAMETER
CONDITIONS
+25°C
G = +1, VO ≤ 0.5VPP
180
+25°C (1)
0°C to
+70°C (2)
UNITS
MIN/
MAX
TEST
LEVEL (3)
MHz
typ
C
B
AC PERFORMANCE
Small-Signal Bandwidth
G = +2, VO ≤ 0.5VPP
90
59
57
MHz
min
G = –1, VO ≤ 0.5VPP
100
63
61
MHz
min
B
VO ≤ 0.5VPP
8
dB
typ
C
Slew Rate
1V Step
150
110
100
V/µs
min
B
Rise Time
0.5V Step
4.4
5.6
5.7
ns
max
B
Fall Time
0.5V Step
4.4
5.6
5.7
ns
max
B
1V Step
48
70
80
ns
max
B
RL = 150Ω
–60
–54
–51
dBc
max
B
RL = 500Ω
–67
–63
–57
dBc
max
B
RL = 150Ω
–66
–60
–55
dBc
max
B
RL = 500Ω
–80
–66
–62
dBc
max
B
Input Voltage Noise
f > 1MHz
9.4
nV/√Hz
typ
C
Input Current Noise
f > 1MHz
2.4
pA/√Hz
typ
C
G = +2
±0.3
±1.5
±1.6
%
min
A
G = –1
±0.2
±1.5
±1.6
%
max
B
Maximum
400
455
460
Ω
max
B
Minimum
400
345
340
Ω
max
B
±0.1
%/°C
max
B
±1.4
±6.5
±7.7
mV
max
A
±27
µV/°C
max
B
+12
µA
max
A
±45
nA/°C
max
B
±2
µA
max
A
±10
nA/°C
max
B
Peaking at a Gain of +1
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
5MHz
DC PERFORMANCE (4)
Gain Error
Internal RF and RG
Average Drift
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
—
VCM = 0.75V
Input Bias Current Drift
Input Offset Current
+5.5
+10
—
VCM = 0.75V
Input Offset Current Drift
±0.1
±1.5
—
INPUT
Least Positive Input Voltage
–0.5
–0.3
–0.2
V
max
B
Most Positive Input Voltage
1.5
1.4
1.3
V
min
B
Input Impedance
Differential Mode
10 | | 2.1
kΩ | | pF
typ
C
Common-Mode
400 | | 1.2
kΩ | | pF
typ
C
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
RL = 1kΩ to 0.75V
0.03
0.16
0.18
V
max
B
RL = 150Ω to 0.75V
0.1
0.3
0.35
V
max
B
RL = 1kΩ to 0.75V
3
2.8
2.6
V
min
B
RL = 150Ω to 0.75V
3
2.8
2.6
V
min
B
±35
±25
±20
mA
min
A
Current Output, Sinking and Sourcing
Short-Circuit Output Current
Closed-Loop Output Impedance
(1)
(2)
(3)
(4)
Output Shorted to Either Supply
80
mA
typ
C
See Figure 2, f < 100kHz
0.2
Ω
typ
C
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +4°C at high temperature limit for over
temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
Current is considered positive out of node.
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SBOS370 – DECEMBER 2006
ELECTRICAL CHARACTERISTICS: VS = +3.3V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 0.75V, unless otherwise noted.
OPA3832ID, IPW
PARAMETER
CONDITIONS
+25°C
+25°C (1)
0°C to
+70°C (2)
UNITS
MIN/
MAX
TEST
LEVEL (3)
VDIS = 0, All Channels
0.4
0.8
0.85
mA
max
A
VIN = 1VDC
40
µs
typ
C
DISABLE (Disabled LOW)
Power Down Supply Current (+VS)
DIsable Time
Enable Time
VIN = 1VDC
20
ns
typ
C
Off Isolation
G = +2V/V, 5MHz
-75
dB
typ
C
pF
typ
C
Output Capacitance in Disable
Turn-On Glitch
G = +2V/V, RL = 150Ω, VIN = 0V
2
mV
typ
C
Turn-Off Glitch
G = +2V/V, RL = 150Ω, VIN = 0V
6
mV
typ
C
Enable Voltage
2.8
2.8
V
min
A
Disable Voltage
1.3
1.3
V
max
A
130
140
µA
max
A
Control Pin Input Bias Current (DIS)
VDIS = 0V, Each Channel
73
POWER SUPPLY
Minimum Operating Voltage
+2.8
V
typ
C
Maximum Operating Voltage
—
+11
+11
V
max
A
A
Maximum Quiescent Current
All Channels, VS = +3.3V
11.4
12.2
14.5
mA
max
Minimum Quiescent Current
All Channels, VS = +3.3V
11.4
10.2
9.5
mA
min
A
Input-Referred
60
dB
typ
C
–40 to +85
°C
typ
C
Power-Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IPW
Thermal Resistance
8
D
SO-14
85
°C/W
typ
C
PW
TSSOP-14
100
°C/W
typ
C
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SBOS370 – DECEMBER 2006
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
3
VO = 0.2VPP
RL = 150W
0
0
Normalized Gain (dB)
Normalized Gain (dB)
G = -1V/V
-3
G = +2V/V
-6
-9
VO = 0.5VPP
-3
-6
VO = 1VPP
-9
VO = 2VPP
-12
-12
-15
-15
1
10
100
400
G = +2V/V
RL = 150W
1
10
Frequency (MHz)
Figure 1.
Figure 2.
NONINVERTING PULSE RESPONSE
1.5
0.3
1.0
0.5
Small-Signal Pulse
Response ±0.1V
Left Scale
0
0.4
0
-0.1
-0.5
-0.2
-1.0
-0.3
-1.5
-0.4
-2.0
Small-Signal Output Voltage (V)
0.1
Large-Signal Pulse Response ±1V
Right Scale
2.0
G = -1V/V
RL = 150W
1.5
0.2
1.0
0.1
0.5
Small-Signal Pulse
Response ±0.1V
Left Scale
0
-0.1
-1.0
-0.3
-0.4
-1.5
-2.0
Time (10ns/div)
Figure 4.
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Normalized Gain to Capacitive Load (dB)
REQUIRED RS vs CAPACITIVE LOAD
1dB Peaking Targeted
35
30
25
20
15
10
5
0
100
-0.5
Large-Signal Pulse Response ±1V
Right Scale
Figure 3.
10
0
-0.2
Time (10ns/div)
40
400
INVERTING PULSE RESPONSE
2.0
Large-Signal Output Voltage (V)
0.2
RS (W)
Small-Signal Output Voltage (V)
G = +2V/V
RL = 150W
100
Frequency (MHz)
0.4
0.3
VO = 4VPP
Large-Signal Output Voltage (V)
3
1k
3
CL = 10pF
0
-3
CL = 1000pF
-6
CL = 100pF
-9
VI
1/3
OPA3832
RS
CL
-12
1kW
(1)
NOTE: (1) 1kW is optional.
-15
1
10
100
Capacitive Load (pF)
Frequency (MHz)
Figure 5.
Figure 6.
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SBOS370 – DECEMBER 2006
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted.
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-50
-55
-55
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
HARMONIC DISTORTION vs LOAD RESISTANCE
-50
-60
2nd-Harmonic
-65
-70
3rd-Harmonic
-75
-80
G = +2V/V
VO = 2VPP
f = 5MHz
-85
-60
2nd-Harmonic
-65
-70
3rd-Harmonic
-75
-80
-85
-90
-90
-95
100
1k
0.5
2.5
3.5
4.5
5.5
Output Swing (VPP)
Figure 7.
Figure 8.
6.5
7.5
8.5 9.0
2-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
3rd-Order Spurious Level (dBc)
-40
G = +2V/V
RL = 500W
VO = 2VPP
-50
1.5
Load Resistance (W)
HARMONIC DISTORTION vs FREQUENCY
-40
Harmonic Distortion (dBc)
G = +2V/V
RL = 500W
f = 5MHz
2nd-Harmonic
-60
-70
-80
-90
3rd-Harmonic
-100
-45
PI
-50
1/3
50W OPA3832
PO
20MHz
500W
400W
-55
-60
400W
10MHz
-65
-70
-75
-80
-85
5MHz
-90
-95
-100
-110
0.1
1
10
20
-26
-22
Frequency (MHz)
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
RL = 500W
VO (V)
RL = 50W
0
RL = 100W
-1
1W Internal
Power Limit
One Channel Only
-2
-3
-4
-5
Output
Current Limit
-6
-160
4
Maximum Output Voltage (V)
4
1
G = +2V/V
VS = ±5V
-2
2
6
Positive Output Voltage
3
2
1
0
-1
-2
-3
Negative Output Voltage
-4
-5
-120
-80
-40
0
40
80
120
160
10
IO (mA)
100
RL (W)
Figure 11.
10
-6
OUTPUT SWING vs LOAD RESISTANCE
5
Output
Current Limit
5
1W Internal
Power Limit
One Channel Only
-10
Figure 10.
6
2
-14
Single-Tone Load Power (dBm)
Figure 9.
3
-18
Figure 12.
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SBOS370 – DECEMBER 2006
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to GND, unless otherwise noted.
CHANNEL-TO-CHANNEL CROSSTALK REJECTION
ALL HOSTILE CROSSTALK REJECTION
COMPOSITE VIDEO dG/dP
1.2
-30
No Pull-Down
With 1.3kW Pull-Down
VI
1.0
75W
1/3
OPA3832
Video
Loads
Optional
1.3kW
Pull-Down
400W
dG/dP
0.8
-35
Crosstalk, Input Referred (dB)
+5V
400W
dP
- 5V
0.6
dP
0.4
dG
0.2
dG
-40
-45
All Hostile
-50
-55
-60
-65
Channel-to-Channel
-70
-75
-80
0
-85
1
2
3
4
0.1
1
10
Number of 150W Loads
Frequency (MHz)
Figure 13.
Figure 14.
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SBOS370 – DECEMBER 2006
TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, Differential Gain = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
VO = 0.2VPP
RL = 500W
G = -1V/V
0
-3
G = +2V/V
-6
-9
-12
VO = 1VPP
-3
VO = 0.5VPP
-6
-9
VO = 2VPP
-12
-15
-15
1
10
100
300
1
10
Frequency (MHz)
Figure 15.
Figure 16.
NONINVERTING PULSE RESPONSE
Large-Signal Pulse Response ±1V
Right Scale
2.7
2.6
2.9
4.0
2.8
3.5
3.0
Small-Signal Pulse
Response ±0.1V
Left Scale
2.5
2.4
2.5
2.0
2.3
1.5
2.2
1.0
2.1
0.5
Small-Signal Output Voltage (V)
G = +2V/V
RL = 150W
300
INVERTING PULSE RESPONSE
4.5
Large-Signal Output Voltage (V)
Small-Signal Output Voltage (V)
2.9
2.8
100
Frequency (MHz)
4.5
G = -1V/V
RL = 150W
4.0
2.7
3.5
2.6
3.0
Small-Signal Pulse
Response ±0.1V
Left Scale
2.5
2.4
2.3
2.5
2.0
1.5
Large-Signal Pulse Response ±1V
Right Scale
2.2
2.1
1.0
0.5
Time (10ns/div)
Time (10ns/div)
Figure 17.
Figure 18.
COMPOSITE VIDEO dG/dP
DISABLE FEEDTHROUGH vs FREQUENCY
1.2
-50
Input Referred
+5V
-55
1/3
OPA3832
-60
400W
0.8
dG/dP
Video
Loads
Feedthrough (dB)
1.0
VI
dP
400W
0.6
0.4
dG
-65
-70
-75
-80
-85
0.2
-90
0
-95
1
2
3
4
1
Figure 19.
12
10
Frequency (MHz)
Number of 150W Loads
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100
Large-Signal Output Voltage (V)
Normalized Gain (dB)
0
LARGE-SIGNAL FREQUENCY RESPONSE
3
Normalized Gain (dB)
3
OPA3832
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SBOS370 – DECEMBER 2006
TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, Differential Gain = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
-30
-50
2nd-Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-55
-60
-65
-70
3rd-Harmonic
-75
-80
-85
G = +2V/V
VO = 2VPP
f = 5MHz
-90
-95
-40
Input Limited
-50
-60
2nd-Harmonic
-70
3rd-Harmonic
-80
-90
-100
100
1k
3
5
6
Figure 21.
G = +2V/V
RL = 500W
VO = 2VPP
-40
-60
-70
-80
-90
3rd-Harmonic
-100
10
11
G = -1V/V
RL = 500W
f = 5MHz
-50
2nd-Harmonic
-60
-70
-80
-90
3rd-Harmonic
-100
-110
-110
0.1
1
10
20
0.1
1
Frequency (MHz)
10
20
Frequency (MHz)
Figure 22.
Figure 23.
HARMONIC DISTORTION vs OUTPUT VOLTAGE
2-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
-40
G = +2V/V
RL = 500W
f = 5MHz
3rd-Order Spurious Level (dBc)
Harmonic Distortion (dBc)
9
G = –1V/V, HARMONIC DISTORTION vs FREQUENCY
-30
2nd-Harmonic
-50
8
Figure 20.
-50
-40
7
(+) Supply Voltage (V)
Harmonic Distortion (dBc)
-40
4
Load Resistance (W)
G = +2V/V, HARMONIC DISTORTION vs FREQUENCY
-30
Harmonic Distortion (dBc)
G = +2V/V
RL = 500W
f = 5MHz
2nd-Harmonic
-60
-70
3rd-Harmonic
-80
-90
-45
PI
50W
-50
1/3
OPA3832
PO
500W
400W
-55
20MHz
400W
-60
-65
10MHz
-70
-75
-80
5MHz
-85
-90
-95
-100
-100
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-24 -22 -20 -18 -16 -14 -12 -10
-8
Output Voltage Swing (VPP)
Single-Tone Load Power (2dBm/div)
Figure 24.
Figure 25.
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-4
-2
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SBOS370 – DECEMBER 2006
TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, Differential Gain = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted.
POWER-SUPPLY REJECTION RATIO AND
COMMON-MODE REJECTION RATIO VS FREQUENCY
INPUT VOLTAGE AND CURRENT NOISE
80
70
PSRR and CMRR (dB)
Input Voltage Noise (nV/ÖHz)
Input Current Noise (pA/ÖHz)
100
Voltage Noise (9.3nV/ÖHz)
10
CMRR
60
50
+PSRR
40
30
20
10
Current Noise (2.3pA/ÖHz)
1
0
100
1k
10k
100k
1M
100
10M
1k
10k
Figure 26.
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
400W
4.0
+5V
Output Impedance (W)
3.5
3.0
2.5
2.0
1.5
400W
10
1/3
OPA3832
ZO
200W
1
1.0
Least Negative Output Voltage
0
0.1
10
100
1k
1k
10k
100k
Frequency (Hz)
Figure 28.
Figure 29.
VOLTAGE RANGES vs TEMPERATURE
10
Input Offset Voltage (VOS)
2.5
2.0
Most Positive Output Voltage
Most Positive Input Voltage
RL = 150W
2.0
1.5
1.0
0.5
0
Least Positive Output Voltage
Input Offset Voltage (mV)
3.0
100M
TYPICAL DC DRIFT OVER TEMPERATURE
4.5
3.5
10M
2.5
5.0
4.0
1M
RL (W)
8
1.5
6
Bias Current (IB)
1.0
4
0.5
2
0
0
10 x Input Offset (IOS)
-0.5
Least Positive Input Voltage
-2
-0.5
-1.0
-50
-1.0
0
50
90
-4
-40
-20
20
40
60
80
100
Ambient Temperature (20°C/div)
Ambient Temperature (10°C/div)
Figure 30.
14
0
Figure 31.
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120
140
Input Bias and Offset Current (mA)
Maximum Output Voltage (V)
100M
Most Positive Output Voltage
0.5
Voltage Ranges (V)
10M
100
G = +2V/V
VS = +5V
4.5
1M
Figure 27.
OUTPUT SWING vs LOAD RESISTANCE
5.0
100k
Frequency (Hz)
Frequency (Hz)
OPA3832
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SBOS370 – DECEMBER 2006
TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, Differential Gain = +2V/V, and RL = 150Ω to VCM = 2V, unless otherwise noted.
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
11
5
VDIS
Output Current, Sinking
9
40
8
Supply Current
20
7
0
6
Output Voltage (V)
60
Supply Current (mA)
10
Output Current, Sourcing
1
-1
1.2
1.0
0.8
0.6
0.4
VIN = = 0.5VDC
0.2
0.0
-20
0
20
40
60
80
100
120
-0.2
140
Time (10ms/div)
Ambient Temperature (20°C/div)
Figure 32.
Figure 33.
DISABLE/ENABLE GLITCH
5
VDIS
3
1
-1
4
3
2
1
At Matched Load
0
-1
Disable Voltage (V)
-40
Output Voltage (mV)
Output Current (mA)
80
3
Disable Voltage (V)
100
-2
-3
-4
Time (10ms/div)
Figure 34.
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SBOS370 – DECEMBER 2006
TYPICAL CHARACTERISTICS: VS = +3.3V
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 0.75V, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
VO = 0.2VPP
RL = 150W
G = -1V/V
0
-3
G = +2V/V
-6
-9
-12
VO = 1VPP
-3
VO = 0.5VPP
-6
-9
VO = 1.5VPP
G = +2V/V
RL = 150W
-12
-15
-15
1
10
100
300
1
10
Frequency (MHz)
Figure 35.
Figure 36.
NONINVERTING PULSE RESPONSE
G = +2V/V
RL = 150W
Large-Signal Pulse Response ±1V
Right Scale
1.2
1.4
1.6
1.3
1.4
1.1
1.2
Small-Signal Pulse
Response ±0.1V
Left Scale
1.0
0.9
1.0
0.8
0.8
0.6
0.7
0.4
0.6
0.2
Small-Signal Output Voltage (V)
1.3
1.8
G = -1V/V
RL = 150W
1.6
1.2
1.4
1.1
1.0
0.9
Large-Signal Pulse Response ±1V
Right Scale
0.7
0.6
0.2
Figure 38.
Normalized Gain to Capacitive Load (dB)
FREQUENCY RESPONSE vs CAPACITIVE LOAD
1dB Peaking Targeted
40
RS (W)
0.4
Time (10ns/div)
50
30
20
10
0
16
0.8
0.6
REQUIRED RS vs CAPACITIVE LOAD
10
1.0
0.8
Figure 37.
1
1.2
Small-Signal Pulse
Response ±0.1V
Left Scale
Time (10ns/div)
60
300
INVERTING PULSE RESPONSE
1.8
Large-Signal Output Voltage (V)
Small-Signal Output Voltage (V)
1.4
100
Frequency (MHz)
100
1k
3
CL = 10pF
0
CL = 1000pF
-3
CL = 100pF
-6
VI
-9
1/3
OPA3832
CL
1kW
(1)
400W
-12
400W
NOTE: (1) 1kW is optional.
-15
1
10
Capacitive Load (pF)
Frequency (MHz)
Figure 39.
Figure 40.
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100
300
Large-Signal Output Voltage (V)
Normalized Gain (dB)
0
LARGE-SIGNAL FREQUENCY RESPONSE
3
Normalized Gain (dB)
3
OPA3832
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SBOS370 – DECEMBER 2006
TYPICAL CHARACTERISTICS: VS = +3.3V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to VCM = 0.75V, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-50
-60
-55
-60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
2nd-Harmonic
2nd-Harmonic
-65
-70
3rd-Harmonic
G = +2V/V
VO = 1VPP
f = 5MHz
-75
-80
-80
3rd-Harmonic
-90
G = +2V/V
RL = 500W
f = 5MHz
-100
100
1k
0.50
1.00
1.25
Output Voltage Swing (VPP)
Figure 41.
Figure 42.
HARMONIC DISTORTION vs FREQUENCY
TWO-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
1.50
-50
G = +2V/V
RL = 500W
VO = 1VPP
3rd-Order Spurious Level (dBc)
-50
0.75
Load Resistance (W)
-40
-60
2nd-Harmonic
-70
-80
-90
-100
3rd-Harmonic
-110
-55
PI
50W
1/3
OPA3832
PO
20MHz
500W
-60
400W
-65
400W
-70
10MHz
-75
-80
-85
5MHz
-90
-95
-100
0.1
1
10
20
-26
-24
-22
Frequency (MHz)
-20
-18
-16
-14
-12
-10
-8
Single-Tone Load Power (dBm)
Figure 43.
Figure 44.
OUTPUT SWING vs LOAD RESISTANCE
3.3
G = +2V/V
VS = +3.3V
3.0
Maximum Output Voltage (V)
Harmonic Distortion (dBc)
-70
2.7
Most Positive Output Voltage
2.4
2.1
1.8
1.5
1.2
0.9
0.6
Least Positive Output Voltage
0.3
0
10
100
1k
RL (W)
Figure 45.
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SBOS370 – DECEMBER 2006
APPLICATION INFORMATION
WIDEBAND VOLTAGE-FEEDBACK
OPERATION
The OPA3832 is a unity-gain stable, very high-speed
voltage-feedback op amp designed for single-supply
operation (+3V to +11V). The input stage supports
input voltages below ground and to within 1.7V of the
positive supply. The complementary common-emitter
output stage provides an output swing to within
25mV of ground and the positive supply. The
OPA3832 is compensated to provide stable
operation with a wide range of resistive loads.
Figure 46 shows the ac-coupled, gain of +2V/V
configuration used for the +5V Specifications and
Typical Characteristic Curves. For test purposes, the
input impedance is set to 50Ω with the 66.7Ω resistor
to ground in parallel with the 200Ω bias network.
Voltage swings reported in the Electrical
Characteristics are taken directly at the input and
output pins. For the circuit of Figure 46, the total
effective load on the output at high frequencies is
150Ω || 800Ω. The 332Ω and 505Ω resistors at the
noninverting input provide the common-mode bias
voltage. This parallel combination equals the dc
resistance at the inverting input RF), reducing the dc
output offset resulting from input bias current.
VS = +5V
6.8mF
+
505W
0.1mF
VIN
66.7W
2V
332W
400W
+2V
0.1mF
1/3
OPA3832
VOUT
RL
150W
400W
+2V
Figure 46. AC-Coupled, G = +2, +5V
Single-Supply Specification and Test Circuit
Figure 47 shows the ac-coupled, gain of +2V/V
configuration used for the +3.3V Specifications and
Typical Characteristic Curves. For test purposes, the
input impedance is set to 66.5Ω with a resistor to
ground. Voltage swings reported in the Electrical
Characteristics are taken directly at the input and
output pins. For the circuit of Figure 47, the total
18
effective load on the output at high frequencies is
150Ω || 800Ω. The 255Ω and 1.13kΩ resistors at the
noninverting input provide the common-mode bias
voltage. This parallel combination equals the dc
resistance at the inverting input RF), reducing the dc
output offset arising from input bias current.
VS = +3.3V
6.8mF
+
1.13kW
0.1mF
VIN
66.5W
0.1mF
+0.75V
255W
400W
1/3
OPA3832
400W
VOUT
RL
150W
+0.75
0.75V
Figure 47. AC-Coupled, G = +2, +3.3V
Single-Supply Specification and Test Circuit
Figure 48 shows the dc-coupled, gain of +2, dual
power-supply circuit configuration used as the basis
of the ±5V Electrical Characteristics and Typical
Characteristics. For test purposes, the input
impedance is set to 50Ω with a resistor to ground
and the output impedance is set to 150Ω with a
series output resistor. Voltage swings reported in the
specifications are taken directly at the input and
output pins. For the circuit of Figure 48, the total
effective load will be 150Ω || 800Ω. Two optional
components are included in Figure 48. An additional
resistor (175Ω) is included in series with the
noninverting input. Combined with the 25Ω dc source
resistance looking back towards the signal generator,
this configuration gives an input bias current
cancelling resistance that matches the 200Ω source
resistance seen at the inverting input (see the DC
Accuracy and Offset Control section). In addition to
the usual power-supply decoupling capacitors to
ground, a 0.01µF capacitor is included between the
two power-supply pins. In practical printed circuit
board (PCB) board layouts, this optional capacitor
will typically improve the 2nd-harmonic distortion
performance by 3dB to 6dB.
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SBOS370 – DECEMBER 2006
pole set to 3.2kHz for the component values shown).
As discussed for Figure 46, this configuration allows
the midpoint bias formed by one 2kΩ and one 3kΩ
resistor to appear at both the input and output pins.
The midband signal gain is set to +2 (6dB) in this
case. The capacitor to ground on the noninverting
input is intentionally set larger to dominate input
parasitic terms. At a gain of +2, the OPA3832 on a
single supply will show 80MHz small- and
large-signal bandwidth. The resistor values have
been slightly adjusted to account for this limited
bandwidth in the amplifier stage. Tests of this circuit,
shown in Figure 49, illustrate a precise 1MHz, –3dB
point with a maximally-flat passband (above the
3.2kHz ac-coupling corner), and a maximum stop
band attenuation of 36dB.
+5V
0.1mF
6.8mF
+
50W Source
175W
VIN
VO
1/3
OPA3832
50W
150W
0.01mF
400W
400W
+
6.8mF
0.1mF
9
-5V
6
Figure 48. DC-Coupled, G = +2, Bipolar Supply
Specification and Test Circuit
Gain (dB)
3
SINGLE-SUPPLY ACTIVE FILTER
0
-3
-6
-9
The OPA3832, while operating on a single +3.3V or
+5V supply, lends itself well to high-frequency active
filter designs. Again, the key additional requirement
is to establish the dc operating point of the signal
near the supply midpoint for highest dynamic range.
Figure 50 shows an example design of a 1MHz
low-pass Butterworth filter using the Sallen-Key
topology.
-12
-15
-18
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 49. 1MHz, 2nd-Order, Butterworth
Low-Pass Filter
Both the input signal and the gain setting resistor are
ac-coupled using 0.1µF blocking capacitors (actually
giving bandpass response with the low-frequency
+5V
470pF
3kW
0.1mF
205W
866W
VI
2kW
300pF
1/3
OPA3832
400W
2VI
1MHz, 2nd-Order
Butterworth Filter
400W
0.1mF
Figure 50. Single-Supply, High-Frequency Active Filter
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SBOS370 – DECEMBER 2006
HIGH-SPEED INSTRUMENTATION
AMPLIFIER
9
6
3
Gain (dB)
Figure 51 shows an instrumentation amplifier based
on the OPA3832. The offset matching between
inputs makes this an attractive input stage for this
application. The differential-to-single-ended gain for
this circuit is 2.0V/V. The inputs are high impedance,
with only 1pF to ground at each input. The loads on
the OPA3832 outputs are equal for the best
harmonic distortion possible.
0
-3
-6
-9
-12
VOUT
20log
-15
|V1 - V2|
-18
V1
1/3
OPA3832
400W
400W
400W
400W
1/3
OPA3832
200W
1
200W
100
400
1/3
OPA3832
400W
Figure 52. High-Speed Instrumentation Amplifier
Response
VOUT
400W
V2
Figure 51. High-Speed Instrumentation Amplifier
As shown in Figure 52, the OPA3832 used as an
instrumentation amplifier has a 55MHz, –3dB
bandwidth. This data plots a 1VPP output signal using
a low-impedance differential input source.
20
10
Frequency (MHz)
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MULTIPLEXED CONVERTER DRIVER
under control, so the switching glitches for two 0V
inputs are < 20mV. With standard video signals
levels at the inputs, the maximum differential voltage
across the disabled inputs will not exceed the ±1.2V
maximum rating.
The converter driver in Figure 53 multiplexes among
the three input signals. The OPA3832s enable and
disable times support multiplexing among video
signals.
The
make-before-break
disable
characteristic of the OPA3832 ensures that the
output is always under control. To avoid large
switching glitches, switch during the sync or retrace
portions of the video signal—the two inputs should
be almost equal at these times. The output is always
V1
The output resistors isolate the outputs from each
other when switching between channels. The
feedback network of the disabled channels forms
part of the load seen by the enabled amplifier,
attenuating the signal slightly.
100W
1/3
OPA3832
4.99kW
400W
V2
0.1mF
400W
100W
1/3
OPA3832
400W
0.1mF
4.99kW
REFT
+3.5V
0.1mF
REFB
+1.5V
+In
400W
ADS826
10-Bit
60MSPS
100pF
-In
CM
V3
100W
1/3
OPA3832
400W
400W
0.1mF
Selection
Logic
Multiplexed Converter Driver
Figure 53. Multiplexed Converter Driver
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SBOS370 – DECEMBER 2006
LOW-PASS FILTER
The circuit in Figure 54 realizes a 7th-order
Butterworth low-pass filter with a –3dB bandwidth of
1.2pF
47.5W
2MHz. This filter is based on the KRC active filter
topology that uses an amplifier with the fixed gain ≥
1. The OPA3832 makes a good amplifier for this type
of filter. The component values have been adjusted
to compensate of the parasitic effects of the op amp.
49.9W
560pF
110W
VIN
2.2pF
124W
820pF
1/3
OPA3832
255W
1/3
OPA3832
220pF
400W
400W
400W
400W
1.8pF
48.7W
7TH-ORDER BUTTERWORTH
FILTER RESPONSE
95.3W
10
0
Gain (dB)
1/3
OPA3832
680pF
-10
-20
-30
400W
-40
-50
400W
-60
-70
-80
0
1
10
100
Frequency (MHz)
Figure 54. 7th-Order Butterworth Filter
22
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SBOS370 – DECEMBER 2006
DESIGN-IN TOOLS
DEMONSTRATION FIXTURES
Two printed circuit boards (PCBs) are available to
assist in the initial evaluation of circuit performance
using the OPA3832 in its two package options. Both
of these are offered free of charge as unpopulated
PCBs, delivered with a user's guide. The summary
information for these fixtures is shown in Table 1.
Table 1. Demonstration Fixtures by Package
PRODUCT
PACKAGE
ORDERING
NUMBER
LITERATURE
NUMBER
OPA3832ID
SO-14
DEM-OPA-SO-3B
SBOU018
OPA3832IPW
TSSOP-14
DEM-OPA-SSOP-3B
SBOU019
The demonstration fixtures can be requested at the
Texas Instruments web site (www.ti.com) through the
OPA3832 product folder.
MACROMODEL AND APPLICATIONS
SUPPORT
Computer simulation of circuit performance using
SPICE is often a quick way to analyze the
performance of the OPA3832 and its circuit designs.
This is particularly true for video and RF amplifier
circuits where parasitic capacitance and inductance
can play a major role on circuit performance. A
SPICE model for the OPA3832 is available through
the TI web page (www.ti.com). The applications
department is also available for design assistance.
These models predict typical small signal ac,
transient steps, dc performance, and noise under a
wide variety of operating conditions. The models
include the noise terms found in the electrical
specifications of the data sheet. These models do
not attempt to distinguish between the package types
in their small-signal ac performance.
OPERATING SUGGESTIONS
OUTPUT CURRENT AND VOLTAGES
The OPA3832 provides outstanding output voltage
capability. For the +5V supply, under no-load
conditions at +25°C, the output voltage typically
swings closer than 90mV to either supply rail.
The minimum specified output voltage and current
specifications over temperature are set by
worst-case simulations at the cold temperature
extreme. Only at cold startup will the output current
and voltage decrease to the numbers shown in the
ensured tables. As the output transistors deliver
power, the junction temperatures will increase,
decreasing the VBEs (increasing the available output
voltage swing) and increasing the current gains
(increasing the available output current). In
steady-state operation, the available output voltage
and current will always be greater than that shown in
the over-temperature specifications, because the
output stage junction temperatures will be higher
than the minimum specified operating ambient.
To maintain maximum output stage linearity, no
output short-circuit protection is provided. This
configuration will not normally be a problem, since
most applications include a series matching resistor
at the output that will limit the internal power
dissipation if the output side of this resistor is shorted
to ground. However, shorting the output pin directly
to the adjacent positive power-supply pin (8-pin
packages) will, in most cases, destroy the amplifier.
If additional short-circuit protection is required,
consider a small series resistor in the power-supply
leads. This resistor will reduce the available output
voltage swing under heavy output loads.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an
Analog-to-Digital
Converter
(ADC)—including
additional external capacitance which may be
recommended to improve ADC linearity. A
high-speed, high open-loop gain amplifier like the
OPA3832 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the primary considerations are frequency
response flatness, pulse response fidelity, and/or
distortion, the simplest and most effective solution is
to isolate the capacitive load from the feedback loop
by inserting a series isolation resistor between the
amplifier output and the capacitive load.
The Typical Characteristic curves show the
recommended RS versus capacitive load and the
resulting frequency response at the load. Parasitic
capacitive loads greater than 2pF can begin to
degrade the performance of the OPA3832. Long
PCB traces, unmatched cables, and connections to
multiple devices can easily exceed this value. Always
consider this effect carefully, and add the
recommended series resistor as close as possible to
the output pin (see the Board Layout Guidelines
section).
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For a
gain of +2, the frequency response at the output pin
is already slightly peaked without the capacitive load,
requiring relatively high values of RS to flatten the
response at the load. Increasing the noise gain will
also reduce the peaking.
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DISTORTION PERFORMANCE
The OPA3832 provides good distortion performance
into a 150Ω load. Relative to alternative solutions, it
provides exceptional performance into lighter loads
and/or operating on a single +3.3V supply.
Generally, until the fundamental signal reaches very
high frequency or power levels, the 2nd-harmonic will
dominate
the
distortion
with
a
negligible
3rd-harmonic component. Focusing then on the
2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total
load includes the feedback network; in the
noninverting configuration (see Figure 47) this is the
sum of RF + RG, while in the inverting configuration,
only RF needs to be included in parallel with the
actual load.
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage-feedback
op amps usually achieve their slew rate at the
expense of a higher input noise voltage. The
9.2nV/√Hz input voltage noise for the OPA3832,
however, is much lower than comparable amplifiers.
The input-referred voltage noise and the two
input-referred current noise terms (2.2pA/√Hz)
combine to give low output noise under a wide
variety
of
operating
conditions.
Figure 55 shows the op amp noise analysis model
with all the noise terms included. In this model, all
noise terms are taken to be noise voltage or current
density terms in either nV/√Hz or pA/√Hz.
ENI
1/3
OPA3832
RS
EO
IBN
ERS
RF
Ö 4kTRS
4kT
RG
RG
IBI
Ö 4kTRF
4kT = 1.6E - 20J
at 290°K
The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 1 shows the
general form for the output noise voltage using the
terms shown in Figure 55:
EO
ENI
2
4kTRS NG 2
IBN RS
IBI RF
2
4kTRF NG
(1)
Dividing this expression by the noise gain
(NG = (1 + RF/RG)) gives the equivalent
input-referred spot noise voltage at the noninverting
input, as shown in Figure 55:
EN
ENI
2
IBNR S
2
4kTRS
IBIRF
NG
2
4kTRF
NG
(2)
Evaluating these two equations for the circuit and
component values shown in Figure 46 gives a total
output spot noise voltage of 18.8nV/√Hz and a total
equivalent input spot noise voltage of 9.42nV/√Hz.
This total includes the noise added by the resistors.
This total input-referred spot noise voltage is not
much higher than the 9.2nV/√Hz specification for the
op amp voltage noise alone.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband
voltage-feedback op amp allows good output dc
accuracy in a wide variety of applications. The
power-supply current trim for the OPA3832 gives
even tighter control than comparable products.
Although the high-speed input stage does require
relatively high input bias current (typically 5µA out of
each input terminal), the close matching between
them may be used to reduce the output dc error
caused by this current. This configuration matches
the dc source resistances appearing at the two
inputs. Evaluating the configuration of Figure 48
(which has matched dc input resistances), using
worst-case +25°C input offset voltage and current
specifications, gives a worst-case output offset
voltage equal to:
• (NG = noninverting signal gain at dc)
• ±(NG × VOS(MAX)) + RF × IOS(MAX))
• = ±(2 × 80mV) + (400Ω × 1.5µA)
• = –15.4mV to +16.6mV
Figure 55. Noise Analysis Model
24
2
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A fine-scale output offset null, or dc operating point
adjustment, is often required. Numerous techniques
are available for introducing dc offset control into an
op amp circuit. Most of these techniques are based
on adding a dc current through the feedback resistor.
In selecting an offset trim method, one key
consideration is the impact on the desired signal
path frequency response. If the signal path is
intended to be noninverting, the offset control is best
applied as an inverting summing signal to avoid
interaction with the signal source. If the signal path is
intended to be inverting, applying the offset control to
the noninverting input may be considered. Bring the
dc offsetting current into the inverting input node
through resistor values that are much larger than the
signal path resistors. This configuration ensures that
the adjustment circuit has minimal effect on the loop
gain and thus the frequency response.
THERMAL ANALYSIS
Maximum desired junction temperature sets the
maximum allowed internal power dissipation, as
described below. In no case should the maximum
junction temperature be allowed to exceed +150°C.
Operating junction temperature (TJ) is given by
TA + PD × θJA. The total internal power dissipation
(PD) is the sum of quiescent power (PDQ) and
additional power dissipated in the output stage (PDL)
to deliver load power. Quiescent power is simply the
specified no-load supply current times the total
supply voltage across the part. PDL depends on the
required output signal and load, though for resistive
loads connected to midsupply (VS/2), PDL is at a
maximum when the output is fixed at a voltage equal
to VS/4 or 3VS/4. Under this condition, PDL = VS2/(4 ×
RL), where RL includes feedback network loading.
Note that it is the power in the output stage, and not
into the load, that determines internal power
dissipation.
As a worst-case example, compute the maximum TJ
using an OPA3832 (TSSOP-14 package) in the
circuit of Figure 48 operating at the maximum
specified ambient temperature of +85°C and driving
both channels at a 150Ω load at mid-supply.
PD
10V
Maximum T J
12.75mA
85°C
4
3 52
150W 800W
0.276W
276mV
100°C W
113°C
Although this value is still well below the specified
maximum junction temperature, system reliability
considerations may require lower ensured junction
temperatures. The highest possible internal
dissipation will occur if the load requires current to be
forced into the output at high output voltages or
sourced from the output at low output voltages. This
condition puts a high current through a large internal
voltage drop in the output transistors.
BOARD LAYOUT GUIDELINES
Achieving
optimum
performance
with
a
high-frequency amplifier such as the OPA3832
requires careful attention to board layout parasitics
and external component types. Recommendations
that will optimize performance include:
a) Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability; on the noninverting input, it can react with
the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be opened
in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
unbroken elsewhere on the board.
b) Minimize the distance ( < 0.25") from the
power-supply pins to high-frequency 0.1µF
decoupling capacitors. At the device pins, the ground
and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. Each
power-supply connection should always be
decoupled with one of these capacitors. An optional
supply decoupling capacitor (0.1µF) across the two
power supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply
pins. These may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PCB.
c) Careful selection and placement of external
components will preserve the high-frequency
performance. Resistors should be a very low
reactance type. Surface-mount resistors work best
and allow a tighter overall layout. Metal film or
carbon composition axially-leaded resistors can also
provide good high-frequency performance. Again,
keep the leads and PCB traces as short as possible.
Never use wire-wound type resistors in a
high-frequency application. Since the output pin and
inverting input pin are the most sensitive to parasitic
capacitance, always position the series output
resistor, if any, as close as possible to the output pin.
Other network components, such as noninverting
input termination resistors, should also be placed
close to the package.
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d) Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set RS from the typical characteristic curve, Figure 5.
Low parasitic capacitive loads (< 5pF) may not need
an RS since the OPA3832 is nominally compensated
to operate with a 2pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the
signal gain increases (increasing the unloaded phase
margin). If a long trace is required, and the 6dB
signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a
matched impedance transmission line using
microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline layout
techniques). A 50Ω environment is normally not
necessary onboard, and in fact, a higher impedance
environment will improve distortion as shown in the
distortion versus load plots. With a characteristic
board trace impedance defined (based on board
material and trace dimensions), a matching series
resistor into the trace from the output of the
OPA3832 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and the
input impedance of the destination device; this total
effective impedance should be set to match the trace
impedance. If the 6dB attenuation of a
doubly-terminated transmission line is unacceptable,
a long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in this
case and set the series resistor value as shown in
the typical characteristic curve, Figure 5. This
configuration will not preserve signal integrity as well
as a doubly-terminated line. If the input impedance of
the destination device is low, there will be some
signal attenuation as a result of the voltage divider
formed by the series output into the terminating
impedance.
26
e) Socketing a high-speed part is not
recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
that can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the OPA3832 directly onto the
board.
INPUT AND ESD PROTECTION
The OPA3832 is built using a very high-speed,
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins are protected with internal ESD
protection diodes to the power supplies, as shown in
Figure 56.
+VCC
External
Pin
Internal
Circuitry
-VCC
Figure 56. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (that is, in systems with ±15V supply parts
driving into the OPA3832), current-limiting series
resistors should be added into the two inputs. Keep
these resistor values as low as possible, since high
values degrade both noise performance and
frequency response.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
OPA3832ID
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA3832IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA3832IDR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA3832IDRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA3832IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA3832IPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA3832IPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA3832IPWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
OPA3832IPWR
17-May-2007
Package Pins
PW
14
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
MLA
330
12
7.0
5.6
1.6
8
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
OPA3832IPWR
PW
14
MLA
342.9
336.6
28.58
Pack Materials-Page 2
W
Pin1
(mm) Quadrant
12
PKGORN
T1TR-MS
P
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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