PI6C2410 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PCI-X Clock Buffers Product Features • • • • • • • • • • Product Description Four synchronous outputs Selectable divider/multiplier Output Enable control Low phase error < 150 ps Allows clock input to have spread spectrum modulation for EMI reduction Low output skew < 200 ps Low cycle jitter < 200 ps Industrial temperature (40°C to 85°C) 3.3V V supply Packages: 24-pin QSOP (Q) and 24-pin TSSOP (L) PI6C2410 is a low skew, low jitter, PLL clock buffer with divider or multiplier designed for PCI-X application in servers and workstations. There are two selectable input ranges using HF# input: 10-40 MHz and 40-80 MHz. All outputs are synchronized to the input and to the other outputs. Each output can be independently turned off to reduce EMI and power consumption. Block Diagram Pin Configuration OUT0 OUT1 OUT2 OE[0:3] HF# OUT3 CLKIN PLL FBIN FBOUT DIV DIV[0:1] AGND 1 24 CLKIN VCC 2 23 AVCC HF# 3 22 VCC DIV0 4 21 OUT0 DIV1 5 20 OUT1 GND 6 24-Pin Q, L 19 GND GND 7 18 GND FBIN 8 17 OUT2 FBOUT 9 16 OUT3 VCC 10 15 VCC OE0 11 14 OE3 OE1 12 13 OE2 Clock Select Table HF# D IV1 D IV0 OUTx CLKIN OUTx 1 1 1 CLK IN 1 1 0 2xCLK IN 1 0 1 3xCLK IN 1 0 0 4xCLK IN 133MHz 0 1 1 CLK IN/2 33MHz 0 1 0 CLK IN 0 0 1 1.5xCLK IN 0 0 0 2xCLK IN 33MHz 33MHz 66MHz 66MHz 100MHz 66MHz 100MHz 133MHz 1 PS8593 01/22/02 PI6C2410 PCI-X Clock Buffers 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Description Pin Type Qty Symbol De s cription 21,20,17,16 O 4 OUT[0:3] Clock outputs. To achieve zero input to output delay, all outputs must have the same loading. 11- 14 I 4 OE[0:3] Active high Output Enable, pulled up. When OE is low, OUT [0:3] outputs are disabled at low state. 9 O 1 FBOUT Feedback output. To achieve zero input to output delay, FBOUT must have the same loading as OUT[0:3]. 8 I 1 FBIN Feedback input. 7pF must be added to the output driving this pin (FBOUT) in addition to the other load. 24 I 1 CLKIN 3 I 1 HF# 4,5 I 2 DIV[0,1] 2,10,15,22 P 4 VCC 3.3V power 6,7,18,19 P 4 GND Ground 23 P 1 AVCC 3.3V analog power 1 P 1 AGND Analog ground Input Clock. High Frequency range, pulled up. "1" = Low, "0" = High. Divider/Multiplier Select, pulled up. Absolute Maximum Ratings Supply Voltage (VCC, AVCC) ................................................ 0.5V to +7.0V Input Voltage ................................................................ 0.5V to Vcc+0.5V Industrial Operating Temperature ....................................... -40°C to +85°C Storage Temperature ........................................................ 65°C to +150°C Junction Temperature ....................................................................... 150°C Input ESD MIL-883, Method 3015, human body model ....................... 2kV Operating Condition Symbol VCC, AVCC TA De s cription M in. M ax. Units I/O Supply, Analog Core Supply 3.0 3.6 V Industrial Ambient Temperature 40 +85 °C 2 PS8593 01/22/02 PI6C2410 PCI-X Clock Buffers 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics Over Operating Conditions Symbol Parame te r Conditions M in. Typ. M ax. Vil Low Input Voltage Vih High Input Voltage Iil Low Input Current VIN = 0V 50 Iih High Input Current VIN = VCC 200 Vol Low Output Voltage VCC = 3.0V, Iol = 12mA 0.4 Voh High Output Voltage VCC = 3.0V, Ioh = 12mA Idd_33 Supply Current Cl = 15pF, FOUT = 33MHz 25 Idd_66 Supply Current Cl = 15pF, FOUT = 66MHz 35 Idd_100 Supply Current Cl = 15pF, FOUT = 100MHz 45 Idd_133 Supply Current Cl = 15pF, FOUT = 133MHz 60 0.8 2.0 2.4 tbd Co Output Capacitance 6 Ci Input Capacitance 5 Cl Load Capacitance 15 Pin Inductance 7 Lpin Units V uA V mA pF nH Switching Characteristics (TA = 25°C, VCC = 3.3V ±0.3V, Cl = 15pF, FOUT = 66.67 MHz) Symbol Parame te r Te s t Conditions M in. Typ. M ax. Low Freq., HF# = "1" 10 33 40 High Freq., HF# = "0" 40 66 80 Fin Input frequency Tpd Propagation delay CLKIN to FBIN rising edges @VDD/2 Tsk Output skew @1.4V, rising edges 200 Tskpp Pkg to pkg skew @VDD/2, rising edges, same CLKIN 400 Tjc Cycle jitter Tdc Duty cycle @1.4V Tr/Tf Rise/Fall time 0.8V~2.0V 150 Units MHz 150 ps 200 45 50 55 % 1.5 ns Note: Tjc = Tp(n+1) Tp(n) Tdc = Th/Tp Tp(n) = Period of the nth cycle Tp = Period cycle time Tp(n+1) = Period of nth+1 cycle Th = High time @1.4V 3 PS8593 01/22/02 PI6C2410 PCI-X Clock Buffers 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 2.0V T1 2.0V 0.8V 0.8V Tr 1.4V Tf Tp Figure 1. Rise/Fall time Figure 2. Duty cycle 1.4V Tp(n) OUTx 1.65V Tsk OUTy 1.65V 1.4V Tp(n+1) Figure 4. Cycle jitter Figure 3. Output skew Device1 OUTx 1.65V CLKIN Tpd Tskp2p Device2 OUTy 1.65V 1.65V FBIN 1.65V Figure 6. Propagation Delay Figure 5. Pkg.-to-Pkg. skew DUT OUTx 15pF Figure 7. Test load 4 PS8593 01/22/02 PI6C2410 PCI-X Clock Buffers 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Packaging Mechanical: 24-pin QSOP (Q) 24 .008 0.20 MIN. .150 .157 .008 .013 0.20 0.33 3.81 3.99 Guage Plane .010 0.254 Detail A 1 .337 .344 0˚-6˚ .016 .035 0.41 0.89 .041 1.04 REF 8.56 8.74 .033 0.84 .053 .069 .015 x 45˚ 0.38 1.35 1.75 Detail A .007 .010 SEATING PLANE .025 typical 0.635 0.406 1.27 .016 .050 .004 0.101 .010 0.254 .008 0.203 .012 0.305 0.178 0.254 .228 .244 5.79 6.20 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Packaging Mechanical: 24-Pin TSSOP (L) 24 .169 .177 4.3 4.5 .004 .008 1 .303 .311 7.7 7.9 .0256 BSC 0.65 0.45 0.75 .047 1.20 Max .007 .012 0.19 0.30 .002 .006 SEATING PLANE 0.09 0.20 .018 .030 .252 BSC 6.4 0.05 0.15 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS Ordering Information Orde ring Code Package Name Package Type PI6C2410Q Q24 24- pin, 150- mil QSO P PI6C2410L L24 24- pin, 4.4- mil TSSO P Ope rating Te mp Industrial Pericom Semiconductor Corporation 2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com 5 PS8593 01/22/02