ETC P3C1256-15JI

P3C1256
P3C1256
HIGH SPEED 32K x 8
3.3V STATIC CMOS RAM
FEATURES
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin 300 mil DIP and SOJ
3.3V Power Supply
High Speed (Equal Access and Cycle Times)
— 12/15/20/25 ns (Commercial)
— 15/20/25 ns (Industrial)
Low Power
— 360 mW Active
Single 3.3 Volts ±0.3Volts Power Supply
Easy Memory Expansion Using CE and OE
Inputs
DESCRIPTION
The P3C1256 is a 262,144-bit high-speed CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 3.3V± 0.3V tolerance power
supply.
The P3C1256 device provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pins A0 to A14. Reading is accomplished by device selection (CE and output enabling
(OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the
addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z
state when either CE or OE is HIGH or WE is LOW.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The
P3C1256 is a member of a family of PACE RAM™ products offering fast access times.
Package options for the P3C1256 include 28-pin 300 mil
DIP and SOJ packages.
FUNCTIONAL BLOCK DIAGRAM
ROW SELECT
1
28
VCC
A1
2
27
WE
A2
3
26
A14
A3
4
25
A13
A4
5
24
A12
A5
6
23
A 11
A6
7
22
•••
•• •
A
A0
•••
A
(8)
PIN CONFIGURATIONS
A7
8
21
OE
A 10
A8
9
20
CE
A9
10
19
I/08
I/01
18
I/07
I/02
11
12
17
I/06
I/03
13
16
I/05
GND
14
15
I/04
262,144-BIT
MEMORY
ARRAY
I/O1
•••
COLUMN I/O
• ••
••• •••
INPUT
DATA
CONTROL
I/O2
COLUMN
SELECT
WE
•••
CE
•••
1519B
A
(7)
A
DIP (P5), SOJ (J5)
TOP VIEW
OE
Means Quality, Service and Speed
1Q97
133
P3C1256
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Supply Voltage
Commercial (0°C to 70°C)
3.0V ≤ VCC ≤ 3.6V
Industrial (-40°C to 85°C)
3.0 ≤ VCC ≤ 3.6V
MAXIMUM RATINGS
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress
ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those
given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can
adversely affect device reliability.
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage with Respect to GND
-0.5
7.0
V
VTERM
Terminal Voltage with Respect to GND (up to 7.0V)
-0.5
VCC + 0.5
V
TA
Operating Ambient Temperature
-40
85
°C
STG
Storage Temperature
-55
125
°C
IOUT
Output Current into Low Outputs
25
mA
ILAT
Latch-up Current
>200
mA
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
Test Conditions
Min
2.4
VOH
Output High Voltage
(I/O0 - I/O7)
IOH = –4mA, VCC = 3.0V
VOL
Output Low Voltage
(I/O0 - I/O8)
IOL = 8 mA
IOL = 10 mA
VIH
Input High Voltage
VIL
Input Low Voltage
ILI
Input Leakage Current
ILO
Max
Unit
V
0.4
0.5
V
V
2.2
VCC + 0.3
V
-0.5
0.8
V
GND ≤ VIN ≤ VCC
-5
+5
µA
Output Leakage Current
GND ≤ VOUT ≤ VCC
CE = VCC
-5
+5
µA
ISB
VCC Current
TTL Standby Current
VCC = 3.6V, IOUT = 0 mA
CE = VCC
20
mA
ISB1
VCC Current
CMOS Standby Current
VCC = 3.6V, IOUT = 0 mA
CE = VCC
3
mA
134
P3C1256
CAPACITANCES
(VCC = 5.0V, TA = 25°C, f = 1.0 MHz)
Symbol
CIN
COUT
Parameter
Test Conditions
Max
Unit
Input Capacitance
VIN = 0V
10
pF
Output Capacitance
VOUT = 0V
10
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
ICC
Temperature
Test
Range
Conditions
Parameter
Dynamic Operating Current
Commercial
Industrial
*
*
-12
-15
-20
-25
110
N/A
100
115
95
110
90
105
Unit
mA
mA
*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e., CE, and WE ≤ VIL (max), OE is high. Switching inputs are 0V
and 3V.
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
-12
Min
-15
Max
Min
-25
-20
Max
Min
Max
Min
Max
Unit
tRC
Read Cycle Time
tAA
Address Access Time
12
15
20
25
ns
tAC
Chip Enable Access
Time
Output Hold from
Address Change
12
15
20
25
ns
tOH
12
15
20
ns
25
2
2
2
2
ns
2
2
2
2
ns
tLZ
Chip Enable to
Output in Low Z
tHZ
Chip Disable to
Output in High Z
7
8
9
10
ns
tOE
Output Enable Low
to Data Valid
7
9
11
12
ns
tOLZ
Output Enable Low
to Low Z
tOHZ
Output Enable High
to High Z
tPU
Chip Enable to
Power Up Time
tPD
Chip Disable to
Power Down Time
0
0
0
6
0
7
0
9
0
12
15
135
ns
0
10
0
20
ns
ns
20
ns
P3C1256
OE CONTROLLED)(1)
READ CYCLE NO. 1 (OE
tRC (5)
ADDRESS
tAA
OE
t OE
tOLZ
tOH
(4)
CE
t AC
tAC
tOHZ
(4)
tHZ
(4)
(4)
DATA OUT
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
tRC (5)
ADDRESS
tAA
tOH
PREVIOUS DATA VALID
DATA OUT
DATA VALID
CE CONTROLLED)
READ CYCLE NO. 3 (CE
tRC
CE
tLZ(8)
tHZ
tAC
DATA OUT
DATA VALID
HIGH IMPEDANCE
ICC
tPD
tPU
V CC SUPPLY I
SB
CURRENT
Notes:
1. WE is HIGH for READ cycle.
2. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with CE1 transition
LOW .
4. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
136
P3C1256
AC CHARACTERISTICS—WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
-12
Parameter
Min
-20
-15
Max
Min
Max
Min
-25
Max
Min
Max
Unit
tWC
Write Cycle Time
12
15
20
25
ns
tCW
Chip Enable Time to
End of Write
10
12
15
18
ns
tAW
Address Valid to
End of Write
Address Set-up
Time
10
12
15
18
ns
0
0
0
0
ns
tWP
Write Pulse Width
9
11
15
18
ns
tAH
Address Hold Time
0
0
0
0
ns
tDW
Data Valid to End of
Write
8
10
12
15
ns
tDH
Data Hold Time
0
0
0
0
ns
tWZ
Write Enable to
Output in High Z
tOW
Output Active from
End of Write
tAS
7
8
3
10
3
11
3
3
ns
ns
WE CONTROLLED)(6)
WRITE CYCLE NO. 1 (WE
(9)
tWC
ADDRESS
tCW
CE
tAW
tAH
tWP
WE
tAS
tDW
tDH
DATA VALID
DATA IN
(4)
tOW
tWZ
(4,7)
(7)
DATA OUT
DATA UNDEFINED
HIGH IMPEDANCE
Notes:
6. CE1 and WE must be LOW for WRITE cycle.
7. OE is LOW for this WRITE cycle to show tWZ and tOW.
8. If CE1 goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first
transitioning address.
137
P3C1256
CE CONTROLLED)(6)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE
tWC (9)
ADDRESS
tCW
tAS
CE
tAH
tAW
tWP
WE
tDW
tDH
DATA VALID
DATA IN
DATA OUT(6)
HIGH IMPEDANCE
AC TEST CONDITIONS
Input Pulse Levels
TRUTH TABLE
Mode
GND to 3.0V
CE
OE
WE
I/O
Power
Input Rise and Fall Times
3ns
Standby
H
X
X
High Z Standby
Input Timing Reference Level
1.5V
Standby
X
X
High Z
Standby
Output Timing Reference Level
1.5V
DOUT Disabled
L
H
X
H
High Z
Active
Read
L
L
H
DOUT
Active
Write
L
X
L
High Z
Active
Output Load
See Figures 1 and 2
+3.3V
R TH = 167.2 Ω
320Ω
D OUT
DOUT
350Ω
VTH = 1.72V
30pF* (5pF* for tHZ, tLZ, tOHZ,
tOLZ , tWZ and T OW)
30pF* (5pF* for tHZ, tLZ , tOHZ,
tOLZ, tWZ and tOW)
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P3C1256, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the VCC and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
capacitor is also required between VCC and ground. To avoid signal
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with DOUT to match 166Ω (Thevenin Resistance).
138
P3C1256
DATA RETENTION
Symbol
Parameter
Test Conditions
Min
Max
Unit
2.0
3.6
V
600
µA
VDR
VCC for Data Retention
CE ≥ VCC -0.2V, CE2 ≤ 0.2V
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
ICCDR(1)
Data Retention Current
VDR = 2.0V
tCDR
Chip Deselect to Data
Retention Time
See Retention Waveform
tR
Operating Recovery Time
0
ns
tRC(2)
ns
1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 ≤ 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V
2. tRC = Read Cycle Time
CE1 CONTROLLED)
LOW VCC DATA RETENTION WAVEFORM (1) (CE
Data Retention Mode
VCC
4.5V
VDR
tCDR
2.2V
CE
4.5V
tR
CE ≥ VDR -0.2V
2.2V
LOW VCC DATA RETENTION WAVEFORM (2) (CE2 CONTROLLED)
Data Retention Mode
VCC
4.5V
VDR
tCDR
CE2
VIL
2.2V
4.5V
tR
CE2 ≤ 0.2V
139
VIL
P3C1256
PACKAGE SUFFIX
Package
Suffix
P
J
TEMPERATURE RANGE SUFFIX
Temperature
Range Suffix
Description
Plastic DIP, 300 mil wide standard
Plastic SOJ, 300 mil wide standard
C
Description
Commercial Temperature Range,
0°C to +70°C.
Industrial Temperature Range,
–40˚C to +85˚C.
I
ORDERING INFORMATION
Performance Semiconductor's part numbering scheme is as follows:
P3C 1256
ss
p
t
Temperature Range
Package Code
Speed (Access/Cycle Time)
Device Number
Static RAM Prefix (3.3 Volts)
ss = Speed (access/cycle time in ns), e.g., 12, 15.
p = Package code, i.e., P, J.
t = Temperature range, i.e. C, I.
SELECTION GUIDE
The P3C1256 is available in the following temperature, speed and package options.
Temperature
Range
Package
Commercial Plastic DIP
Plastic SOJ
Industrial
Plastic DIP
Plastic SOJ
Speed
12
-12PC
-12JC
15
-15PC
-15JC
20
-20PC
-20JC
25
-25PC
-25JC
N/A
N/A
-15PI
-15JI
-20PI
-20JI
-25PI
-25JI
N/A = Not Available
140