INTEGRATED CIRCUITS P3Z22V10 3V zero power, TotalCMOS, universal PLD device Product specification Supersedes data of 1997 May 15 IC27 Data Handbook 1997 Jul 18 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device P3Z22V10 • Programmable output polarity • Synchronous preset/asynchronous reset capability • Security bit prevents unauthorized access • Electronic signature for identification • Design entry and verification using industry standard CAE tools • Reprogrammable using industry standard device programmers FEATURES • Industry’s first TotalCMOS 22V10 – both CMOS design and process technologies • Fast Zero Power (FZP) design technique provides ultra-low power and high speed – Static current of less than 45µA – Dynamic current 1/10 to 1/1000 that of competitive devices – Pin-to-pin delay of only 10ns • True Zero Power device with no turbo bits or power down schemes DESCRIPTION • Function/JEDEC map compatible with The P3Z22V10 is the first SPLD to combine high performance with low power, without the need for “turbo bits” or other power down schemes. To achieve this, Philips Semiconductors has used their FZP design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates. This results in the combination of low power and high speed that has previously been unattainable in the PLD arena. For 5V operation, Philips Semiconductors offers the P5Z22V10 that offers high speed and low power in a 5V implementation. Bipolar, UVCMOS, EECMOS 22V10s • Multiple packaging options featuring PCB-friendly flow-through pinouts (SOL and TSSOP) – 24-pin TSSOP—uses 93% less in-system space than a 28-pin PLCC – 24-pin SOL – 28-pin PLCC with standard JEDEC pin-out • Available in commercial and industrial operating ranges • Supports mixed voltage systems–5V tolerant I/Os • Advanced 0.5µ E2CMOS process • 1000 erase/program cycles guaranteed • 20 years data retention guaranteed • Varied product term distribution with up to 16 product terms per The P3Z22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an “Output Macro Cell” (OMC), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. output for complex functions ORDERING INFORMATION ORDER CODE PACKAGE PROPAGATION DELAY TEMPERATURE RANGE OPERATING RANGE DRAWING NUMBER P3Z22V10-DA 28-pin PLCC 10ns 0 to +70°C VCC = 3.3V ±10% SOT261-3 P3Z22V10-DD 24-pin SOL 10ns 0 to +70°C VCC = 3.3V ±10% SOT137-1 P3Z22V10-DDH 24-pin TSSOP 10ns 0 to +70°C VCC = 3.3V ±10% SOT355-1 P3Z22V10-BA 28-pin PLCC 15ns 0 to +70°C VCC = 3.3V ±10% SOT261-3 P3Z22V10-BD 24-pin SOL 15ns 0 to +70°C VCC = 3.3V ±10% SOT137-1 P3Z22V10-BDH 24-pin TSSOP 15ns 0 to +70°C VCC = 3.3V ±10% SOT355-1 P3Z22V10IBA 28-pin PLCC 15ns –40 to +85°C VCC = 3.3V ±10% SOT261-3 P3Z22V10IBD 24-pin SOL 15ns –40 to +85°C VCC = 3.3V ±10% SOT137-1 P3Z22V10IBDH 24-pin TSSOP 15ns –40 to +85°C VCC = 3.3V ±10% SOT355-1 1997 Jul 18 2 853–2004 18193 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device PIN CONFIGURATIONS 28-Pin PLCC NC 2 1 F8 IO/CLK 3 VCC I1 4 F9 I2 PIN DESCRIPTIONS 28 27 26 DESCRIPTION I1 – I11 Dedicated Input NC Not Connected I3 5 25 F7 I4 6 24 F6 I5 7 23 F5 NC 8 22 NC VCC Supply Voltage I6 9 21 F4 GND Ground I7 10 20 F3 I8 11 13 14 15 16 17 18 I9 I10 GND NC I11 F0 F1 19 F2 12 SP00474 24-Pin SOL and 24-Pin TSSOP IO/CLK 1 24 VCC I1 2 23 F9 I2 3 22 F8 I3 4 21 F7 I4 5 20 F6 I5 6 19 F5 I6 7 18 F4 I7 8 17 F3 I8 9 16 F2 I9 10 15 F1 I10 11 14 F0 GND 12 13 I11 AP00475 1997 Jul 18 PIN LABEL 3 F0 – F9 Macrocell Input/Output I0/CLK Dedicated Input/Clock Input P3Z22V10 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device P3Z22V10 LOGIC DIAGRAM CLK/I0 1 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 24 VCC 43 AR 0 1 DAR 9 SP Q Q 1 1 0 0 0 1 0 1 23 F9 1 1 0 0 0 1 0 1 22 F8 1 1 0 0 0 1 0 1 21 F7 1 1 0 0 0 1 0 1 20 F6 1 1 0 0 0 1 0 1 19 F5 1 1 0 0 0 1 0 1 18 F4 1 1 0 0 0 1 0 1 17 F3 1 1 0 0 0 1 0 1 16 F2 1 1 0 0 0 1 0 1 15 F1 1 1 0 0 0 1 0 1 14 F0 13 I11 0 1 10 DAR 20 I1 SP Q Q 0 1 2 21 DAR SP 33 I2 Q Q 0 1 3 34 DAR SP Q Q 48 I3 0 1 4 49 DAR SP Q Q 65 I4 0 1 5 66 DAR SP Q Q 82 I5 0 1 6 83 DAR SP Q Q 97 I6 0 1 7 98 DAR SP 110 I7 Q Q 0 1 8 111 DAR 121 I8 SP Q Q 0 1 9 122 DAR 130 SP I9 10 SP 131 I10 11 GND 12 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 NOTE: Programmable connection. 1997 Jul 18 35 36 39 40 Q Q 0 1 43 SP00059 4 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device P3Z22V10 CLK/I0 I1 – I11 1 11 PROGRAMMABLE AND ARRAY (44 × 132) 10 12 14 16 16 14 12 10 8 OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL OUTPUT MACRO CELL F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 PRESET RESET 8 SP00060A Figure 1. Functional Diagram 132 product terms: – 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16) used to form logical sums – 10 output enable terms (one for each I/O) – 1 global synchronous preset product term – 1 global asynchronous clear product term FUNCTIONAL DESCRIPTION The P3Z22V10 implements logic functions as sum-of-products expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further increase logic flexibility. At each input-line/product-term intersection there is an EEPROM memory cell which determines whether or not there is a logical connection at that intersection. Each product term is essentially a 44-input AND gate. A product term which is connected to both the True and Complement of an input signal will always be FALSE, and thus will not affect the OR function that it drives. When all the connections on a product term are opened, a Don’t Care state exists and that term will always be TRUE. ARCHITECTURE OVERVIEW The P3Z22V10 architecture is illustrated in Figure 1. Twelve dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs for creation of logic functions. At the core of the device is a programmable electrically-erasable AND array which drives a fixed-OR array. With this structure, the P3Z22V10 can implement up to 10 sum-of-products logic expressions. Associated with each of the 10 OR functions is an I/O macrocell which can be independently programmed to one of 4 different configurations. The programmable macrocells allow each I/O to create sequential or combinatorial logic functions with either Active-High or Active-Low polarity. Variable Product Term Distribution The P3Z22V10 provides 120 product terms to drive the 10 OR functions. These product terms are distributed among the outputs in groups of 8, 10, 12, 14, and 16 to form logical sums (see Logic Diagram). This distribution allows optimum use of device resources. AND/OR Logic Array The programmable AND array of the P3Z22V10 (shown in the Logic Diagram) is formed by input lines intersecting product terms. The input lines and product terms are used as follows: 44 input lines: – 24 input lines carry the True and Complement of the signals applied to the 12 input pins – 20 additional lines carry the True and Complement values of feedback or input signals from the 10 I/Os 1997 Jul 18 5 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device 1 0 1 1 Q 0 0 Q 0 1 AR D CLK SP F P3Z22V10 S1 S0 OUTPUT CONFIGURATION 0 0 Registered/Active-LOW/Macrocell feedback 0 1 Registered/Active-HIGH/Macrocell feedback 1 0 Combinatorial/Active-LOW/Pin feedback 1 1 Combinatorial/Active-HIGH/Pin feedback 0 = Unprogrammed fuse 1 = Programmed fuse S1 S0 0 1 SP00484 Figure 2. S0 = 0 S1 = 0 AR D S0 = 0 S1 = 1 F Q CLK Output Macro Cell Logic Diagram F Q SP a. Registered/Active-LOW S0 = 1 S1 = 0 AR D S0 = 1 S1 = 1 F Q CLK c. Combinatorial/Active-LOW F Q SP d. Combinatorial/Active-HIGH b. Registered/Active-HIGH Figure 3. SP00376 Output Macro Cell Configurations Programmable I/O Macrocell Output type The output macrocell provides complete control over the architecture of each output. the ability to configure each output independently permits users to tailor the configuration of the P3Z22V10 to the precise requirements of their designs. The signal from the OR array can be fed directly to the output pin (combinatorial function) or latched in the D-type flip-flop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register will be set HIGH at the next rising edge of the clock input. Satisfying the asynchronous clear term will set Q LOW, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset. Macrocell Architecture Each I/O macrocell, as shown in Figure 2, consists of a D-type flip-flop and two signal-select multiplexers. The configuration of each macrocell of the P3Z22V10 is determined by the two EEPROM bits controlling these multiplexers. These bits determine output polarity, and output type (registered or non-registered). Equivalent circuits for the macrocell configurations are illustrated in Figure 3. 1997 Jul 18 6 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device P3Z22V10 from the I/O pin. In this case, the pin can be used as a dedicated input, a dedicated output, or a bi-directional I/O. Program/Erase Cycles The P3Z22V10 is 100% testable, erases/programs in seconds, and guarantees 1000 program/erase cycles. Power-On Reset Each macrocell can be configured to implement Active-High or Active-Low logic. Programmable polarity eliminates the need for external inverters. To ease system initialization, all flip-flops will power-up to a reset condition and the Q output will be low. The actual output of the P3Z22V10 will depend on the programmed output polarity. The VCC rise must be monotonic. Output Enable Design Security The output of each I/O macrocell can be enabled or disabled under the control of its associated programmable output enable product term. When the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the I/O pin. Otherwise, the output buffer is driven into the high-impedance state. The P3Z22V10 provides a special EEPROM security bit that prevents unauthorized reading or copying of designs programmed into the device. The security bit is set by the PLD programmer, either at the conclusion of the programming cycle or as a separate step, after the device has been programmed. Once the security bit is set, it is impossible to verify (read) or program the P3Z22V10 until the entire device has first been erased with the bulk-erase function. Output Polarity Under the control of the output enable term, the I/O pin can function as a dedicated input, a dedicated output, or a bi-directional I/O. Opening every connection on the output enable term will permanently enable the output buffer and yield a dedicated output. Conversely, if every connection is intact, the enable term will always be logically FALSE and the I/O will function as a dedicated input. TotalCMOS Design Technique for Fast Zero Power Philips is the first to offer a TotalCMOS SPLD, both in process technology and design technique. Philips employs a cascade of CMOS gates to implement its Sum of Products instead of the traditional sense amp approach. This CMOS gate implementation allows Philips to offer SPLDs which are both high performance and low power, breaking the paradigm that to have low power, you must accept low performance. Refer to Figure 4 and Table 1 showing the IDD vs. Frequency of our P3Z22V10 TotalCMOS SPLD. Register Feedback Select When the I/O macrocell is configured to implement a registered function (S1 = 0) (Figures 3a or 3b), the feedback signal to the AND array is taken from the Q output. Bi-directional I/O Select When configuring an I/O macrocell to implement a combinatorial function (S1 = 1) (Figures 3c or 3d), the feedback signal is taken TYPICAL IDD (mA) 1 FREQUENCY (MHz) SP00443 Figure 4. Typical IDD vs. Frequency @ VDD = 3.3V, 25°C (10-bit counter) Table 1. Typical IDD vs. Frequency VDD = 3.3V@25°C FREQ (MHz) 1 10 20 30 40 50 60 70 80 90 100 110 120 130 Typical IDD (mA) 0.2 1.5 3.0 4.5 6.0 7.4 8.9 10.4 11.8 13.2 14.5 15.8 17.0 18.2 1997 Jul 18 7 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device P3Z22V10 ABSOLUTE MAXIMUM RATINGS1 LIMITS SYMBOL PARAMETER VDD UNIT Supply voltage VI Input voltage MIN. MAX. –0.5 4.6 V –0.5 5.52 V V VOUT Output voltage –0.5 5.52 IIN Input current –30 30 mA IOUT Output current –100 100 mA TR Allowable thermal rise ambient to junction 0 75 °C TJ Junction temperature range –40 150 °C TSTG Storage temperature range –65 150 °C NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. 2. Except F7, where max = VDD + 0.5V. OPERATING RANGE PRODUCT GRADE Commercial Industrial 1997 Jul 18 TEMPERATURE VOLTAGE 0 to +70°C 3.3 ± 10% V –40 to +85°C 3.3 ± 10% V 8 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device P3Z22V10 DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES Commercial: 0°C ≤ Tamb ≤ +70°C; 3.0 ≤ VDD ≤ 3.6V SYMBOL PARAMETER TEST CONDITIONS VIL VIH VI VOL VOH Input voltage low Input voltage high Input clamp voltage Output voltage low Output voltage high II Input In ut leakage current IOZ output 3-Stated out ut leakage current IDDQ Standby current IDDD 1 Dynamic current ISC Short circuit output current MIN. VDD = 3.0V VDD = 3.6V VDD = 3.0V; IIN = –18mA VDD = 3.0V; IOL = 8mA VDD = 3.0V; IOH = –4mA VIN = 0 to VDD VIN = VDD to 5.5V2 VIN = 0 to VDD VIN = VDD to 5.5V2 VDD = 3.6V; Tamb = 0°C VDD = 3.6V; Tamb = 0°C @ 1MHz VDD = 3.6V; Tamb = 0°C @ 50MHz 1 pin/time for no longer than 1 second Tamb = 25°C; f = 1MHz Tamb = 25°C; f = 1MHz Tamb = 25°C; f = 1MHz LIMITS TYP. MAX. 0.8 2 –1.2 0.5 2.4 –10 –10 –10 –10 25 .5 10 –15 UNITS V V V V V µA 10 10 10 10 45 2 15 µA mA mA –100 mA µA CIN Input pin capacitance 8 pF CCLK Clock input capacitance 5 12 pF CI/O I/O pin capacitance 10 pF NOTES: 1. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where current may be affected. 2. Does not apply to F7. AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES Commercial: 0°C ≤ Tamb ≤ +70°C; 3.0 ≤ VDD ≤ 3.6V SYMBOL –B PARAMETER MIN. –D MAX. 15 MIN. MAX. 10 UNIT tPD Input or feedback to non-registered output ns tSU Setup time from input, feedback or SP to Clock 4.5 3.5 ns tCO Clock to output 10 9 ns tCF Clock to feedback1 6 4.5 ns tH Hold time 0 0 ns tAR Asynchronous Reset to registered output 17 17 ns tARW Asynchronous Reset width 5 5 ns tARR Asynchronous Reset recovery time 6 6 ns tSPR Synchronous Preset recovery time 6 6 ns tWL Width of Clock LOW 3 3 ns tWH Width of Clock HIGH 3 3 ns tR Input rise time 20 20 ns tF Input fall time 20 20 ns fMAX1 Maximum internal frequency2 (1/tSU + tCF) 95 125 MHz fMAX2 Maximum external frequency1 (1/tSU + tCO) 69 80 MHz fMAX3 Maximum clock frequency1 (1/tWL + tWH) 167 167 MHz tEA Input to Output Enable 9 9 ns tER Input to Output Disable 9 9 ns Capacitance CIN Input pin capacitance 10 10 pF COUT Output capacitance 10 10 pF NOTES: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 2. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 1997 Jul 18 9 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device P3Z22V10 DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES Industrial: –40°C ≤ Tamb ≤ +85°C; 3.0 ≤ VDD ≤ 3.6V SYMBOL PARAMETER VIL VIH VI VOL VOH Input voltage low Input voltage high Input clamp voltage Output voltage low Output voltage high II Input In ut leakage current IOZ 3-Stated out output ut leakage current IDDQ Standby current IDDD 1 Dynamic current ISC Short circuit output current TEST CONDITIONS VDD = 3.0V VDD = 3.6V VDD = 3.0V; IIN = –18mA VDD = 3.0V; IOL = 8mA VDD = 3.0V; IOH = –4mA VIN = 0 to VDD VIN = VDD to 5.5V2 VIN = 0 to VDD VIN = VDD to 5.5V2 VDD = 3.6V; Tamb = –40°C VDD = 3.6V; Tamb = –40°C @ 1MHz VDD = 3.6V; Tamb = –40°C @ 50MHz 1 pin/time for no longer than 1 second Tamb = 25°C; f = 1MHz Tamb = 25°C; f = 1MHz Tamb = 25°C; f = 1MHz MIN. LIMITS TYP. MAX. 0.8 UNITS 30 10 10 10 10 45 V V V V V µA µA µA µA µA .5 3 mA 10 20 mA –100 mA 2 –1.2 0.5 2.4 –10 –10 –10 –10 –15 CIN Input pin capacitance 8 pF CCLK Clock input capacitance 5 12 pF CI/O I/O pin capacitance 10 pF NOTES: 1. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where current may be affected. 2. Does not apply to F7. AC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES Industrial: –40°C ≤ Tamb ≤ +85°C; 3.0 ≤ VDD ≤ 3.6V SYMBOL LIMITS PARAMETER MIN. MAX. 15 UNIT tPD Input or feedback to non-registered output ns tSU Setup time from input, feedback or SP to Clock 5 ns tCO Clock to output 10.5 ns tCF Clock to feedback1 6 ns tH Hold time 0 ns tAR Asynchronous Reset to registered output 17 ns tARW Asynchronous Reset width 5 ns tARR Asynchronous Reset recovery time 6 ns tSPR Synchronous Preset recovery time 6 ns tWL Width of Clock LOW 3 ns tWH Width of Clock HIGH 3 ns tR Input rise time 20 ns tF Input fall time 20 ns fMAX1 Maximum internal frequency2 (1/tSU + tCF) 91 MHz fMAX2 Maximum external frequency1 (1/tSU + tCO) 65 MHz fMAX3 Maximum clock frequency1 (1/tWL + tWH) 167 MHz tEA Input to Output Enable 11 ns tER Input to Output Disable 11 ns Capacitance CIN Input pin capacitance 10 pF COUT Output capacitance 12 pF NOTES: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 2. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 1997 Jul 18 10 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device TEST LOAD CIRCUIT VCC C1 +3.3V S1 C2 R1 F0 I0 R2 CL DUT INPUTS Fn In OE CK GND NOTE: C1 and C2 are to bypass VCC to GND. R1 = 300Ω, R2 = 300Ω, CL = 35pF. SP00478 THEVENIN EQUIVALENT VL = 1.65V 150Ω DUT OUTPUT 35pF SP00479A VOLTAGE WAVEFORM +3.0V 90% 10% 0V tR tF 1.5ns 1.5ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses 1997 Jul 18 SP00368 11 P3Z22V10 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device P3Z22V10 SWITCHING WAVEFORMS INPUT OR FEEDBACK INPUT OR FEEDBACK VT VT tPD tS COMBINATORIAL OUTPUT tH CLOCK VT VT tCO REGISTERED OUTPUT Combinatorial Output VT Registered Output INPUT VT tWH tER CLOCK tEA VT VOH – 0.5V OUTPUT VT VOL + 0.5V tWL Clock Width Input to Output Disable/Enable tARW INPUT ASSERTING ASYNCHRONOUS RESET INPUT ASSERTING SYNCHRONOUS PRESET VT VT tAR REGISTERED OUTPUT tS CLOCK VT tSPR VT tARR CLOCK tH VT tCO REGISTERED OUTPUT VT VT Asynchronous Reset Synchronous Preset NOTES: 1. VT = 1.5V. 2. Input pulse amplitude 0V to 3.0V. 3. Input rise and fall times 2.0ns max. SP00065 “AND” ARRAY – (I, B) I, B I, B I, B I, B I, B I, B I, B I, B P, D I, B I, B I, B P, D I, B P, D P, D STATE CODE STATE CODE STATE CODE INACTIVE1 O TRUE H COMPLEMENT L STATE DON’T CARE CODE — SP00008 NOTE: 1. This is the initial state. 1997 Jul 18 12 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device PLCC28: plastic leaded chip carrer; 28 leads; pedestal 1997 Jul 18 13 P3Z22V10 SOT261-3 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device SO24: plastic small outline package; 24 leads; body width 7.5 mm 1997 Jul 18 14 P3Z22V10 SOT137-1 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm 1997 Jul 18 15 P3Z22V10 SOT355-1 Philips Semiconductors Product specification 3V zero power, TotalCMOS, universal PLD device P3Z22V10 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1997 Jul 18 16