PYRAMID P4C1023L

P4C1023/P4C1023L
LOW POWER 128K x 8
SINGLE CHIP ENABLE
CMOS STATIC RAM
FEATURES
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 400 or 600 mil Ceramic DIP
—32-Pin Ceramic SOJ
VCC Current
— Operating: 35mA
— CMOS Standby: 100µA
Access Times
—55/70 ns
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE and OE
Inputs
DESCRIPTION
The P4C1023L is a 1 Megabit low power CMOS static
RAM organized as 128K x 8. The CMOS memory requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1023L device provides asynchronous operation with matching access and cycle times. Memory
locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE low) and
output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output
pins stay in the HIGH Z state when either CE is HIGH or
WE is LOW.
The P4C1023L is packaged in a 32-pin 400 or 600 mil
ceramic DIP and in a 32-pin ceramic SOJ.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
DIP (C10, C11), CERAMIC SOJ (CJ1)
TOP VIEW
Document # SRAM126 REV OR
Revised October 2005
1
P4C1023/P4C1023L
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Supply Voltage
Commercial (0°C to 70°C)
4.5V ≤ VCC ≤ 5.5V
Industrial (-40°C to 85°C)
4.5V ≤ VCC ≤ 5.5V
Military (-55°C to 125°C)
4.5V ≤ VCC ≤ 5.5V
MAXIMUM RATINGS
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only.
Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device
reliability.
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage with Respect to GND
-0.5
7.0
V
VTERM
Terminal Voltage with Respect to GND (up to 7.0V)
-0.5
VCC + 0.5
V
TA
Operating Ambient Temperature
-55
125
°C
STG
Storage Temperature
-65
150
°C
IOUT
Output Current into Low Outputs
25
mA
ILAT
Latch-up Current
>200
mA
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
VOH
Output High Voltage
(I/O0 - I/O7)
IOH = –1mA, VCC = 4.5V
VOL
Output Low Voltage
(I/O0 - I/O7)
IOL = 2.1mA
VIH
Input High Voltage
VIL
Input Low Voltage
ILI
Input Leakage Current
Test Conditions
Min
Output Leakage Current
0.4
V
2.2
VCC + 0.3
V
-0.3
0.8
V
Comm.
Industrial
Military
-2
-5
-10
+2
+5
+10
µA
Comm.
-2
+2
µA
Industrial
-5
+5
Military
-10
+10
GND ≤ VIN ≤ VCC
CE1 ≥ VIH or CE2 ≤ VIL
ISB
VCC Current
TTL Standby Current
(TTL Input Levels)
VCC = 5.5V, IOUT = 0 mA
ISB1
VCC Current
CMOS Standby Current
(CMOS Input Levels)
VCC = 5.5V, IOUT = 0 mA
Document # SRAM126 REV OR
Unit
V
2.4
GND ≤ VOUT ≤ VCC
ILO
Max
3
mA
100
µA
CE1 = VIH or CE2 = VIL
CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V
Page 2 of 11
P4C1023/P4C1023L
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0 MHz)
Symbol
Parameter
Test Conditions
Max
Unit
CIN
Input Capacitance
VIN = 0V
7
pF
COUT
Output Capacitance
VOUT = 0V
9
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
ICC
Parameter
Dynamic Operating Current
Note 1
-55
-70
Temperature
Range
Commercial
20
20
Industrial
25
25
Military
35
35
Unit
mA
Note 1 - Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e., CE2 ≥ VIH (min), CE1 and WE ≤ VIL (max), OE is high. Switching
inputs are 0V and 3V.
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
-70
-55
Min
Max
Min
Max
Unit
tRC
Read Cycle Time
tAA
Address Access Time
55
70
ns
tAC
Chip Enable Access
Time
Output Hold from
Address Change
55
70
ns
tOH
55
ns
70
5
5
10
10
ns
tLZ
Chip Enable to
Output in Low Z
tHZ
Chip Disable to
Output in High Z
20
25
ns
tOE
Output Enable Low
to Data Valid
30
35
ns
tOLZ
Output Enable Low to
Low Z
tOHZ
Output Enable High
to High Z
tPU
Chip Enable to Power
Up Time
tPD
Chip Disable to
Power Down Time
Document # SRAM126 REV OR
5
ns
5
20
0
ns
25
0
55
ns
ns
70
ns
Page 3 of 11
P4C1023/P4C1023L
OE CONTROLLED)(1)
READ CYCLE NO. 1 (OE
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
CE CONTROLLED)
READ CYCLE NO. 3 (CE
Notes:
1. WE is HIGH for READ cycle.
2. CE and OE are LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE transition LOW.
Document # SRAM126 REV OR
4. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter
is sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the
first transitioning address.
Page 4 of 11
P4C1023/P4C1023L
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
-70
-55
Symbol
Parameter
tWC
Write Cycle Time
55
70
ns
tCW
Chip Enable Time
to End of Write
50
60
ns
tAW
Address Valid to
End of Write
50
60
ns
tAS
Address Set-up Time
0
0
ns
tWP
Write Pulse Width
40
50
ns
tAH
Address Hold Time
0
0
ns
tDW
Data Valid to End
of Write
25
30
ns
tDH
Data Hold Time
0
0
ns
tWZ
Write Enable to
Output in High Z
tOW
Output Active from
End of Write
Min
Max
Min
25
5
Max
30
5
Unit
ns
ns
WE CONTROLLED)(6)
WRITE CYCLE NO. 1 (WE
Notes:
6. CE and WE are LOW for WRITE cycle.
7. OE is LOW for this WRITE cycle to show twz and tow.
8. Write Cycle Time is measured from the last valid address to the first transitioning address.
Document # SRAM126 REV OR
Page 5 of 11
P4C1023/P4C1023L
CE CONTROLLED)(6)
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE
TRUTH TABLE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
Mode
3ns
Standby
I/O
Power
X
High Z
Standby
Active
Active
Active
CE OE WE
H
X
1.5V
1.5V
DOUT Disabled
L
H
H
High Z
Read
L
H
DOUT
See Figures 1 and 2
Write
L
L
X
L
DIN
* including scope and test fixture.
Note:
Because of the high speed of the P4C1023L, care must be taken when
testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground.
Document # SRAM126 REV OR
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω
load with 1.77V (Thevenin Voltage) at the comparator input, and a
589Ω resistor must be used in series with DOUT to match 639Ω
(Thevenin Resistance).
Page 6 of 11
P4C1023/P4C1023L
DATA RETENTION
Symbol
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to Data
Retention Time
tR
Test Conditions
Min
Max
Unit
2.0
5.5
V
VDR = 2.0V
50
µA
VDR = 3.0V
100
µA
Parameter
CE ≥ VCC -0.2V,
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
See Retention Waveform
Operating Recovery Time
0
ns
tRC
ns
1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 - 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V
LOW VCC DATA RETENTION WAVEFORM
Document # SRAM126 REV OR
Page 7 of 11
P4C1023/P4C1023L
ORDERING INFORMATION
SELECTION GUIDE
The P4C1023L is available in the following temperature, speed and package options.
Temperature
Range
Commercial
Package
Military
Temperature
Military
Processed*
55
70
Side Brazed DIP (400 mil)
-55CC
-70CC
Side Brazed DIP (600 mil)
-55CWC
-70CWC
-55CJC
-70CJC
Ceramic SOJ
Industrial
Speed (ns)
Side Brazed DIP (400 mil)
-55CI
-70CI
Side Brazed DIP (600 mil)
-55CWI
-70CWI
Ceramic SOJ
-55CJI
-70CJI
Side Brazed DIP (400 mil)
-55CM
-70CM
Side Brazed DIP (600 mil)
-55CWM
-70CWM
Ceramic SOJ
-55CJM
-70CJM
Side Brazed DIP (400 mil)
-55CMB
-70CMB
Side Brazed DIP (600 mil)
-55CWMB
-70CWMB
Ceramic SOJ
-55CJMB
-70CJMB
Document # SRAM126 REV OR
Page 8 of 11
P4C1023/P4C1023L
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
C11
SIDEBRAZED DUAL IN-LINE PACKAGE
32 (400 mil)
Min
Max
0.232
0.014
0.023
0.038
0.065
0.008
0.018
1.700
0.350
0.410
0.400 BSC
0.100 BSC
0.125
0.200
0.015
0.060
0.005
0.005
-
C10
SIDEBRAZED DUAL IN-LINE PACKAGE
32 (600 mil)
Min
Max
0.225
0.014
0.026
0.045
0.065
0.008
0.018
1.680
0.510
0.620
0.600 BSC
0.100 BSC
0.125
0.200
0.015
0.070
0.005
0.005
-
Document # SRAM126 REV OR
Page 9 of 11
P4C1023/P4C1023L
Pkg #
# Pins
Symbol
A
A1
A2
B
B1
B2
B3
D
D1
E
E1
E2
e
e1
e2
j
S
S1
CJ1
CERAMIC SOJ SMALL OUTLINE IC PACKAGE
32
Min
Max
0.120
0.165
0.088
0.120
0.070
REF
0.010
REF
0.030R
TYP
0.020
REF
0.025
0.045
0.816
0.838
0.750
REF
0.419
0.431
0.430
0.445
0.360
0.380
0.050 BSC
0.038
TYP
0.005
0.005
TYP
0.030
0.040
0.020
TYP
Document # SRAM126 REV OR
Page 10 of 11
P4C1023/P4C1023L
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM126
P4C1023 / P4C1023L LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC
RAM
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
Oct-05
JDB
Document # SRAM126 REV OR
DESCRIPTION OF CHANGE
New Data Sheet
Page 11 of 11