PCA2003 32 kHz watch circuit with programmable adaptive motor pulse and pulse period Rev. 02 — 21 July 2009 Product data sheet 1. General description The PCA2003 is a CMOS integrated circuit for battery operated wrist watches with a 32 kHz quartz crystal as timing element and a bipolar 1 Hz stepping motor. The quartz crystal oscillator and the frequency divider are optimized for minimum power consumption. A timing accuracy of 1 ppm is achieved with a programmable, digital frequency adjustment. To obtain the minimum overall power consumption for the watch, an automatic motor pulse adaptation function is provided. The circuit supplies only the minimum drive current, which is necessary to ensure a correct motor step. Changing the drive current of the motor is achieved by chopping the motor pulse with a variable duty cycle. The pulse period and the range of the variable duty cycle can be programmed to suit different types of motors. The automatic pulse adaptation scheme is based on a safe dynamic detection of successful motor steps. A pad RESET is provided (used for stopping the motor) for accurate time setting and for accelerated testing of the watch. 2. Features n Amplitude-regulated 32 kHz quartz crystal oscillator, with excellent frequency stability and high immunity to leakage currents n Electrically programmable time calibration with 1 ppm resolution stored in One Time Programmable (OTP) memory n The quartz crystal is the only external component connected n Very low supply current, typical 90 nA n One second output pulses for bipolar stepping motor n Five different programmable output periods (1 s to 30 s) n Minimum power consumption for the entire watch, due to self adaptation of the motor drive according to the required torque n Reliable step detection circuit n Motor pulse width, pulse modulation, and pulse adaptation range programmable in a wide range, stored in OTP memory n Stop function for accurate time setting and power saving during shelf life n Test mode for accelerated testing of the mechanical parts of the watch and the IC n Test bits for type recognition PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 3. Applications n Driver circuits for bipolar stepping motors n High immunity motor drive circuits 4. Ordering information Table 1. Ordering information Type number[1] Package Name Description Version PCA2003U/10AA/1 PCA200xU wire bond die; 8 bonding pads; 1.16 × 0.86 × 0.22 mm[2] PCA200xU PCA2003U/10AC/1 PCA200xU wire bond die; 8 bonding pads; 1.16 × 0.86 × 0.22 mm[2] PCA200xU [1] Version AC: enhanced oscillator performance; to be used for new designs. [2] Packing method: bare die; chip on film frame carrier. 5. Block diagram 32 Hz 8 kHz OSCIN OSCOUT 3 4 OSCILLATOR DIVIDER ÷4 RESET VSS RESET reset TIMING ADJUSTMENT, INHIBITION VDD 8 5 1 VOLTAGE DETECTOR, OTP-CONTROLLER OTP-MEMORY 1 Hz MOTOR CONTROL WITH ADAPTIVE PULSE MODULATION i.c. 2 STEP DETECTION PCA2003 6 MOT1 Fig 1. 7 MOT2 001aai168 Block diagram PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 2 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 6. Pinning information 6.1 Pinning PCA200xU VSS 1 i.c. 2 8 RESET 7 MOT2 6 MOT1 5 VDD x 0 OSCIN 3 OSCOUT 4 0 y 001aai177 Top view. For mechanical details, see Figure 13. Fig 2. Pad configuration of PCA2003 6.2 Pin description Table 2. Pin description Symbol Pin Description VSS 1 ground i.c. 2 internally connected OSCIN 3 oscillator input OSCOUT 4 oscillator output VDD 5 supply voltage MOT1 6 motor 1 output MOT2 7 motor 2 output RESET 8 reset input 7. Functional description 7.1 Motor pulse The motor output supplies pulses of different driving stages, depending on the torque required to turn on the motor. The number of different stages can be selected between three and six. With the exception of the highest driving stage, each motor pulse (tp in Figure 3 and Figure 6) is followed by a detection phase during which the motor movement is monitored, in order to check whether the motor has turned correctly or not. PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 3 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 1.96 ms tp tp detection phase 2t p mgw350 0.98 ms 31.25 ms Fig 3. 31.25 ms Correction sequence after failed motor step If a missing step is detected, a correction sequence is generated (see Figure 3) and the driving stage is switched to the next level. The correction sequence consists of two pulses: first a short pulse in the opposite direction (0.98 ms, modulated with the maximum duty cycle) to give the motor a defined position, followed by a motor pulse of the strongest driving level. Every 4 minutes, the driving level is lowered again by one stage. The motor pulse has a constant pulse width. The driving level is regulated by chopping the driving pulse with a variable duty cycle. The driving level starts from the programmed minimum value and increases by 6.25 % after each failed motor step. The strongest driving stage, which is not followed by a detection phase, is programmed separately. Therefore, it is possible to program a larger energy gap between the pulses with step detection and the strongest, not monitored, pulse. This might be necessary to ensure a reliable and stable operation under adverse conditions (magnetic fields and vibrations). If the watch works in the highest driving stage, the driving level jumps after the 4-minute period directly to the lowest stage, and not just one stage lower. To optimize the performance for different motors, the following parameters can be programmed: • • • • • Pulse width: 0.98 ms to 7.8 ms in steps of 0.98 ms Duty cycle of lowest driving level: 37.5 % to 56.25 % in steps of 6.25 % Number of driving levels (including the highest driving level): 3 to 6 Duty cycle of the highest driving level: 75 % or 100 % Enlargement pulse for the highest driving level: on or off The enlargement pulse has a duty cycle of 25 % and a pulse width which is twice the programmed motor pulse width. The repetition period for the chopping pattern is 0.98 ms. Figure 4 shows an example of a 3.9 ms pulse. PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 4 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 0.244 ms DUTY CYCLE 0.122 ms 37.5 % 43.75 % 50 % 56.25 % 62.5 % 68.75 % 75 % 81.25 % 100 % 0.98 ms Fig 4. 0.98 ms 0.98 ms 0.98 ms mgw351 Possible modulations for a 3.9 ms motor pulse 7.2 Step detection Figure 5 shows a simplified diagram of the motor driving and step detection circuit, and Figure 6 shows the step detection sequence and corresponding sampling current. Between the motor driving pulses, the switches P1 and P2 are closed, which means the motor is short-circuited. For a pulse in one direction, P1 and N2 are open, and P2 and N1 are closed with the appropriate duty cycle; for a pulse in the opposite direction, P2 and N1 are open, and P1 and N2 closed. VDD RD D1 P1 P3 P2 P4 MOTOR MOT1 N1 MOT2 N2 VSS Fig 5. mgw352 Simplified diagram of motor driving and step detection circuit PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 5 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse The step detection phase is initiated after the motor driving pulse. In phase 1 P1 and P2 are first closed for 0.98 ms and then in phase 2 all four drive switches (P1, N1, P2 and N2) are opened for 0.98 ms. As a result, the energy stored in the motor inductance is reduced as fast as possible. phase 2 phase 4 I motor phase 3 phase 1 The induced current caused by the residual motor movement is then sampled in phase 3 (closing P3 and P2) and in phase 4 (closing P1 and P4). For step detection in the opposite direction P1 and P4 are closed during phase 3 and P2 and P3 during phase 4 (see Figure 6). positive detection level t negative detection level tp 0.98 ms (motor shorted) t d = 0.98 ms sampling voltage programmable time limit OTP C4 to C6 sampling t sampling voltage negative detection positive detection sampling results t motor shorted sampling 61 µs Fig 6. 0.49 ms mgw569 Step detection sequence and corresponding sampling voltage The condition for a successful motor step is a positive step detection pulse (current in the same direction as in the driving phase) followed by a negative detection pulse within a given time limit. This time limit can be programmed between 3.9 ms and 10.7 ms (in steps of 0.98 ms) in order to ensure a safe and correct step detection under all conditions (for instance magnetic fields). The step detection phase stops after the last 31.25 ms, after the start of the motor driving pulse. PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 6 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 7.3 Time calibration The quartz crystal oscillator has an integrated capacitance of 5.2 pF, which is lower than the specified capacitance (CL) of 8.2 pF for the quartz crystal (see Table 10). Therefore, the oscillator frequency is typically 60 ppm higher than 32.768 kHz. This positive frequency offset is compensated by removing the appropriate number of 8192 Hz pulses in the divider chain (maximum 127 pulses), every 1 or 2 minutes. The time correction is given in Table 3. Table 3. Time calibration Calibration period Correction per step (n = 1) Correction per step (n = 127) ppm Seconds per day ppm Seconds per day 1 minute 2.03 0.176 258 22.3 2 minutes 1.017 0.088 129 11.15 After measuring the effective oscillator frequency, the number of correction pulses must be calculated and stored together with the calibration period in the OTP memory (see Section 7.7). The oscillator frequency can be measured at pad RESET, where a square wave signal 1 1024 with the frequency of ------------ × f osc is provided. This frequency shows a jitter every minute or every two minutes, which originates from the time calibration, depending on the programmed calibration period. Details on how to measure the oscillator frequency and the programmed inhibition time are given in Section 7.10. 7.4 Reset 1 1024 At pad RESET an output signal with a frequency of ------------ × f osc = 32 Hz is provided. Connecting pad RESET to VDD stops the motor drive and opens all four (P1, N1, P2 and N2) driver switches (see Figure 5). Connecting pad RESET to VSS activates the test mode. In this mode the motor output frequency is 32 Hz, which can be used to test the mechanical function of the watch. After releasing the pad RESET, the motor starts exactly one second later with the smallest duty cycle and with the opposite polarity to the last pulse before stopping. The debounce time for the RESET function is between 31 ms and 62 ms. 7.5 Programming possibilities The programming data is stored in OTP cells (EPROM cells). At delivery, all memory cells are in state 0. The cells can be programmed to the state 1, but then there is no more set back to state 0. The programming data is organized in an array of four 8-bit words: word A contains the time calibration, words B and C contain the setting for the monitor pulses and word D contains the type recognition (see Table 4). PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 7 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse Table 4. Word Words and bits Bit 1 2 3 4 A number of 8192 Hz pulses to be removed B lowest stage: duty cycle C pulse width D type 5 6 7 8 calibration period number of driving stages highest stage: duty cycle pulse stretching maximum time delay between positive and negative detection pulses output period output period factory test bit factory test bits Table 5. Description of word A bits Bit Value Description - adjust the number of the 8192 Hz pulses to be removed; bit 1 is the MSB and bit 7 is the LSB 0 1 minute 1 2 minutes Inhibition time 1 to 7 Calibration period 8 Table 6. Description of word B bits Bit Value Description Duty cycle lowest driving stage 1 to 2 00 37.5 % 01 43.75 % 10 50 % 11 56.25 % Number of driving stages 3 to 4 00 3 01 4 10 5 11 6[1] Duty cycle highest driving stage 5 0 75 %[2] 1 100 % Pulse stretching 6 0 no pulse stretching 1 pulse of 2 × tp and duty cycle of 25 % are added PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 8 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse Table 6. Description of word B bits …continued Bit Value Description 00 1s 01 5s 10 10 s 11 20 s Output period 7 to 8 [1] Including the highest driving stage, which one has no motor step detection. [2] If the maximum duty cycle of 75 % is selected, not all programming combinations are possible since the second highest level must be smaller than the highest driving level. Table 7. Description of word C bits Bit Value Description 000 0.98 ms 001 1.95 ms 010 2.90 ms 011 3.90 ms 100 4.90 ms 101 5.90 ms 110 6.80 ms 111 7.80 ms Pulse width tp 1 to 3 Time delay td(max) 4 to 6 [1] 000 3.91 ms 001 4.88 ms 010 5.86 ms 011 6.84 ms 100 7.81 ms 101 8.79 ms 110 9.77 ms 111 10.74 ms 0 bit 7 and 8 of word B active 1 30 s, bit 7 and 8 of word B inactive - - Output period 7 Factory test bit 8 [1] Between positive and negative detection pulses. Byte D is read to determine which type of the PCA200x family is used in a particular application. PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 9 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse Table 8. Description of word D bits Bit Value Description 0000 PCA2002 1000 PCA2000 0100 PCA2001 1100 PCA2003 - - Type recognition 1 to 4 Factory test bits 5 to 8 7.6 Programming procedure For a watch it is essential that the timing calibration can be made after the watch is fully assembled. In this situation, the supply pads are often the only terminals which are still accessible. Writing to the OTP cells and performing the related functional checks is achieved in the PCA2003 by modulating the supply voltage. The necessary control circuit consists basically of a voltage level detector, an instruction counter which determines the function to be performed, and an 8-bit shift register which allows writing to the OTP cells of an 8-bit word in one step and acts as a data pointer for checking the OTP content. There are six different instruction states (state 3 and state 5 are handled as state 4): • • • • • • State 1: measurement of the quartz crystal oscillator frequency (divided by 1024) State 2: measurement of the inhibition time State 3: write/check word A State 4: write/check word B State 5: write/check word C State 6: check word D (type recognition) Each instruction state is switched on with a pulse to VP(prog)(start). After this large pulse, an initial waiting time of t0 is required. The programming instructions are then entered by modulating the supply voltage with small pulses (amplitude VP(mod) and pulse width tmod). The first small pulse defines the start time, the following pulses perform three different functions, depending on the time delay (td) from the preceding pulse (see Figure 7, Figure 8, Figure 11 and Figure 12): • td = t1 (0.7 ms); increments the instruction counter • td = t2 (1.7 ms); clocks the shift register with data = logic 0 • td = t3 (2.7 ms); clocks the shift register with data = logic 1 The programming procedure requires a stable oscillator. This means that a waiting time, determined by the start-up time of the oscillator is necessary after power-on of the circuit. After the VP(prog)(start) pulse, the instruction counter is in state 1 and the data shift register is cleared. The instruction state ends with a second pulse to VP(prog)(stop) or with a pulse to Vstore. PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 10 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse In any case, the instruction states are terminated automatically 2 seconds after the last supply modulation pulse. 7.7 Programming the memory cells Applying the two-stage programming pulse (see Figure 7) transfers the stored data in the shift register to the OTP cells. Perform the following to program a memory word: 1. Starting with a VP(prog)(start) pulse wait for the time period t0 then set the instruction counter to the word to be written (td = t1). 2. Enter the data to be stored in the shift register (td = t2 or t3). LSB first (bit 8) and the MSB last (bit 1). 3. Applying the two-stage programming pulse Vprestore followed by Vstore stores the word. The delay between the last data bit and the prestore pulse Vprestore is td = t4. Store the word by raising the supply voltage to Vstore; the delay between the last data bit and the store pulse is td. The example shown in Figure 7 performs the following functions: • • • • Start Setting instruction counter to state 4 (word B) Entering data word 110101 into the shift register (sequence: LSB first and MSB last) Writing to the OTP cells for word B tw(prestore) VDD Vstore tp(start) VP(prog)(start) Vprestore t0 t1 t1 t1 t3 t2 t3 t2 t3 t3 t4 tw(store) VP(mod) VDD(nom) VSS mgw356 VDD(nom): nominal supply voltage. The example shows the programming of B = 110101 (the sequence is MSB first and LSB last). Fig 7. Supply voltage modulation for programming PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 11 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 7.8 Checking memory content The stored data of the OTP array can be checked bit wise by measuring the supply current. The array word is selected by the instruction state and the bit is addressed by the shift register. To read a word, the word is first selected (td = t1), and a logic 1 is written into the first cell of the shift register (td = t3). This logic 1 is then shifted through the entire shift register (td = t2), so that it points with each clock pulse to the next bit. If the addressed OTP cell contains a logic 1, a 30 kΩ resistor is connected between VDD and VSS, which increases the supply current accordingly. Figure 8 shows the supply voltage modulation for reading word B, with the corresponding supply current variation for word B = 110101 (sequence: first MSB and last LSB). VDD tp(start) tp(stop) VP(prog)(start) VP(prog)(stop) t0 t1 t1 t1 t3 t2 t2 t2 t2 t2 VP(mod) VDD(nom) VSS IDD (1) mgw357 VDD(nom): nominal supply voltage. (1) Fig 8. V DD ∆I DD = --------------30 kΩ Supply voltage modulation and corresponding supply current variation for reading word B PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 12 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 7.9 Frequency tuning of assembled watch Figure 9 shows the test set-up for frequency tuning the assembled watch. 32 kHz M PCA200x FREQUENCY COUNTER motor PROGRAMMABLE DC POWER SUPPLY battery PC INTERFACE PC mgw568 Fig 9. Frequency tuning the assembled watch 7.10 Measurement of oscillator frequency and inhibition time The output of the two measuring states can either be monitored directly at pad RESET or as a modulation of the supply voltage (a modulating resistor of 30 kΩ is connected between VDD and VSS when the signal at pad RESET is at HIGH-level). The supply voltage modulation must be followed as shown in Figure 10 in order to guarantee the correct start-up of the circuit during production and testing. VDD tp(stop) VP(prog)(stop) td(start) > 500 ms VDD(nom) VSS 001aac503 VDD(nom): nominal supply voltage. Fig 10. Supply voltage at start-up during production and testing Measuring states: PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 13 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse • State 1: quartz crystal oscillator frequency divided by 1024; state 1 starts with a pulse to VP and ends with a second pulse to VP • State 2: inhibition time has a value of n × 0.122 ms. A signal with periodicity of 31.25 ms + n × 0.122 ms appears at pad RESET and as current modulation at pad VDD (see Figure 11 and Figure 12) 31.25 ms + inhibition time VDD VO(dif) VSS mgw355 Fig 11. Output waveform at pad RESET for instruction state 2 VDD t p(stop) t p(start) VP(prog)(stop) VP(prog)(start) t0 t1 VP(mod) VDD(nom) VSS mgu719 VDD(nom): nominal supply voltage. Fig 12. Supply voltage modulation for starting and stopping of instruction state 2 7.11 Customer testing Connecting pad RESET to VSS activates the test mode. In this test mode, the motor output frequency is 8 Hz; the duty cycle reduction and battery check occurs every second, instead of every 4 minutes. PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 14 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 8. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDD supply voltage VSS = 0 V [1][2] Min Max Unit −1.8 +7.0 V VI input voltage on all supply pins −0.5 +7.5 V tsc short circuit duration time output - indefinite s Tamb ambient temperature VESD Ilu Tstg −10 +60 °C HBM [3] - ±2000 V MM [4] - ±200 V latch-up current [5] - 100 mA storage temperature [6] −30 +100 °C electrostatic discharge voltage [1] When writing to the OTP cells, the supply voltage (VDD) can be raised to a maximum of 12 V for a time period of 1 s. [2] Connecting the battery with reversed polarity does not destroy the circuit, but in this condition a large current flows, which rapidly discharges the battery. [3] Pass level; Human Body Model (HBM) according to JESD22-A114. [4] Pass level; Machine Model (MM), according to JESD22-A115. [5] Pass level; Latch-up testing, according to JESD78. [6] According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %. PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 15 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 9. Characteristics Table 10. Characteristics VDD = 1.55 V; VSS = 0 V; fosc = 32.768 kHz; Tamb = 25 °C; quartz crystal: RS = 40 kΩ, C1 = 2 fF to 3 fF, CL = 8.2 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage normal operating mode; Tamb = −10 °C to +60 °C 1.1 1.55 3.60 V ∆VDD supply voltage variation ∆V/∆t = 1 V/µs - - 0.25 V IDD supply current Supply between motor pulses - 90 120 nA between motor pulses at VDD = 3.5 V - 120 180 nA Tamb = −10 °C to +60 °C - - 200 nA stop mode; pad RESET connected to VDD - 100 135 nA - 150 200 mV - 200 300 Ω 1.1 - - V 5 10 - µS - 0.3 0.9 s - 0.05 0.20 ppm 4.3 5.2 6.3 pF 20 - - MΩ Motor output Vsat saturation voltage Rmotor = 2 kΩ; Tamb = −10 °C to +60 °C Zo(sc) output impedance (short circuit) between motor pulses; Imotor < 1 mA [1] Oscillator Vstart start voltage gm transconductance tstartup start-up time ∆f/f frequency stability CL(itg) integrated load capacitance Rpar parasitic resistance Vi(osc) ≤ 50 mV (p-p) ∆VDD = 100 mV allowed resistance between adjacent pads Pad RESET output frequency fo - 32 - Hz 1.4 - - V VO(dif) differential output voltage RL = 1 MΩ; CL = 10 pF [2] tr rise time RL = 1 MΩ; CL = 10 pF [2] - 1 - µs [2] - 1 - µs - 10 20 nA tf fall time RL = 1 MΩ; CL = 10 pF Ii(AV) average input current pad RESET connected to VDD or VSS [1] P1 + ... + P4 + N1 + N2 (see Section 7.2). [2] RL and CL are a load resistor and load capacitor, externally connected to pad RESET. PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 16 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 10. OTP programming characteristics Table 11. Specifications for OTP programming See Figure 7, Figure 8 and Figure 12. Symbol Parameter[1] Conditions Min Typ Max Unit VDD supply voltage during programming procedure 1.5 - 3.0 V VP(prog)(start) programming supply voltage (start) 6.6 - 6.8 V VP(prog)(stop) programming supply voltage (stop) 6.2 - 6.4 V VP(mod) supply voltage modulation for entering instructions 320 350 380 mV Vprestore prestore voltage for prestore pulse 6.2 - 6.4 V Vstore store voltage for writing to the OTP cells 9.9 10.0 10.1 V Istore store current for writing to the OTP cells - - 10 mA tp(start) start pulse width 8 10 12 ms tp(stop) pulse width of stop pulse 0.05 - 0.5 ms tmod modulation pulse width 25 30 40 µs tw(prestore) prestore pulse width 0.05 - 0.5 ms tw(store) store pulse width for writing to the OTP cells 95 100 110 ms t0 time 0 waiting time after start pulse 20 - 30 ms t1 time 1 pulse distance for incrementing the state counter 0.6 0.7 0.8 ms t2 time 2 pulse distance for clocking the data register with data = logic 0 1.6 1.7 1.8 ms t3 time 3 pulse distance for clocking the data register with data = logic 1 2.6 2.7 2.8 ms t4 time 4 waiting time for writing to OTP cells 0.1 0.2 0.3 ms SR slew rate for modulation of the supply voltage 0.5 - 5.0 V/µs Rmod modulation resistance supply current modulation read-out resistor 18 30 45 kΩ [1] Program each word once only. PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 17 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 11. Bare die outline Wire bond die; 8 bonding pads; 1.16 x 0.86 x 0.22 mm PCA200xU A D P1 P2 e1 e2 E P4 P3 detail X X eD DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A 0.22 0.20 0.18 OUTLINE VERSION D E 1.16 0.86 e1 e2 0.17 0.32 eD 0.96 P1 P2 P3 P4 0.099 0.089 0.099 0.089 0.096 0.086 0.096 0.086 0.093 0.083 0.093 0.083 0 JEDEC 1 mm scale REFERENCES IEC 0.5 EUROPEAN PROJECTION JEITA ISSUE DATE 08-05-09 08-05-21 PCA200xU Fig 13. Bare die outline PCA2003U Table 12. Symbol Bonding pad locations Pad x y 1 −480 +330 i.c.[3] 2 −480 +160 OSCIN 3 −480 −160 OSCOUT 4 −480 −330 VDD 5 +480 −330 VSS [2] MOT1 6 +480 −160 MOT2 7 +480 +160 RESET 8 +480 +330 [1] All coordinates are referenced, in µm, to the center of the die (see Figure 13). [2] The substrate (rear side of the chip) is connected to VSS. Therefore the die pad must be either floating or connected to VSS. [3] Pad i.c. is used for factory tests; in normal operation it should be left open-circuit, and it has an internal pull-down resistance to VSS. PCA2003_2 Product data sheet Coordinates[1] © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 18 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 12. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor HBM Human Body Model LSB Least Significant Bit MM Machine Model MSB Most Significant Bit OTP One Time Programmable 13. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA2003_2 20090721 Product data sheet - PCA2003_1 - - Modifications: PCA2003_1 • Amended new product type 20081215 Product data sheet PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 19 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA2003_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 21 July 2009 20 of 21 PCA2003 NXP Semiconductors 32 kHz watch circuit with programmable adaptive motor pulse 16. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Motor pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Step detection. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Time calibration . . . . . . . . . . . . . . . . . . . . . . . . 7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Programming possibilities. . . . . . . . . . . . . . . . . 7 Programming procedure . . . . . . . . . . . . . . . . . 10 Programming the memory cells . . . . . . . . . . . 11 Checking memory content . . . . . . . . . . . . . . . 12 Frequency tuning of assembled watch . . . . . . 13 Measurement of oscillator frequency and inhibition time . . . . . . . . . . . . . . . . . . . . . . . . . 13 Customer testing. . . . . . . . . . . . . . . . . . . . . . . 14 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 16 OTP programming characteristics . . . . . . . . . 17 Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 21 July 2009 Document identifier: PCA2003_2