TI PCA6107DW

PCA6107
REMOTE 8-BIT
AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
Low Standby Current Consumption of
1 µA Max
I2C to Parallel Port Expander
Open-Drain Active-Low Interrupt Output
Active-Low Reset Input
Operating Power-Supply Voltage Range of
2.3 V to 5.5 V
5-V Tolerant I/O Ports
400-kHz Fast I2C Bus
Three Hardware Address Pins Allow for Use
of up to Eight Devices on the I2C/SMBus
Input/Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
High-Impedance Open Drain on P0
•
•
•
•
•
Power Up With All Channels Configured as
Inputs
No Glitch On Power Up
Noise Filter on SCL/SDA Inputs
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DW PACKAGE
(TOP VIEW)
INT
SCL
SDA
A0
A1
A2
P0
P1
GND
1
18
2
17
3
16
4
15
5
14
6
13
7
12
8
11
9
10
VCC
VCC
RESET
P7
P6
P5
P4
P3
P2
DESCRIPTION/ORDERING INFORMATION
This 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. It
provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial
clock (SCL) and serial data (SDA)].
ORDERING INFORMATION
PACKAGE (1)
TA
Tube of 40
–40°C to 85°C
SOIC – DW
Reel of 2000
Reel of 250
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
PCA6107DW
PCA6107DWG4
PCA6107DWR
PCA6107
PCA6107DWRG4
PCA6107DWT
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
PCA6107
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The PCA6107 consists of one 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity
Inversion (active high) registers. At power on, the I/Os are configured as inputs. However, the system master
can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or
output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted
with the Polarity Inversion register. All registers can be read by the system master.
The system master can reset the PCA6107 in the event of a timeout or other improper operation by asserting a
low in the active-low reset (RESET) input. The power-on reset puts the registers in their default states and
initializes the I2C/SMBus state machine. Asserting RESET causes the same reset/initialization to occur without
depowering the part.
The PCA6107 open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA6107 can remain a simple slave device.
The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low
current consumption and a high-impedance open-drain output pin, P0.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address, allowing up to eight
devices to share the same I2C bus or SMBus.
TERMINAL FUNCTIONS
TERMINAL
2
DESCRIPTION
NO.
NAME
1
INT
Interrupt output. Connect to VCC through a pullup resistor.
2
SCL
Serial clock bus. Connect to VCC through a pullup resistor.
3
SDA
Serial data bus. Connect to VCC through a pullup resistor.
4
A0
Address input. Connect directly to VCC or ground.
5
A1
Address input. Connect directly to VCC or ground.
6
A2
Address input. Connect directly to VCC or ground.
7
P0
P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.
8
P1
P-port input/output. Push-pull design structure.
9
GND
10
P2
Ground
P-port input/output. Push-pull design structure.
11
P3
P-port input/output. Push-pull design structure.
12
P4
P-port input/output. Push-pull design structure.
13
P5
P-port input/output. Push-pull design structure.
14
P6
P-port input/output. Push-pull design structure.
15
P7
P-port input/output. Push-pull design structure.
16
RESET
17
VCC
Supply voltage
18
VCC
Supply voltage
Active-low reset input. Connect to VCC through a pullup resistor if no active connection is used.
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PCA6107
REMOTE 8-BIT
AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
INT
A0
A1
A2
SCL
SDA
1
Interrupt
Logic
LP Filter
4
5
6
2
3
Input
Filter
I2C Bus
Control
Shift
Register
8 Bits
I/O
Port
P7−P0
Write Pulse
VCC
RESET
GND
A.
Read Pulse
17, 18
16
Power-On
Reset
9
All I/Os are set to inputs at reset.
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PCA6107
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
SIMPLIFIED SCHEMATIC OF P0
Data From
Shift Register
Data From
Shift Register
Configuration
Register
Q
D
Output Port
Register Data
FF
Write Configuration
Pulse
Write Pulse
CK Q
D
Q
FF
P0
CK Q
Output
Port
Register
ESD Protection Diode
Input
Port
Register
D
Q
FF
Read Pulse
D
Q
FF
Write Polarity Pulse
CK Q
Polarity
Inversion
Register
4
Input Port
Register Data
CK Q
Data From
Shift Register
A.
GND
On power up or reset, all registers return to default values.
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Polarity
Register Data
PCA6107
REMOTE 8-BIT
AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
SIMPLIFIED SCHEMATIC OF P1 TO P7
Data From
Shift Register
Data From
Shift Register
Output Port
Register Data
VCC
Configuration
Register
D
Q
FF
Write Configuration
Pulse
Write Pulse
CK Q
D
Q
FF
P1 to P7
CK Q
Output
Port
Register
ESD Protection Diode
Input
Port
Register
D
Q
FF
Read Pulse
GND
Input Port
Register Data
CK Q
Data From
Shift Register
D
Q
FF
Write Polarity Pulse
Polarity
Register Data
CK Q
Polarity
Inversion
Register
A.
On power up or reset, all registers return to default values.
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device
must not be changed between the Start and the Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 2).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
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PCA6107
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Stop Condition
Start Condition
Figure 1. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
Figure 2. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Start
Condition
Clock Pulse for
Acknowledgment
Figure 3. Acknowledgment on the I2C Bus
Interface Definition
BYTE
6
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
I2C slave address
L
L
H
H
A2
A1
A0
R/W
Px I/O data bus
P7
P6
P5
P4
P3
P2
P1
P0
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PCA6107
REMOTE 8-BIT
AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
Device Address
The address of the PCA6107 is shown in Figure 4.
Slave Address
0
0
1
1 A2 A1 A0 R/W
Fixed
Programmable
Figure 4. PCA6107 Address
Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2
A1
A0
L
L
L
24 (decimal), 18 (hexadecimal)
L
L
H
25 (decimal), 19 (hexadecimal)
L
H
L
26 (decimal), 1A (hexadecimal)
L
H
H
27 (decimal), 1B (hexadecimal)
H
L
L
28 (decimal), 1C (hexadecimal)
H
L
H
29 (decimal), 1D (hexadecimal)
H
H
L
30 (decimal), 1E (hexadecimal)
H
H
H
31 (decimal), 1F (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA6107. Two bits of this data byte state the operation (read or write) and
the internal registers (input, output, polarity inversion or configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a new command byte has been sent, the register that was addressed continues to be accessed by reads
until a new command byte has been sent.
0
0
0
0
0
0
B1
B0
Figure 5. Control Register Bits
Command Byte
CONTROL REGISTER BITS
B1
B0
COMMAND BYTE
(HEX)
0
0
0x00
Input Port
Read byte
xxxx xxxx
0
1
0x01
Output Port
Read/write byte
0000 0000
1
0
0x02
Polarity Inversion
Read/write byte
1111 0000
1
1
0x03
Configuration
Read/write byte
1111 1111
REGISTER
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PROTOCOL
POWER-UP
DEFAULT
7
PCA6107
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration register. It acts only on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level. Before a read
operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port
register will be accessed next.
Register 0 (Input Port Register)
BIT
I7
I6
I5
I4
I3
I2
I1
I0
DEFAULT
X
X
X
X
X
X
X
X
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Register 1 (Output Port Register)
BIT
O7
O6
O5
O4
O3
O2
O1
O0
DEFAULT
0
0
0
0
0
0
0
0
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in
this register is cleared (written with a 0), the corresponding port pin's original polarity is retained.
Register 2 (Polarity Inversion Register)
BIT
N7
N6
N5
N4
N3
N2
N1
N0
DEFAULT
1
1
1
1
0
0
0
0
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Register 3 (Configuration Register)
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
1
1
1
1
1
1
1
1
Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA6107 in a reset condition
until VCC has reached VPOR. At that time, the reset condition is released, and the PCA6107 registers and
I2C/SMBus state machine initializes to their default states. After that, VCC must be lowered to below 0.2 V and
back up to the operating voltage for a power-reset cycle. The RESET input can be asserted to reset the system,
while keeping the VCC at its operating level.
RESET Input
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The PCA6107 registers and
I2C/SMBus state machine are held in their default states until the RESET input is again high. This input requires
a pullup resistor to VCC, if no active connection is used.
8
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PCA6107
REMOTE 8-BIT
AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the read
mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. In a
Stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock
pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the
I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the Input Port Register.
The INT output has an open-drain structure and requires pullup resistor to VCC.
Bus Transactions
Data is exchanged between the master and PCA6107 through write and read commands.
Writes
Data is transmitted to the PCA6107 by sending the device address and setting the least-significant bit to a logic
0 (see Figure 4 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one
write transmission.
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
0
0
1
Command Byte
1 A2 A1 A0 0
Start Condition
A
0
0
0
0
0
0
Data to Port
0
1
A
R/W ACK From Slave
Data 1
A
ACK From Slave
P
ACK From Slave
Write to Port
Data Out
From Port
Data 1 Valid
tpv
Figure 6. Write to Output Port Register
<br/>
SCL
1
2
3
4
5
6
7
8
9
Slave Address
SDA
S
0
0
1
Command Byte
1 A2 A1 A0 0
Start Condition
R/W
A
0
0
0
0
ACK From Slave
0
0
Data to Register
0 1/0 A
Data
ACK From Slave
A
P
ACK From Slave
Figure 7. Write to Configuration or Polarity Inversion Registers
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PCA6107
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
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SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
Reads
The bus master first must send the PCA6107 address with the least-significant bit set to a logic 0 (see Figure 4
for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the PCA6107 (see Figure 8 and Figure 9). After a
restart, the value of the register defined by the command byte matches the register being accessed when the
restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no
limitation on the number of data bytes received in one read transmission, but when the final byte is received, the
bus master must not acknowledge the data.
ACK From
Slave
Slave Address
S 0
0
1
1 A2 A1 A0 0
ACK From
Slave
Command Byte
A
A S 0
ACK From
ACK From
Master
Slave Data from Register
Slave Address
0
1
1 A2 A1 A0 1 A
At this moment, master-transmitter
becomes master-receiver, and
slave-receiver becomes
slave-transmitter
R/W
A
Data
First byte
R/W
Data from Register
NACK From
Master
NA P
Data
Last Byte
Figure 8. Read From Register
<br/>
1
SCL
2
3
4
5
6
7
8
9
Data From Port
Slave Address
S 0
SDA
0
Start
Condition
1
1 A2 A1 A0 0
R/W
Data 1
A
Data From Port
Data 4
A
ACK From
Slave
ACK From
Master
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
tph
Data 3
Data 4
Data 5
tps
INT
tiv
tir
A.
This figure assumes the command byte has been programmed previously with 00h.
B.
Transfer of data can be stopped at any moment by a Stop condition. When this occurs, data present at the last
acknowledge phase is valid (output mode). Input data is lost.
C.
This figure eliminates the command byte transfer, a restart and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 8 for these details).
Figure 9. Read Input Port Register
10
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PCA6107
REMOTE 8-BIT
AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6
V
VI
Input voltage range (2)
–0.5
6
V
range (2)
VO
Output voltage
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input/output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current, P7–P1
VO = 0 to VCC
–50
mA
ICC
–200
Continuous current through VCC
160
Package thermal impedance (3)
Tstg
Storage temperature range
(2)
(3)
6
Continuous current through GND
θJA
(1)
–0.5
UNIT
–65
V
mA
73
°C/W
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
VCC
Supply voltage
MIN
MAX
2.3
5.5
0.7 × VCC
5.5
2
5.5
SCL, SDA
–0.5
0.3 × VCC
A2–A0, P7–P0, RESET
–0.5
0.8
SCL, SDA
UNIT
V
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
P7-P1
–10
mA
IOL
Low-level output current
P7-P0
25
mA
TA
Operating free-air temperature
85
°C
A2–A0, P7–P0, RESET
–40
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V
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PCA6107
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
II = –18 mA
VPOR
Power-on reset voltage
VI = VCC or GND, IO = 0
VCC
MIN
2.3 V to 5.5 V
–1.2
VPOR
IOH = –8 mA
P-port high-level output voltage (2)
VOH
IOH = –10 mA
SDA
VOL = 0.4 V
2.3 V
1.8
3V
2.6
4.5 V
3
4.75 V
4.1
2.3 V
1.5
3V
2.5
4.5 V
3
4.75 V
4
2.3 V to 5.5 V
3
VOL = 0.5 V
IOL
P
port (3)
VOL = 0.55 V
2.3 V to 5.5 V
VOL = 0.7 V
INT
P port, except for
IOH
P0 (3)
P0 (3)
SCL, SDA
II
A2–A0, RESET
TYP (1)
MAX
1.65
2.1
UNIT
V
V
V
8
20
8
20
10
24
mA
VOL = 0.4 V
2.3 V to 5.5 V
3
VOH = VCC – 0.4 V
2.3 V to 5.5 V
–4
VOH = 4.6 V
4.6 V to 5.5 V
1
VOH = 3.3 V
3.3 V to 5.5 V
1
VI = VCC or GND
2.3 V to 5.5 V
mA
±1
±1
µA
µA
IIH
P port
VI = VCC
2.3 V to 5.5 V
1
µA
IIL
P port
VI = GND
2.3 V to 5.5 V
1
µA
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 400 kHz
Operating mode
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 100 kHz
ICC
Standby mode
∆ICC
CI
Cio
(1)
(2)
(3)
12
Additional current in Standby mode
SCL
SDA
P port
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 0 kHz
5.5 V
19
25
3.6 V
12
22
2.7 V
8
20
5.5 V
1.5
5
3.6 V
1
4
2.7 V
0.6
3
5.5 V
0.25
1
3.6 V
0.25
0.9
2.7 V
0.2
0.8
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.3 V to 5.5 V
0.2
Every LED I/O at VI = 4.3 V,
fSCL = 0 kHz
5.5 V
0.4
VI = VCC or GND
VIO = VCC or GND
µA
mA
2.3 V to 5.5 V
2.3 V to 5.5 V
4
6
5.5
8
7.5
9.5
pF
pF
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
Each I/O must be externally limited to a maximum of 25 mA, and the P port (P7–P1) must be limited to a maximum current of 100 mA.
The total current sourced by all I/Os must be limited to 85 mA per bit.
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PCA6107
REMOTE 8-BIT
AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
MIN
MAX
100
UNIT
MIN
MAX
0
400
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
0.6
µs
tscl
I2C clock low time
4.7
1.3
µs
tsp
I2C
tsds
I2C serial data setup time
tsdh
I2C serial data hold time
ticr
I2C input rise time
ticf
I2C
tocf
I2C output fall time (10-pF to 400-pF bus)
tbuf
I2C bus free time between Stop and Start
4.7
1.3
µs
tsts
I2C Start or repeater Start condition setup time
4.7
0.6
µs
tsth
I2C Start or repeater Start condition hold time
4
0.6
µs
tsps
I2C Stop condition setup time
4
0.6
µs
tvd(data)
Valid data time; SCL low to SDA output valid
1
0.9
µs
tvd(ack)
Valid data time of ACK condition; ACK signal from SCL low to
SDA (out) low
1
0.9
µs
Cb
I2C bus capacitive load
400
400
pF
(1)
spike time
50
50
250
100
0
0
input fall time
kHz
ns
ns
ns
1000
20 + 0.1Cb (1)
300
ns
300
20 + 0.1Cb
(1)
300
ns
300
20 + 0.1Cb (1)
300
ns
Cb = total capacitance of one bus line in pF
Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
STANDARD MODE
I2C BUS
MIN
tW
Reset pulse duration
tREC
Reset recovery time
tRESET
Time to reset (1)
(1)
FAST MODE
I2C BUS
MAX
MIN
16
UNIT
MAX
16
ns
0
0
ns
400
400
ns
The PCA6107 requires a minimum of 400 ns to be reset.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)
PARAMETER
FROM
TO
STANDARD MODE
I2C BUS
MIN
FAST MODE
I2C BUS
MAX
MIN
UNIT
MAX
P port
INT
4
4
µs
SCL
INT
4
4
µs
SCL
P0
250
250
SCL
P1–P7
200
200
Input data setup time
P port
SCL
0
0
ns
Input data hold time
P port
SCL
200
200
ns
tiv
Interrupt valid time
tir
Interrupt reset delay time
tpv
Output data valid
tps
tph
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ns
13
PCA6107
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
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SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
TEMPERATURE
STANDBY SUPPLY CURRENT
vs
TEMPERATURE
20
60
70
SCL = VCC
VCC = 5 V
ICC - Standby Supply Current - nA
50
f SCL = 400 kHz
I/Os unloaded
45
40
35
30
25
VCC = 3.3 V
20
15
10
VCC = 2.5 V
f SCL = 400 kHz
I/Os unloaded
60
15
ICC – Supply Current – µA
55
ICC - Supply Current - µA
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VCC = 5 V
10
VCC = 3.3 V
5
VCC = 2.5 V
50
40
30
20
10
5
0
-50
-25
0
25
50
75
0
-50
100
0
-25
25
50
75
100
2.3
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
TA = 25°C
15
10
TA = 85°C
5
30
ISINK – I/O Sink Current – mA
ISINK – I/O Sink Current – mA
20
TA = –40°C
25
TA = 25°C
20
15
10
TA = 85°C
5
0
0.3
0.4
0.5
0.6
0.1
VOL – Output Low Voltage – V
30
TA = 25°C
25
20
15
10
TA = 85°C
0.3
0.4
0.5
0.6
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VOL – Output Low Voltage – V
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
(P7–P1)
40
VCC = 5 V
VCC = 3.3 V
35
TA = –40°C
15
TA = 25°C
10
5
TA = 85°C
25
ISOURCE – I/O Source Current – mA
ISOURCE – I/O Source Current – mA
ISOURCE – I/O Source Current – mA
0.2
30
0
TA = –40°C
20
TA = 25°C
15
10
TA = 85°C
5
0.3
0.4
0.5
0.6
0.7
TA = –40°C
30
25
TA = 25°C
20
15
10
TA = 85°C
5
0
0
0.2
(VCC – VOH) – Output High Voltage – V
14
35
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
(P7–P1)
VCC = 2.5 V
0.1
5.5
TA = –40°C
40
VOL – Output Low Voltage – V
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
(P7–P1)
0.0
5.1
0
0.0
20
4.7
5
0
0.2
4.3
VCC = 5 V
45
35
TA = –40°C
3.9
50
VCC = 3.3 V
25
3.5
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
40
VCC = 2.5 V
0.1
3.1
VCC – Supply Voltage – V
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
30
0.0
2.7
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
ISINK – I/O Sink Current – mA
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
(VCC – VOH) – Output High Voltage – V
Submit Documentation Feedback
0.7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
(VCC – VOH) – Output High Voltage – V
0.7
PCA6107
REMOTE 8-BIT
AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS (continued)
OUTPUT HIGH VOLTAGE
vs
SUPPLY VOLTAGE
(P7–P1)
OUTPUT HIGH VOLTAGE
vs
TEMPERATURE
(P7–P1)
600
(V CC – V OH ) – Output High Voltage – mV
TA = 25°C
5
4
IOH = –4 mA
3
IOH = –8 mA
2
IOH = –10 mA
1
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
VCC – Supply Voltage – V
5.1
5.5
550
500
300
450
400
350
300
250
VCC = 5 V, ISOURCE = 10
200
150
VCC = 2.5 V, ISOURCE = 1 mA
100
VCC = 5 V, ISOURCE = 1 mA
50
0
-50
VCC = 2.5 V, ISINK = 10 mA
275
VCC = 2.5 V, ISOURCE = 10
VOL – Output Low Voltage – mV
6
VOH – Output High Voltage – V
OUTPUT LOW VOLTAGE
vs
TEMPERATURE
250
225
200
175
150
VCC = 5 V, ISINK = 10 mA
125
100
VCC = 2.5 V, ISINK = 1 mA
75
50
VCC = 5 V, ISINK = 1 mA
25
-25
0
25
50
75
TA – Free-Air Temperature – °C
Submit Documentation Feedback
100
0
-50
-25
0
25
50
75
100
TA – Free-Air Temperature – °C
15
PCA6107
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION
VCC
RL = 1 kΩ
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Address
Address
Condition
Bit 7
Bit 6
(S)
(MSB)
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
0.3 × VCC
ticr
tsts
tPHL
ticf
tbuf
tPLH
tsp
0.7 × VCC
SDA
0.3 × VCC
ticf
ticr
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 10. I2C Interface Load Circuit and Voltage Waveforms
16
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PCA6107
REMOTE 8-BIT
AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
VCC
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Bytes)
From Port
R/W
Slave Address
S
0
0
1
1 A2 A1 A0 1
A
1
2
3
4
A
5
6
7
8
Data 1
ACK
From Slave
Data From Port
A
Data 2
1
P
A
tir
tir
B
B
INT
A
tiv
tsps
A
Data
Into
Port
Address
Data 1
0.7 × VCC
INT
0.3 × VCC
SCL
Data 2
0.7 × VCC
R/W
tiv
A
0.3 × VCC
tir
0.7 × VCC
Pn
0.7 × VCC
1.5 V
0.3 × VCC
INT
0.3 × VCC
View A−A
View B−B
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR = 10 MHz, ZO = 50 Ω, tr/tf≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 11. Interrupt Load Circuit and Voltage Waveforms
Submit Documentation Feedback
17
PCA6107
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Pn
500 W
DUT
CL = 50 pF
(see Note A)
2 × VCC
500 W
P-PORT LOAD CONFIGURATION
SCL
0.7 × VCC
P0
A
P7
0.3 × VCC
Slave
ACK
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
SDA
Pn
tpv
(see Note B)
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
SCL
0.7 × VCC
P0
A
tps
P7
0.3 × VCC
tph
0.7 × VCC
1.5 V
0.3 × VCC
Pn
READ MODE (R/W = 1)
A.
CL includes probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 12. P-Port Load Circuit and Voltage Waveforms
18
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PCA6107
REMOTE 8-BIT
AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
VCC
RL = 1 kΩ
DUT
500 W
Pn
SDA
2 × VCC
DUT
CL = 50 pF
(see Note A)
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
SDA LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 y VCC
tRESET
RESET
VCC/2
tREC
tw
Pn
VCC/2
tRESET
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf≤ 30 ns.
C.
I/Os are configured as inputs.
D.
All parameters and waveforms are not applicable to all devices.
Figure 13. Reset Load Circuits and Voltage Waveforms
Submit Documentation Feedback
19
PCA6107
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
APPLICATION INFORMATION
Figure 14 shows an application where the PCA6107 can be used.
VCC
(5 V)
620 VCC
Master
Controller
1.8 k
1.8 k
2 k
2 k
2 k
100 k (y5)
VCC
SCL
SCL
SDA
SDA
P0
Subsystem 1
INT
P1
RESET
RESET
P2
INT
INT
RESET
P3
GND
Subsystem 2
(e.g., Counter)
PCA6107
P4
P5
A2
A
Controlled Switch
(e.g., CBT Device)
P6
ENABLE
A1
P7
A0
B
GND
ALARM
Subsystem 3
(e.g., Alarm System)
VCC
A.
Device address is configured as 0011100 for this example.
B.
P1, P4, and P5 are configured as inputs.
C.
P0, P2, and P3 are configured as outputs.
D.
P6 and P7 are not used and must be configured as outputs.
Figure 14. Typical Application
20
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PCA6107
REMOTE 8-BIT
AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
I2C
www.ti.com
SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
Minimizing ICC When I/O Is Used to Control LED
When an I/O is used to control an LED, normally it is connected to VCC through a resistor as shown in Figure 14.
The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ∆ICC parameter
in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. Designs needing to
minimize current consumption, such as battery power applications, should consider maintaining the I/O pin
greater than or equal to VCC when the LED is off.
Figure 15 shows a high-value resistor in parallel with the LED. Figure 16 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional
supply-current consumption when the LED is off.
VCC
LED
VCC
100 kW
Pn
Figure 15. High-Value Resistor in Parallel With the LED
3.3 V
VCC
5V
LED
Pn
Figure 16. Device Supplied by a Low Voltage
Submit Documentation Feedback
21
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
PCA6107DW
ACTIVE
SOIC
DW
18
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
PCA6107DWG4
ACTIVE
SOIC
DW
18
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
PCA6107DWR
ACTIVE
SOIC
DW
18
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
PCA6107DWRG4
ACTIVE
SOIC
DW
18
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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