PHILIPS PCA85232

PCA85232
LCD driver for low multiplex rates
Rev. 1 — 8 December 2010
Product data sheet
1. General description
The PCA85232 is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 160 segments. It can be
easily cascaded for larger LCD applications. The PCA85232 is compatible with most
microprocessors or microcontrollers and communicates via a two-line bidirectional
I2C-bus. Communication overheads are minimized by a display RAM with
auto-incremented addressing, by hardware subaddressing, and by display memory
switching (static and duplex drive modes).
AEC-Q100 compliant for automotive applications.
2. Features and benefits
„ Single-chip LCD controller and driver for up to 640 elements
„ Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
„ 160 segment drives:
‹ Up to eighty 7-segment numeric characters
‹ Up to forty 14-segment alphanumeric characters
‹ Any graphics of up to 640 elements
„ May be cascaded for large LCD applications (up to 5120 elements possible)
„ 160 × 4-bit RAM for display data storage
„ Software programmable frame frequency in the range of 117 Hz to 176 Hz; factory
calibrated
„ Wide LCD supply range: from 1.8 V for low threshold LCDs and up to 8.0 V for
guest-host LCDs and high threshold (automobile) twisted nematic LCDs
„ Internal LCD bias generation with voltage-follower buffers
„ Selectable display bias configuration: static, 1⁄2, or 1⁄3
„ Wide power supply range: from 1.8 V to 5.5 V
„ LCD and logic supplies may be separated
„ Low power consumption, typical: IDD = 4 μA, IDD(LCD) = 65 μA
„ 400 kHz I2C-bus interface
„ Auto-incremental display data loading across device subaddress boundaries
„ Versatile blinking modes
„ Compatible with Chip-On-Glass (COG) technology
„ No external components
„ Two sets of backplane outputs for optimal COG configurations of the application
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 15.
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
PCA85232U/2DA/Q1 bare die
Description
Delivery form
Version
197 bumps; 6.5 × 1.16 × 0.40 mm
chips with bumps in tray PCA85232U
4. Marking
Table 2.
PCA85232
Product data sheet
Marking codes
Type number
Marking code
PCA85232U/2DA/Q1
PC85132/232-1
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
5. Block diagram
S0 to S159
BP0 BP1 BP2 BP3
160
VLCD
BACKPLANE
OUTPUTS
LCD
VOLTAGE
SELECTOR
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
CONTROL
LCD BIAS
GENERATOR
VSS
PCA85232
CLK
SYNC
CLOCK SELECT
AND TIMING
BLINKER
TIMEBASE
OSC
OSCILLATOR
POWER-ON
RESET
SCL
INPUT
FILTERS
SDA
COMMAND
DECODE
WRITE DATA
CONTROL
I2C-BUS
CONTROLLER
SA0
Fig 1.
DISPLAY
RAM
DATA POINTER AND
AUTO INCREMENT
SUBADDRESS
COUNTER
SDAACK
T1
T2
T3
VDD
A0
A1
013aaa282
Block diagram of PCA85232
PCA85232
Product data sheet
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NXP Semiconductors
PCA85232
6.1 Pinning
112
61
S29
D3
S80
BP3
BP1
BP2
BP0
S79
D4
S130
166
30
BP2
BP0
S0
VLCD
VSS
A0
A1
SA0
T3
T2
OSC
T1
SYNC
VDD
CLK
SCL
SDA
60
PCA85232
Pinning diagram of PCA85232
013aaa283
LCD driver for low multiplex rates
4 of 54
© NXP B.V. 2010. All rights reserved.
Viewed from active side. For mechanical details, see Figure 32.
Fig 2.
+x
0
1
SDAACK
197
S159
BP3
BP1
0
S28
D2
PCA85232
167
Rev. 1 — 8 December 2010
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+y
D1
S131
Product data sheet
6. Pinning information
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
6.2 Pin description
Table 3.
PCA85232
Product data sheet
Pin description
Symbol
Pin
Description
SDAACK[1]
1 to 3
I2C-bus acknowledge output
SDA[1]
4 to 6
I2C-bus serial data input
SCL
7 to 9
I2C-bus serial clock input
CLK
10
clock input and output
VDD
11 to 13
supply voltage
SYNC
14
cascade synchronization input and output
OSC
15
selection of internal or external clock
T1, T2 and T3
16, 17 and 18 to 20
dedicated testing pins; to be tied to VSS in
application mode
A0 and A1
21, 22
subaddress inputs
SA0
23
I2C-bus slave address input
VSS[2]
24 to 26
ground supply voltage
VLCD
27 to 29
LCD supply voltage
BP2 and BP0
30, 31
LCD backplane outputs
S0 to S79
32 to 111
LCD segment outputs
BP0, BP2, BP1, and BP3
112 to 115
LCD backplane outputs
S80 to S159
116 to 195
LCD segment outputs
BP3 and BP1
196, 197
LCD backplane outputs
[1]
For most applications SDA and SDAACK are shorted together (see Section 12.2).
[2]
The substrate (rear side of the die) is connected to VSS and should be electrically isolated.
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
7. Functional description
The PCA85232 is a versatile peripheral device designed to interface between any
microprocessor or microcontroller to a wide variety of LCD segment or dot matrix displays
(see Figure 3). It can directly drive any static or multiplexed LCD containing up to four
backplanes and up to 160 segments.
The display configurations possible with the PCA85232 depend on the required number of
active backplane outputs. A selection of display configurations is given in Table 4.
All of the display configurations given in Table 4 can be implemented in a typical system
as shown in Figure 4.
dot matrix
7-segment with dot
14-segment with dot and accent
013aaa312
Fig 3.
Example of displays suitable for PCA85232
Table 4.
Selection of possible display configurations
Number of
Backplanes
PCA85232
Product data sheet
Icons
Digits/Characters
7-segment
14-segment
Dot matrix/
Elements
4
640
80
40
640 dots (4 × 160)
3
480
60
30
480 dots (3 × 160)
2
320
40
20
320 dots (2 × 160)
1
160
20
10
160 dots (1 × 160)
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
VDD
R≤
tr
2CB
SDAACK
VDD
VLCD
160 segment drives
SDA
HOST
MICROPROCESSOR/
MICROCONTROLLER
SCL
LCD PANEL
PCA85232
4 backplanes
OSC
A0
A1
(up to 640
elements)
SA0 VSS
013aaa284
VSS
Fig 4.
Typical system configuration
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication
channel with the PCA85232.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to VSS. The only other connections required to complete the system are the
power supplies (VDD, VSS, and VLCD) and the LCD panel selected for the application.
7.1 Power-On Reset (POR)
At power-on the PCA85232 resets to the following starting conditions:
•
•
•
•
•
•
•
•
All backplane and segment outputs are set to VLCD
The selected drive mode is 1:4 multiplex with 1⁄3 bias
Blinking is switched off
Input and output bank selectors are reset
The I2C-bus interface is initialized
The data pointer and the subaddress counter are cleared (set to logic 0)
The display is disabled
If internal oscillator is selected (pin OSC connected to VSS), then there is no clock
signal on pin CLK
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of
three impedances connected in series between VLCD and VSS. The center impedance is
bypassed by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode
configuration is selected.
PCA85232
Product data sheet
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D) are given in Table 5.
Table 5.
Biasing characteristics
LCD drive
mode
Number of:
LCD bias
Backplanes Levels configuration
V off ( RMS )
------------------------V LCD
V on ( RMS )
----------------------V LCD
static
V on ( RMS )
D = -----------------------V off ( RMS )
1
2
static
0
1
∞
1:2 multiplex 2
3
1⁄
2
0.354
0.791
2.236
1:2 multiplex 2
4
1⁄
3
0.333
0.745
2.236
4
1⁄
3
0.333
0.638
1.915
4
1⁄
3
0.333
0.577
1.732
1:3 multiplex 3
1:4 multiplex 4
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD > 3Vth.
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------- , where the values for a are
1+a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
V on ( RMS ) =
V LCD
a 2 + 2a + n
-----------------------------2
n × (1 + a)
(1)
where the values for n are
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
V off ( RMS ) =
V LCD
a 2 – 2a + n
-----------------------------2
n × (1 + a)
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
V on ( RMS )
D = ---------------------- =
V off ( RMS )
PCA85232
Product data sheet
2
(a + 1) + (n – 1)
-------------------------------------------2
(a – 1) + (n – 1)
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄
2
bias is
1⁄
2
21
bias is ---------- = 1.528 .
3
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): V LCD =
6 × V off ( RMS ) = 2.449V off ( RMS )
4 × 3)
- = 2.309V off ( RMS )
• 1:4 multiplex (1⁄2 bias): V LCD = (--------------------3
These compare with V LCD = 3V off ( RMS ) when 1⁄3 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
7.3.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependant on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vlow) and the other at 90% relative transmission (at Vhigh), see Figure 5.
For a good contrast performance, the following rules should be followed:
V on ( RMS ) ≥ V high
(4)
V off ( RMS ) ≤ V low
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vlow and Vhigh are properties of the LCD liquid and can be provided by the module
manufacturer.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
PCA85232
Product data sheet
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
100 %
Relative Transmission
90 %
10 %
Vlow
OFF
SEGMENT
Vhigh
GREY
SEGMENT
VRMS [V]
ON
SEGMENT
001aam358
Fig 5.
PCA85232
Product data sheet
Electro-optical characteristic: relative transmission curve of the liquid
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
Backplane and segment drive waveforms for this mode are shown in Figure 6.
Tfr
LCD segments
VLCD
BP0
VSS
state 1
(on)
VLCD
state 2
(off)
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
state 1
0V
−VLCD
VLCD
state 2
0V
−VLCD
(b) Resultant waveforms
at LCD segment.
013aaa207
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = VLCD.
Vstate2(t) = V(Sn+1)(t) − VBP0(t).
Voff(RMS) = 0 V.
Fig 6.
PCA85232
Product data sheet
Static drive mode waveforms
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
7.4.2 1:2 multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCA85232 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 7 and
Figure 8.
Tfr
VLCD
BP0
LCD segments
VLCD/2
VSS
state 1
VLCD
BP1
state 2
VLCD/2
VSS
VLCD
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
VLCD/2
state 1
0V
−VLCD/2
−VLCD
VLCD
VLCD/2
state 2
0V
−VLCD/2
−VLCD
(b) Resultant waveforms
at LCD segment.
013aaa208
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.354VLCD.
Fig 7.
PCA85232
Product data sheet
Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
Tfr
BP0
BP1
Sn
Sn+1
VLCD
2VLCD/3
LCD segments
VLCD/3
VSS
state 1
VLCD
2VLCD/3
state 2
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
(a) Waveforms at driver.
VLCD
2VLCD/3
VLCD/3
state 1
0V
−VLCD/3
−2VLCD/3
−VLCD
VLCD
2VLCD/3
VLCD/3
state 2
0V
−VLCD/3
−2VLCD/3
−VLCD
(b) Resultant waveforms
at LCD segment.
013aaa209
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.745VLCD.
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 8.
PCA85232
Product data sheet
Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
7.4.3 1:3 multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as
shown in Figure 9.
Tfr
BP0
BP1
BP2
Sn
Sn+1
Sn+2
VLCD
2VLCD/3
LCD segments
VLCD/3
VSS
state 1
VLCD
2VLCD/3
state 2
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
(a) Waveforms at driver.
VLCD
2VLCD/3
VLCD/3
state 1
0V
−VLCD/3
−2VLCD/3
−VLCD
VLCD
2VLCD/3
VLCD/3
state 2
0V
−VLCD/3
−2VLCD/3
−VLCD
(b) Resultant waveforms
at LCD segment.
013aaa210
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 9.
PCA85232
Product data sheet
Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
7.4.4 1:4 multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as
shown in Figure 10.
Tfr
BP0
VLCD
2VLCD/3
VLCD/3
VSS
BP1
VLCD
2VLCD/3
VLCD/3
VSS
BP2
VLCD
2VLCD/3
VLCD/3
VSS
BP3
VLCD
2VLCD/3
VLCD/3
VSS
Sn
VLCD
2VLCD/3
VLCD/3
VSS
Sn+1
VLCD
2VLCD/3
VLCD/3
VSS
Sn+2
VLCD
2VLCD/3
VLCD/3
VSS
Sn+3
VLCD
2VLCD/3
VLCD/3
VSS
state 1
VLCD
2VLCD/3
VLCD/3
0V
−VLCD/3
−2VLCD/3
−VLCD
state 2
VLCD
2VLCD/3
VLCD/3
0V
−VLCD/3
−2VLCD/3
−VLCD
LCD segments
state 1
state 2
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
013aaa211
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 10. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
PCA85232
Product data sheet
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCA85232 are timed by a frequency
fclk which either is derived from the built-in oscillator frequency fosc:
f osc
f clk = ------64
(6)
or equals an external clock frequency fclk(ext):
(7)
f clk = f clk ( ext )
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to VSS. In this case the output
from pin CLK provides the clock signal for cascaded PCA85232 in the system. However,
the clock signal is only available at pin CLK, if the display is enabled. The display is
enabled using the display enable bit (see Table 10).
The output clock frequency is like specified in Table 19 with parameter fclk.
7.5.2 External clock
Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the
external clock input.
7.6 Timing and frame frequency
The timing of the PCA85232 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs.
In cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between the PCA85232 in the system.
When the internal clock is used, the clock frequency can be programmed by software
such that the frame frequency can be chosen in the range of 117 Hz to 176 Hz (see
Table 16). The internal oscillator is calibrated within an accuracy of ±5.1 % (at
VDD = 5.0 V; Tamb = 30 °C).
The timing also generates the LCD frame frequency derived from an integer division of fclk
(see Table 16).
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
PCA85232
Product data sheet
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
7.8 Segment outputs
The LCD drive section includes 160 segment outputs (S0 to S159) which must be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data resident in the display register.
When less than 160 segment outputs are required the unused segment outputs must be
left open-circuit.
7.9 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated in accordance with the selected LCD drive mode.
• In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required the unused outputs can be left
open-circuit.
• In 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive capabilities.
• In static drive mode the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
The pins for the four backplanes BP0 to BP3 are available on both pin bars of the chip. In
applications it is possible to use either the pins for the backplanes
• on the top pin bar
• on the bottom pin bar
• or both of them to increase the driving strength of the device.
When using all backplanes available they may be connected to the respective sibling
(BP0 on the top pin bar with BP0 on the bottom pin bar and so on).
7.10 Display RAM
The display RAM is a static 160 × 4 bit RAM which stores LCD data. There is a one-to-one
correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map, Figure 11, shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 159 which correspond with the
segment outputs S0 to S159. In multiplexed LCD applications the segment data of the
first, second, third, and fourth row of the display RAM are time-multiplexed with BP0,
BP1, BP2, and BP3 respectively.
PCA85232
Product data sheet
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
columns
display RAM addresses/segment outputs (S)
0
rows
1
2
3
4
155 156 157 158 159
0
display RAM rows/
backplane outputs 1
(BP)
2
3
013aaa220
The display RAM bitmap shows the direct relationship between the display RAM addresses and
the segment outputs; and between the bits in a RAM word and the backplane outputs.
Fig 11. Display RAM bitmap
When display data is transmitted to the PCA85232 the received display bytes are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and does not wait for the acknowledge cycle as with the commands. Depending
on the current multiplex drive mode, data is stored singularly, in pairs, triples, or
quadruples. To illustrate the filling order, an example of a 7-segment numeric display
showing all drive modes is given in Figure 12; the RAM filling organization depicted
applies equally to other LCD types.
The following applies to Figure 12:
• In static drive mode the eight transmitted data bits are placed in row 0 as one byte.
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words.
• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted.
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
PCA85232
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LCD segments
Sn+2
Sn+3
static
display RAM filling order
b
f
Sn+1
BP0
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
g
e
Sn+6
Sn
Sn+7
c
DP
d
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
c
x
x
x
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
Sn
Rev. 1 — 8 December 2010
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Sn+1
a
b
f
g
multiplex
Sn+2
BP1
e
Sn+3
c
Sn+1
1:3
Sn+2
DP
d
a
b
Sn
multiplex
BP1
c
BP0
g
multiplex
BP1
c
d
g e d DP
n
n+1
n+2
n+3
a
b
x
x
f
g
x
x
e
c
x
x
d
DP
x
x
MSB
a b
LSB
f
g e c d DP
n
rows
display RAM 0 b
rows/backplane
1 DP
outputs (BP)
2 c
3 x
n+1
n+2
a
d
g
x
f
e
x
x
MSB
LSB
b DP c a d g
f
e
DP
BP2
n
rows
display RAM 0 a
rows/backplane
1 c
BP3 outputs (BP) 2 b
3 DP
n+1
f
e
g
d
MSB
a c b DP f
LSB
e g d
001aaj646
x = data bit unchanged
Fig 12. Relationships between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus
PCA85232
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Sn+1
f
LCD driver for low multiplex rates
b
f
e
c b a
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
byte4
byte5
a
Sn
1:4
BP2
DP
d
LSB
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
g
e
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
BP0
f
MSB
columns
display RAM address/segment outputs (s)
byte1
byte2
BP0
1:2
transmitted display byte
columns
display RAM address/segment outputs (s)
byte1
a
Sn+4
Sn+5
LCD backplanes
NXP Semiconductors
PCA85232
Product data sheet
drive mode
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
7.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 8). Following this command, an
arriving data byte is stored at the display RAM address indicated by the data pointer. The
filling order is shown in Figure 12.
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
•
•
•
•
In static drive mode by eight
In 1:2 multiplex drive mode by four
In 1:3 multiplex drive mode by three
In 1:4 multiplex drive mode by two
If an I2C-bus data access is terminated early then the state of the data pointer is unknown.
The data pointer should be re-written prior to further RAM accesses.
7.12 Subaddress counter
The storage of display data is conditioned by the content of the subaddress counter.
Storage is allowed only when the content of the subaddress counter matches with the
hardware subaddress applied to A0 and A1. The subaddress counter value is defined by
the device-select command (see Table 13). If the content of the subaddress counter and
the hardware subaddress do not match then data storage is inhibited but the data pointer
is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCA85232 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
The hardware subaddress must not be changed whilst the device is being accessed on
the I2C-bus interface.
7.13 Output bank selector
The output bank selector (see Table 14) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
particular LCD drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, row 2, and then row 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
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PCA85232
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LCD driver for low multiplex rates
The PCA85232 includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In the static drive mode, the bank-select command may request the contents
of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex
mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives
the provision for preparing display information in an alternative bank and to be able to
switch to it once it is assembled.
7.14 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode
or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see
Table 14). The input bank selector functions independently to the output bank selector.
7.15 Blinker
The display blinking capabilities of the PCA85232 are very versatile. The whole display
can blink at frequencies selected by the blink-select command (see Table 15). The blink
frequencies are fractions of the clock frequency. The ratios between the clock and blink
frequencies depend on the blink mode in which the device is operating (see Table 6).
Table 6.
Blink frequencies
Assuming that fclk = 3.500 kHz.
Blink mode
Operating mode ratio
Blink frequency
off
-
blinking off
1
f clk
f blink = -------768
~4.56 Hz
2
f clk
f blink = ----------1536
~2.28 Hz
3
f clk
f blink = ----------3072
~1.14 Hz
An additional feature is for an arbitrary selection of LCD elements to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command (see Table 15).
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD elements can blink selectively by changing the display RAM data at fixed time
intervals.
The entire display can blink at a frequency other than the nominal blinking frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 10).
7.16 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
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PCA85232
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LCD driver for low multiplex rates
By connecting pin SDAACK to pin SDA on the PCA85232, the SDA line becomes fully
I2C-bus compatible. In COG applications where the track resistance from the SDAACK
pin to the system SDA line can be significant, possibly a voltage divider is generated by
the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a
consequence it may be possible that the acknowledge generated by the PCA85232 can’t
be interpreted as logic 0 by the master. In COG applications where the acknowledge cycle
is required, it is therefore necessary to minimize the track resistance from the SDAACK
pin to the system SDA line to guarantee a valid LOW level.
By separating the acknowledge output from the serial data line (having the SDAACK open
circuit) design efforts to generate a valid acknowledge level can be avoided. However, in
that case the I2C-bus master has to be set up in such a way that it ignores the
acknowledge cycle.2
The following definition assumes SDA and SDAACK are connected and refers to the pair
as SDA.
7.16.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 13).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 13. Bit transfer
7.16.1.1
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP
condition (P). The START and STOP conditions are shown in Figure 14.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
mbc622
Fig 14. Definition of START and STOP conditions
2.
For further information, please consider the NXP application note: Ref. 1 “AN10170”.
PCA85232
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PCA85232
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LCD driver for low multiplex rates
7.16.2 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 15.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
mga807
Fig 15. System configuration
7.16.3 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 16.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
START
condition
clock pulse for
acknowledgement
mbc602
Fig 16. Acknowledgement on the I2C-bus
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PCA85232
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LCD driver for low multiplex rates
7.16.4 I2C-bus controller
The PCA85232 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCA85232 are
the acknowledge signals from the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data, and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0 and A1 are normally tied
to VSS which defines the hardware subaddress 0. In multiple device applications
A0 and A1 are tied to VSS or VDD in accordance with a binary coding scheme such that no
two devices with a common I2C-bus slave address have the same hardware subaddress.
7.16.5 Input filters
To enhance noise immunity in electrical adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.16.6 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the
PCA85232.The entire I2C-bus slave address byte is shown in Table 7.
Table 7.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
MSB
0
0
LSB
1
1
1
0
0
SA0
R/W
The PCA85232 is a write-only device and will not respond to a read access, therefore bit 0
should always be logic 0. Bit 1 of the slave address byte, that a PCA85232 will respond to,
is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
Having two reserved slave addresses allows the following on the same I2C-bus:
• Up to 8 PCA85232 on the same I2C-bus for very large LCD applications
• The use of two types of LCD multiplex on the same I2C-bus
The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of two possible PCA85232
slave addresses available. All PCA85232 with the corresponding SA0 level acknowledge
in parallel to the slave address, but all PCA85232 with the alternative SA0 level ignore the
whole I2C-bus transfer.
PCA85232
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PCA85232
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LCD driver for low multiplex rates
R/W = 0
slave address
control byte
RAM/command byte
S
C R
S 0 1 1 1 0 0 A 0 A
O S
0
M
A S
B
L
S P
B
EXAMPLES
a) transmit two bytes of RAM data
S
S 0 1 1 1 0 0 A 0 A 0 1
0
RAM DATA
A
RAM DATA
A
A
COMMAND
A 0 0
A
COMMAND
A P
A
COMMAND
A 0 1
A
RAM DATA
A
A P
b) transmit two command bytes
S
S 0 1 1 1 0 0 A 0 A 1 0
0
c) transmit one command byte and two RAM date bytes
S
S 0 1 1 1 0 0 A 0 A 1 0
0
RAM DATA
A P
mgl752
Fig 17. I2C-bus protocol
After acknowledgement, a control byte follows which defines if the next byte is RAM or
command information. The control byte also defines if the next byte is a control byte or
further RAM or command data.
Table 8.
Control byte description
Bit
Symbol
7
CO
6
5 to 0
Value
Description
continue bit
0
last control byte
1
control bytes continue
RS
register selection
0
command register
1
data register
-
not relevant
MSB
7
6
CO RS
5
4
3
2
1
LSB
0
not relevant
mgl753
Fig 18. Control byte format
In this way it is possible to configure the device and then fill the display RAM with little
overhead.
The command bytes and control bytes are also acknowledged by all addressed
PCA85232 connected to the bus.
The display bytes are stored in the display RAM at the address specified by the data
pointer and the subaddress counter; see Section 7.11 and Section 7.12.
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PCA85232
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LCD driver for low multiplex rates
The acknowledgement after each byte is made only by the (A0 and A1) addressed
PCA85232. After the last (display) byte, the I2C-bus master issues a STOP condition (P).
Alternatively a START may be asserted to RESTART an I2C-bus access.
7.17 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The
commands available to the PCA85232 are defined in Table 9.
Table 9.
Definition of PCA85232 commands
Command
Operation code
Bit
7
6
5
4
3
2
1
mode-set
1
1
0
0
E
B
M[1:0]
load-data-pointer-MSB
0
0
0
0
P[7:4]
Table 11
load-data-pointer-LSB
0
1
0
0
P[3:0]
Table 12
device-select
1
1
1
0
0
0
A[1:0]
bank-select
1
1
1
1
1
0
I
blink-select
1
1
1
1
0
AB
BF[1:0]
frequency-prescaler
1
1
1
0
1
F[2:0]
Table 10.
Symbol
Value
Description
7 to 4
-
1100
fixed value
3
E
Table 13
O
Table 14
Table 15
Table 16
disabled (blank)[2]
1
enabled
LCD bias configuration[3]
0[1]
1⁄
3 bias
1
1⁄
2
M[1:0]
bias
LCD drive mode selection
01
static; BP0
10
1:2 multiplex; BP0, BP1
11
1:3 multiplex; BP0, BP1, BP2
00[1]
1:4 multiplex; BP0, BP1, BP2, BP3
[1]
Power-on and reset value.
[2]
The possibility to disable the display allows implementation of blinking under external control; the enable bit
determines also whether the internal clock signal is available at the CLK pin (see Section 7.5.1).
[3]
Not applicable for static drive mode.
Table 11.
Load-data-pointer-MSB command bit description
Bit
Symbol
Value
Description
7 to 4
-
0000
fixed value
P[7:4]
0000[1]
3 to 0
1001
[1]
Product data sheet
Table 10
display status
0[1]
B
1 to 0
0
Mode-set command bit description
Bit
2
PCA85232
Reference
to
P7 to P4 defines the first 4 (most significant) bits of
the data pointer that indicates one of the 160 display
RAM addresses
Power-on and reset value.
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PCA85232
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LCD driver for low multiplex rates
Table 12.
Load-data-pointer-LSB command bit description
Bit
Symbol
Value
Description
7 to 4
-
0100
fixed value
P[3:0]
0000[1]
3 to 0
to
P3 to P0 defines the last 4 (least significant) bits of the
data pointer that indicates one of the 160 display RAM
addresses
1111
[1]
Power-on and reset value.
Table 13.
Device-select command bit description
Bit
Symbol
Value
Description
7 to 2
-
111000
fixed value
1 to 0
A[1:0]
00[1] to 11
two bits of immediate data, bits A0 to A1, are
transferred to the subaddress counter to define
one of four hardware subaddresses (see Table 20)
[1]
Power-on and reset value.
Table 14.
Bank-select command bit description
Bit
Symbol
Value
Description
Static
7 to 2
-
1
I
0
Product data sheet
fixed value
input bank selection; storage of arriving display data
0[2]
RAM bit 0
RAM bits 0 and 1
1
RAM bit 2
RAM bits 2 and 3
O
output bank selection; retrieval of LCD display data
0[2]
RAM bit 0
RAM bits 0 and 1
1
RAM bit 2
RAM bits 2 and 3
[1]
The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
[2]
Power-on and reset value.
Table 15.
Blink-select command bit description
Bit
Symbol
Value
Description
7 to 3
-
11110
fixed value
2
AB
1 to 0
PCA85232
111110
1:2 multiplex[1]
blink mode selection
0[1]
normal blinking[2]
1
alternate RAM bank blinking[3]
BF[1:0]
blink frequency selection
00[1]
off
01
1
10
2
11
3
[1]
Power-on and reset value.
[2]
Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[3]
Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
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LCD driver for low multiplex rates
Table 16.
Frame-frequency prescaler
Bit
Symbol
Value
Description
Nominal frame frequency[1] Equation
7 to 4
-
3 to 0
F[2:0]
11101
fixed value
defines the division factor for the frame frequency (ffr)
000
117 Hz
64 f clk
f fr = ------ × -------80 24
001
126 Hz
64 f clk
f fr = ------ × -------74 24
010
137 Hz
64 f clk
f fr = ------ × -------68 24
011[2]
146 Hz
f clk
f fr = ------24
100
156 Hz
64 f clk
f fr = ------ × -------60 24
101
167 Hz
64 f clk
f fr = ------ × -------56 24
110
176 Hz
64 f clk
f fr = ------ × -------53 24
111
146 Hz
f clk
f fr = ------24
[1]
Nominal frame frequency calculated for an internal operating frequency of 3.5 kHz.
[2]
Power-on and reset value.
7.18 Display controller
The display controller executes the commands identified by the command decoder. It
contains the status registers of the PCA85232 and co-ordinates their effects. The
controller is also responsible for loading display data into the display RAM as required by
the filling order.
PCA85232
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LCD driver for low multiplex rates
8. Internal circuitry
VLCD
VDD
VSS
VSS
VDD
SDAACK, SCL,
SDA, T3, VLCD
VSS
VSS
S0 to S159,
BP0 to BP3
SYNC, T1,
T2, A0, A1,
OSC, CLK,
SA0
013aaa221
Fig 19. Device protection diagram
PCA85232
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9. Limiting values
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 17. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter
Max
Unit
supply voltage
−0.5
+6.5
V
IDD
supply current
−50
+50
mA
VLCD
LCD supply voltage
−0.5
+9.0
V
IDD(LCD) LCD supply current
−50
+50
mA
−0.5
+6.5
V
−10
+10
mA
on pins S0 to S159 and
BP0 to BP3
−0.5
+9.0
V
on pins SDAACK,
CLK, SYNC
−0.5
+6.5
V
Vi
input voltage
II
input current
VO
output voltage
on pins CLK, SYNC,
SA0, OSC, SDA, SCL,
A0, A1, T1, T2, and T3
IO
output current
−10
+10
mA
ISS
ground supply current
−50
+50
mA
Ptot
total power dissipation
-
400
mW
P/out
power dissipation per output
-
100
mW
HBM
[2]
-
±4500
V
MM
[3]
-
±250
V
latch-up current
[4]
-
200
mA
Tstg
storage temperature
[5]
−65
+150
°C
Toper
operating temperature
−40
+95
°C
Ilu
Product data sheet
Min
VDD
VESD
PCA85232
Conditions
electrostatic discharge
voltage
[1]
Stresses above these values listed may cause permanent damage to the device.
[2]
Pass level; Human Body Model (HBM) according to Ref. 6 “JESD22-A114”.
[3]
Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.
[4]
Pass level; latch-up testing, according to Ref. 8 “JESD78” at maximum ambient temperature
(Tamb(max) = 95 °C).
[5]
According to the NXP store and transport requirements (see Ref. 10 “NX3-00092”) the devices have to be
stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products
deviant conditions are described in that document.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 December 2010
© NXP B.V. 2010. All rights reserved.
30 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
10. Static characteristics
Table 18. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 8.0 V; Tamb = −40 °C to +95 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
1.8
-
5.5
V
VLCD
LCD supply voltage
1.8
-
8.0
V
IDD
supply current
[1][2][3]
-
-
30
μA
[1][3]
-
-
80
μA
[1][2][4]
-
-
60
μA
[1][4]
-
-
80
μA
−0.5
-
+5.5
V
fclk(ext) = 3.500 kHz
with internal oscillator running
IDD(LCD)
LCD supply current
fclk(ext) = 3.500 kHz
with internal oscillator running
Logic
VI
input voltage
on pins SDA and SCL
all other input pins
−0.5
-
VDD + 0.5 V
VIH
HIGH-level input voltage
on pins CLK, SYNC, OSC, A0, A1,
SA0, SCL, and SDA
0.7VDD
-
-
V
VIL
LOW-level input voltage
on pins CLK, SYNC, OSC, A0, A1,
SA0, SCL, and SDA
-
-
0.3VDD
V
VO
output voltage
on pins CLK and SYNC
−0.5
-
VDD + 0.5 V
on pin SDAACK
−0.5
-
+5.5
V
0.8VDD
-
VDD
V
VOH
HIGH-level output voltage on pin SYNC, CLK
VOL
LOW-level output voltage on pin SYNC, CLK, SDAACK
VSS
-
0.2VDD
V
IOH
HIGH-level output current output source current;
VOH = 4.6 V; VDD = 5 V; on pin CLK
1.5
-
-
mA
IOL
LOW-level output current
1.5
-
-
mA
3
-
-
mA
output sink current;
on pins CLK and SYNC
VOL = 0.4 V; VDD = 5 V
on pin SDAACK
VDD ≤ 2 V; VOL = 0.2VDD
VPOR
power-on reset voltage
IL
leakage current
PCA85232
Product data sheet
2 V < VDD < 3 V; VOL = 0.4 V
3
-
-
mA
VDD ≥ 3 V; VOL = 0.4 V
6
-
-
mA
1.0
1.3
1.6
V
−1
-
+1
μA
VI = VDD or VSS; on pin OSC,
CLK, A0, A1, SA0, SDA, and SCL
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31 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
Table 18. Static characteristics …continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 8.0 V; Tamb = −40 °C to +95 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
−30
-
+30
mV
on pins BP0 to BP3
-
1.5
5
kΩ
on pins S0 to S159
-
2.0
5
kΩ
LCD outputs
ΔVO
output voltage variation
on pins BP0 to BP3 and S0 to S159
RO
output resistance
VLCD = 5 V
[5][6]
[1]
LCD outputs are open-circuit; inputs at VSS or VDD; I2C-bus inactive; VLCD = 8.0 V, VDD = 5.0 V and RAM written with all logic 1.
[2]
External clock with 50 % duty factor.
[3]
For typical values, see Figure 20
[4]
For typical values, see Figure 21
[5]
Variation between any 2 backplanes on a given voltage level; static measured.
[6]
Variation between any 2 segments on a given voltage level; static measured.
001aal525
25
IDD
(μA)
20
(1)
15
10
5
(2)
0
1
2
3
4
5
6
VDD (V)
(1) IDD internal is measured with the internal oscillator.
(2) IDD external is measured with an external clock.
Tamb = 30 °C; 1:4 multiplex; VLCD = 8 V; all RAM written with logic 1; no display connected.
Fig 20. IDD with respect to VDD
PCA85232
Product data sheet
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32 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
001aal526
70
IDD(LCD)
(μA)
50
30
10
1
3
5
7
9
VLCD (V)
Tamb = 30 °C; 1:4 multiplex; all RAM written with logic 1; no display connected; fclk = 3.5 kHz.or
fclk(ext) = 3.500 kHz.
Fig 21. IDD(LCD) with respect to VLCD
PCA85232
Product data sheet
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33 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
11. Dynamic characteristics
Table 19. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 8.0 V; Tamb = −40 °C to +95 °C; unless otherwise specified.
Symbol
Parameter
Conditions
fclk
clock frequency
fclk(ext)
external clock frequency
tclk(H)
HIGH-level clock time
tclk(L)
Δffr
on pin CLK;
VDD = 5 V ± 0.5 V
Min
[1][2][3]
[4]
Typ
Max
Unit
3050 3500 4052 Hz
700
-
5000 Hz
external clock source used
100
-
-
μs
LOW-level clock time
external clock source used
100
-
-
μs
frame frequency variation
VDD = 5 V ± 0.5 V
ffr = 146 Hz; Tamb = 30 °C
−5.1
-
+5.1
%
ffr = 135 Hz; Tamb = 95 °C
−6.2
-
+6.9
%
ffr = 157 Hz; Tamb = −40 °C
−7.8
-
+7.6
%
tPD(SYNC_N) SYNC propagation delay
tSYNC_NL
SYNC LOW time
tPD(drv)
driver propagation delay
Timing characteristics:
VLCD = 5 V
-
30
-
ns
100
-
-
μs
-
10
-
μs
I2C-bus[5]
fSCL
SCL clock frequency
-
-
400
kHz
tBUF
bus free time between a STOP and START
condition
1.3
-
-
μs
tHD;STA
hold time (repeated) START condition
0.6
-
-
μs
tSU;STA
set-up time for a repeated START condition
0.6
-
-
μs
tVD;ACK
data valid acknowledge time
-
-
0.9
μs
tLOW
LOW period of the SCL clock
1.3
-
-
μs
tHIGH
HIGH period of the SCL clock
0.6
-
-
μs
tf
fall time
of both SDA and SCL signals
-
-
0.3
μs
tr
rise time
of both SDA and SCL signals
-
-
0.3
μs
Cb
capacitive load for each bus line
-
-
400
pF
tSU;DAT
data set-up time
200
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tSU;STO
set-up time for STOP condition
0.6
-
-
μs
tSP
pulse width of spikes that must be
suppressed by the input filter
-
-
50
ns
[1]
Typical output duty factor: 50 % measured at the CLK output pin.
[2]
For the respective frame frequency ffr see Table 16.
[3]
For the characteristics of VDD at a fixed temperature or of the temperature at a fixed VDD, see Figure 22 and Figure 23.
[4]
For fCLK(ext) > 4 kHz it is recommended to use an external pull-up resistor between pin SYNC and pin VDD. The value of the resistor
should be between 100 kΩ and 1 MΩ.
[5]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
PCA85232
Product data sheet
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
001aal527
3540
fclk
(Hz)
3500
3460
3420
3380
3340
1
2
3
4
5
6
VDD (V)
Tamb = 30 °C.
Fig 22. Typical clock frequency (fclk) with respect to VDD
001aal481
170
ffr
(Hz)
7.6 %
160
150
7.8 %
max
5.1 %
typ
5.1 %
140
6.9 %
min
6.2 %
130
120
−60
−40
−20
0
20
40
60
80
100
Temperature (°C)
Condition: VDD = 5 V ± 0.5 V; frame frequency prescaler = 011; 146 Hz typical.
The frame frequency (ffr) is calculated from the clock frequency (fclk) according to the equations
described in Table 16.
Fig 23. Frame frequency variation
PCA85232
Product data sheet
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
1 / fCLK
tclk(H)
tclk(L)
0.7 VDD
CLK
0.3 VDD
0.7 VDD
SYNC
0.3 VDD
tPD(SYNC_N)
tSYNC_NL
0.5 V
BP0 to BP3,
and S0 to S159
(VDD = 5 V)
0.5 V
tPD(drv)
001aah848
Fig 24. Driver timing waveforms
tf
SDA
tr
tSU;DAT
70 %
30 %
70 %
30 %
cont.
tHD;DAT
tf
tVD;ACK
tHIGH
tr
70 %
30 %
SCL
70 %
30 %
70 %
30 %
tHD;STA
70 %
30 %
tLOW
cont.
9th clock
1 / fSCL
S
1st clock cycle
tBUF
SDA
tSU;STA
tHD;STA
tVD;ACK
tSP
tSU;STO
70 %
30 %
SCL
Sr
P
9th clock
S
013aaa110
Fig 25. I2C-bus timing waveforms when SDA and SDAACK are connected
PCA85232
Product data sheet
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36 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
12. Application information
12.1 Pull-up resistor sizing on I2C-bus
12.1.1 Max value of pull-up resistor
The bus capacitance (Cb) is the total capacitance of wire, connections, and pins. This
capacitance on pin SDA limits the maximum value of the pull-up resistor (RPU) due to the
specified rise time.
According to the I2C-bus specification the rise time (tr) is defined between the VDD related
input threshold of VIL = 0.3VDD and VIH = 0.7VDD. The value for tr(max) is 300 ns.
tr will be calculated with Equation 8:
(8)
t r = t2 – t1
whereas t1 and t2 are the time since the charging started. The values for t1 and t2 are
derivatives of the functions V(t1) and V(t2):
V ( t1 ) = 0.3V DD = V DD ( 1 – e
V ( t2 ) = 0.7V DD = V DD ( 1 – e
-t1 ⁄ R PU C b
-t2 ⁄ R PU C b
)
(9)
)
(10)
with the results of
t1 = – R PU C b × ln(0.7)
(11)
t2 = – R PU C b × ln(0.3)
(12)
t r = – R PU C b × ln(0.3) + R PU C b × ln(0.7)
(13)
RPU(max) is a function of the rise time (tr) and the bus capacitance (Cb) and will be
calculated with Equation 14:
tr
300 × 10 –9
R PU ( max ) = ----------------------- = ------------------------0.8473C b 0.8473C b
(14)
12.1.2 Min value of pull-up resistor
The supply voltage limits the minimum value of resistor RPU due to the specified minimum
sink current (see value of IOL on pin SDAACK in Table 18). RPU(min) as a function of VDD is
calculated with Equation 15:
V DD – V OL
R PU ( min ) = ------------------------I OL
(15)
The designer now has the minimum and maximum value of RPU. The values for RPU(max)
and RPU(min) are shown in Figure 26 and Figure 27.
PCA85232
Product data sheet
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37 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
001aak441
6
RPU(max)
(kΩ)
5
4
3
2
1
0
20
60
100
140
180
220
260
300
340
380
420
460
500
Cb (pF)
Fig 26. Values for RPU(max)
001aak440
6
RPU(min)
(kΩ)
5
4
3
2
1
0
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
Fig 27. Values for RPU(min)
12.2 SDA and SDAACK configuration
The Serial DAta line (SDA) and the I2C-bus acknowledge line (SDAACK) are split. Both
lines can be connected together to facilitate a single line SDA.
SDA
SDA
SDAACK
SDAACK
two wire mode
single wire mode
013aaa111
Fig 28. SDA, SDAACK configurations
PCA85232
Product data sheet
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
12.3 Cascaded operation
In large display configurations, up to 8 PCA85232 can be distinguished on the same
I2C-bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable
I2C-bus slave address (SA0).
Table 20.
Addressing cascaded PCA85232
Cluster
Bit SA0
Pin A1
Pin A0
Device
1
0
0
0
0
0
1
1
1
0
2
1
1
3
0
0
4
0
1
5
1
0
6
1
1
7
2
1
When cascaded PCA85232 are synchronized, they can share the backplane signals from
one of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCA85232 of the cascade contribute
additional segment outputs but their backplane outputs are left open-circuit (see
Figure 29).
For display sizes that are not multiple of 640 elements, a mixed cascaded system can be
considered containing only devices like PCA85232 and PCA85133. Depending on the
application, one must take care of the software commands compatibility and pin
connection compatibility.
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCA85232. This synchronization is guaranteed after the Power-On Reset (POR). The
only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by
noise in adverse electrical environments, or by the definition of a multiplex mode when
PCA85232 with different SA0 levels are cascaded). SYNC is organized as an input/output
pin; the output selection being realized as an open-drain driver with an internal pull-up
resistor. A PCA85232 asserts the SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times. Should synchronization in the cascade be
lost, it will be restored by the first PCA85232 to assert SYNC. The timing relationship
between the backplane waveforms and the SYNC signal for the various drive modes of
the PCA85232 are shown in Figure 31.
When using an external clock signal with high frequencies (fclk(ext) > 4 kHz) it is
recommended to have an external pull-up resistor between pin SYNC and pin VDD (see
Table 19). This resistor should be present even when no cascading configuration is used!
When using it in a cascaded configuration, care must be taken not to route the SYNC
signal to close to noisy signals.
The contact resistance between the SYNC pads of cascaded devices must be controlled.
If the resistance is too high, the device will not be able to synchronize properly. This is
particularly applicable to COG applications. Table 21 shows the limiting values for contact
resistance.
PCA85232
Product data sheet
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39 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
Table 21.
SYNC contact resistance
Number of devices
Maximum contact resistance
2
6000 Ω
3 to 5
2200 Ω
6 to 8
1200 Ω
In the cascaded applications, the OSC pin of the PCA85232 with subaddress 0 is
connected to VSS so that this device uses its internal clock to generate a clock signal at
the CLK pin. The other PCA85232 devices are having the OSC pin connected to VDD,
meaning that these devices are ready to receive external clock, the signal being provided
by the device with subaddress 0.
In the case that the master is providing the clock signal to the slave devices, care must be
taken that the sending of display enable or disable will be received by both, the master
and the slaves at the same time. When the display is disabled the output from pin CLK is
disabled too. The disconnection of the clock may result in a DC component for the display.
Alternatively, the schematic can be also constructed such that all the devices have OSC
pin connected to VDD and thus an external CLK being provided for the system (all devices
connected to the same external CLK).
A configuration where SYNC is connected but all PCA85232 are using the internal clock
(OSC pin tied to VSS) is not recommended and may lead to display artifacts!
PCA85232
Product data sheet
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40 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
VDD
VLCD
SDA
segment drivers
SCL
PCA85232
SYNC
LCD PANEL
(2)
CLK
OSC
backplanes
(open-circuit)
A0
A1
SA0 VSS
VLCD
VDD
R≤
HOST
MICROPROCESSOR/
MICROCONTROLLER
tr
2Cb
VDD
VLCD
SDA
segment drivers
SCL
PCA85232
SYNC
(1)
CLK
backplanes
OSC
013aaa285
A0
A1
SA0 VSS
VSS
(1) Is master (OSC connected to VSS).
(2) Is slave (OSC connected to VDD).
Fig 29. Cascaded configuration with two PCA85232 using the internal clock of the master
PCA85232
Product data sheet
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41 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
VDD
VLCD
SDA
segment drives
SCL
PCA85133
SYNC
LCD PANEL
(2)
CLK
OSC
backplanes
(open-circuit)
A0
A1
A2 SA0 VSS
VLCD
VDD
tr
2Cb
R≤
HOST
MICROPROCESSOR/
MICROCONTROLLER
VDD
VLCD
SDA
segment drives
SCL
PCA85232
SYNC
(1)
CLK
backplanes
OSC
013aaa286
A0
A1
SA0 VSS
VSS
(1) Is master (OSC connected to VSS).
(2) Is slave (OSC connected to VDD).
Fig 30. Cascaded configuration with one PCA85232 and one PCA85133 using the internal
clock of the master
PCA85232
Product data sheet
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42 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
Tfr = 1
ffr
BP0
SYNC
(a) static drive mode
BP1
(1/2 bias)
BP1
(1/3 bias)
SYNC
(b) 1:2 multiplex drive mode
BP2
(1/3 bias)
SYNC
(c) 1:3 multiplex drive mode
BP3
(1/3 bias)
SYNC
(d) 1:4 multiplex drive mode
001aaj498
Fig 31. Synchronization of the cascade for the various PCA85232 drive modes
PCA85232
Product data sheet
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PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
13. Bare die outline
Bare die; 197 bumps; 6.5 x 1.16 x 0.40 mm
PCA85232U
X
D
166
61
+y
0
C1
Marking code: PC85132/232-1
167
+x
E
S1
0
197 1
60
Y
A
b
A2
e1
e
A1
L
detail Y
detail X
0
1
scale
Dimensions
Unit
mm
2 mm
A(1)
A1(1) A2(1)
b(1)
max
0.018
nom 0.40 0.015 0.380 0.0338
min
0.012
D
E
6.5
e(1)
e1(1)
L(1)
1.16 0.054 0.2025 0.090
Note
1. Dimension not drawn to scale.
Outline
version
pca85232_do
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-02-03
PCA85232U
Fig 32. Bare die outline of PCA85232
PCA85232
Product data sheet
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© NXP B.V. 2010. All rights reserved.
44 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
Table 22. Bump locations
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 32.
PCA85232
Product data sheet
Symbol
Bump
X (μm)
Y (μm)
Symbol
Bump
X (μm)
Y (μm)
SDAACK
1
−1165.3
−481.5
S68
100
750.2
481.5
SDAACK
2
−1111.3
−481.5
S69
101
696.2
481.5
SDAACK
3
−1057.3
−481.5
S70
102
642.2
481.5
SDA
4
−854.8
−481.5
S71
103
588.2
481.5
SDA
5
−800.8
−481.5
S72
104
534.2
481.5
SDA
6
−746.8
−481.5
S73
105
480.2
481.5
SCL
7
−575.8
−481.5
S74
106
426.2
481.5
SCL
8
−521.8
−481.5
S75
107
372.2
481.5
SCL
9
−467.8
−481.5
S76
108
318.2
481.5
CLK
10
−316.2
−481.5
S77
109
264.2
481.5
VDD
11
−204.1
−481.5
S78
110
210.2
481.5
VDD
12
−150.1
−481.5
S79
111
156.2
481.5
VDD
13
−96.1
−481.5
BP0
112
86.8
481.5
SYNC
14
6.9
−481.5
BP2
113
32.8
481.5
OSC
15
119.4
−481.5
BP1
114
−21.2
481.5
T1
16
203.1
−481.5
BP3
115
−75.2
481.5
T2
17
286.8
−481.5
S80
116
−190.7
481.5
T3
18
389.9
−481.5
S81
117
−244.7
481.5
T3
19
443.9
−481.5
S82
118
−298.7
481.5
T3
20
497.9
−481.5
S83
119
−352.7
481.5
A0
21
640.5
−481.5
S84
120
−406.7
481.5
A1
22
724.2
−481.5
S85
121
−460.7
481.5
SA0
23
807.9
−481.5
S86
122
−514.7
481.5
VSS
24
893.0
−481.5
S87
123
−568.7
481.5
VSS
25
947.0
−481.5
S88
124
−622.7
481.5
VSS
26
1001.0
−481.5
S89
125
−676.7
481.5
VLCD
27
1107.2
−481.5
S90
126
−730.7
481.5
VLCD
28
1161.2
−481.5
S91
127
−784.7
481.5
VLCD
29
1215.2
−481.5
S92
128
−838.7
481.5
BP2
30
1303.4
−481.5
S93
129
−892.7
481.5
BP0
31
1357.4
−481.5
S94
130
−946.7
481.5
S0
32
1411.4
−481.5
S95
131
−1000.7
481.5
S1
33
1465.4
−481.5
S96
132
−1054.7
481.5
S2
34
1519.4
−481.5
S97
133
−1108.7
481.5
S3
35
1573.4
−481.5
S98
134
−1224.2
481.5
S4
36
1627.4
−481.5
S99
135
−1278.2
481.5
S5
37
1681.4
−481.5
S100
136
−1332.2
481.5
S6
38
1735.4
−481.5
S101
137
−1386.2
481.5
S7
39
1789.4
−481.5
S102
138
−1440.2
481.5
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 December 2010
© NXP B.V. 2010. All rights reserved.
45 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
Table 22. Bump locations …continued
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 32.
PCA85232
Product data sheet
Symbol
Bump
X (μm)
Y (μm)
Symbol
Bump
X (μm)
Y (μm)
S8
40
1843.4
−481.5
S103
139
−1494.2
481.5
S9
41
1897.4
−481.5
S104
140
−1548.2
481.5
S10
42
1951.4
−481.5
S105
141
−1602.2
481.5
S11
43
2005.4
−481.5
S106
142
−1656.2
481.5
S12
44
2059.4
−481.5
S107
143
−1710.2
481.5
S13
45
2113.4
−481.5
S108
144
−1764.2
481.5
S14
46
2167.4
−481.5
S109
145
−1818.2
481.5
S15
47
2221.4
−481.5
S110
146
−1872.2
481.5
S16
48
2363.9
−481.5
S111
147
−1926.2
481.5
S17
49
2417.9
−481.5
S112
148
−1980.2
481.5
S18
50
2471.9
−481.5
S113
149
−2034.2
481.5
S19
51
2525.9
−481.5
S114
150
−2088.2
481.5
S20
52
2579.9
−481.5
S115
151
−2142.2
481.5
S21
53
2633.9
−481.5
S116
152
−2284.7
481.5
S22
54
2687.9
−481.5
S117
153
−2338.7
481.5
S23
55
2741.9
−481.5
S118
154
−2392.7
481.5
S24
56
2795.9
−481.5
S119
155
−2446.7
481.5
S25
57
2849.9
−481.5
S120
156
−2500.7
481.5
S26
58
2903.9
−481.5
S121
157
−2554.7
481.5
S27
59
2957.9
−481.5
S122
158
−2608.7
481.5
S28
60
3011.9
−481.5
S123
159
−2662.7
481.5
S29
61
3067.7
481.5
S124
160
−2716.7
481.5
S30
62
3013.7
481.5
S125
161
−2770.7
481.5
S31
63
2959.7
481.5
S126
162
−2824.7
481.5
S32
64
2905.7
481.5
S127
163
−2878.7
481.5
S33
65
2851.7
481.5
S128
164
−2932.7
481.5
S34
66
2797.7
481.5
S129
165
−2986.7
481.5
S35
67
2743.7
481.5
S130
166
−3040.7
481.5
S36
68
2689.7
481.5
S131
167
−3025.2
−481.5
S37
69
2635.7
481.5
S132
168
−2971.2
−481.5
S38
70
2520.2
481.5
S133
169
−2917.2
−481.5
S39
71
2466.2
481.5
S134
170
−2863.2
−481.5
S40
72
2412.2
481.5
S135
171
−2809.2
−481.5
S41
73
2358.2
481.5
S136
172
−2755.2
−481.5
S42
74
2304.2
481.5
S137
173
−2701.2
−481.5
S43
75
2250.2
481.5
S138
174
−2647.2
−481.5
S44
76
2196.2
481.5
S139
175
−2593.2
−481.5
S45
77
2142.2
481.5
S140
176
−2539.2
−481.5
S46
78
2088.2
481.5
S141
177
−2485.2
−481.5
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© NXP B.V. 2010. All rights reserved.
46 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
Table 22. Bump locations …continued
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 32.
Symbol
Bump
X (μm)
Y (μm)
Symbol
Bump
X (μm)
Y (μm)
S47
79
2034.2
481.5
S142
178
−2431.2
−481.5
S48
80
1891.7
481.5
S143
179
−2377.2
−481.5
S49
81
1837.7
481.5
S144
180
−2234.7
−481.5
S50
82
1783.7
481.5
S145
181
−2180.7
−481.5
S51
83
1729.7
481.5
S146
182
−2126.7
−481.5
S52
84
1675.7
481.5
S147
183
−2072.7
−481.5
S53
85
1621.7
481.5
S148
184
−2018.7
−481.5
S54
86
1567.7
481.5
S149
185
−1964.7
−481.5
S55
87
1513.7
481.5
S150
186
−1910.7
−481.5
S56
88
1459.7
481.5
S151
187
−1856.7
−481.5
S57
89
1405.7
481.5
S152
188
−1802.7
−481.5
S58
90
1351.7
481.5
S153
189
−1748.7
−481.5
S59
91
1297.7
481.5
S154
190
−1694.7
−481.5
S60
92
1243.7
481.5
S155
191
−1640.7
−481.5
S61
93
1189.7
481.5
S156
192
−1586.7
−481.5
S62
94
1135.7
481.5
S157
193
−1532.7
−481.5
S63
95
1081.7
481.5
S158
194
−1478.7
−481.5
S64
96
1027.7
481.5
S159
195
−1424.7
−481.5
S65
97
973.7
481.5
BP3
196
−1370.7
−481.5
S66
98
858.2
481.5
BP1
197
−1316.7
−481.5
S67
99
804.2
481.5
The dummy pins are connected to the segments shown (see Table 23) but are not tested.
Table 23. Dummy bumps
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 32.
Symbol
Connected to pin
X (μm)
Y (μm)
D1
S131
−3079.2
−481.5
D2
S28
3065.9
−481.5
D3
S29
3121.7
481.5
D4
S130
−3094.7
481.5
The alignment marks are shown in Table 24.
Table 24. Alignment marking
All x/y coordinates represent the position of the REF point (see Figure 33) with respect to the center
(x/y = 0) of the chip; see Figure 32.
PCA85232
Product data sheet
Symbol
Size (μm)
X (μm)
Y (μm)
S1
121.5 × 121.5
−2733.75
−47.25
C1
121.5 × 121.5
2603.7
−47.25
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Rev. 1 — 8 December 2010
© NXP B.V. 2010. All rights reserved.
47 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
REF
S1
REF
C1
001aah849
Fig 33. Alignment marks
PCA85232
Product data sheet
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© NXP B.V. 2010. All rights reserved.
48 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
14. Packing information
Table 25.
Tray dimensions (see Figure 34)
Symbol
Description
Value
A
pocket pitch in x direction
8.8 mm
B
pocket pitch in y direction
3.6 mm
C
pocket width in x direction
6.65 mm
D
pocket width in y direction
1.31 mm
E
tray width in x direction
50.8 mm
F
tray width in y direction
50.8 mm
x
number of pockets, x direction
5
y
number of pockets, y direction
12
A
C
D
B
F
y
E
x
001aah890
Fig 34. Tray details
PCA85232
Product data sheet
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Rev. 1 — 8 December 2010
© NXP B.V. 2010. All rights reserved.
49 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
marking code
001aaj643
Fig 35. Tray alignment
15. Abbreviations
Table 26.
PCA85232
Product data sheet
Abbreviations
Acronym
Description
AEC
Automotive Electronics Council
COG
Chip-On-Glass
DC
Direct Current
HBM
Human Body Model
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
ITO
Indium Tin Oxide
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MM
Machine Model
MSB
Most Significant Bit
POR
Power-On Reset
RC
Resistance and Capacitance
RAM
Random Access Memory
RMS
Root Mean Square
SCL
Serial CLock line
SDA
Serial DAta line
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 December 2010
© NXP B.V. 2010. All rights reserved.
50 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
16. References
[1]
AN10170 — Design guidelines for COG modules with NXP monochrome LCD
drivers
[2]
AN10706 — Handling bare die
[3]
AN10853 — ESD and EMC sensitivity of IC
[4]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[5]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[6]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[7]
JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[8]
JESD78 — IC Latch-Up Test
[9]
JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[10] NX3-00092 — NXP store and transport requirements
[11] UM10204 — I2C-bus specification and user manual
17. Revision history
Table 27.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA85232 v.1
20101208
Product data sheet
-
-
PCA85232
Product data sheet
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51 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
PCA85232
Product data sheet
suitable for use in medical, military, aircraft, space or life support equipment,
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 December 2010
© NXP B.V. 2010. All rights reserved.
52 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18.4 Trademarks
I2C-bus — logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA85232
Product data sheet
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Rev. 1 — 8 December 2010
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53 of 54
PCA85232
NXP Semiconductors
LCD driver for low multiplex rates
20. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
Functional description . . . . . . . . . . . . . . . . . . . 6
7.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 7
7.2
LCD bias generator . . . . . . . . . . . . . . . . . . . . . 7
7.3
LCD voltage selector . . . . . . . . . . . . . . . . . . . . 8
7.3.1
Electro-optical performance . . . . . . . . . . . . . . . 9
7.4
LCD drive mode waveforms . . . . . . . . . . . . . . 11
7.4.1
Static drive mode . . . . . . . . . . . . . . . . . . . . . . 11
7.4.2
1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 12
7.4.3
1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 14
7.4.4
1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 15
7.5
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.5.1
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.5.2
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.6
Timing and frame frequency . . . . . . . . . . . . . . 16
7.7
Display register . . . . . . . . . . . . . . . . . . . . . . . . 16
7.8
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 17
7.9
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 17
7.10
Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.11
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.12
Subaddress counter . . . . . . . . . . . . . . . . . . . . 20
7.13
Output bank selector . . . . . . . . . . . . . . . . . . . 20
7.14
Input bank selector . . . . . . . . . . . . . . . . . . . . . 21
7.15
Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.16
Characteristics of the I2C-bus. . . . . . . . . . . . . 21
7.16.1
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.16.1.1 START and STOP conditions . . . . . . . . . . . . . 22
7.16.2
System configuration . . . . . . . . . . . . . . . . . . . 23
7.16.3
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.16.4
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 24
7.16.5
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.16.6
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 24
7.17
Command decoder . . . . . . . . . . . . . . . . . . . . . 26
7.18
Display controller . . . . . . . . . . . . . . . . . . . . . . 28
8
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 29
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 30
10
Static characteristics. . . . . . . . . . . . . . . . . . . . 31
11
Dynamic characteristics . . . . . . . . . . . . . . . . . 34
12
Application information. . . . . . . . . . . . . . . . . . 37
12.1
12.1.1
12.1.2
12.2
12.3
13
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
Pull-up resistor sizing on I2C-bus. . . . . . . . . .
Max value of pull-up resistor . . . . . . . . . . . . .
Min value of pull-up resistor . . . . . . . . . . . . . .
SDA and SDAACK configuration . . . . . . . . . .
Cascaded operation. . . . . . . . . . . . . . . . . . . .
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . .
Packing information . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
37
37
38
39
44
49
50
51
51
52
52
52
52
53
53
54
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 8 December 2010
Document identifier: PCA85232