PCI-DIO PCI Isolated Digital Input/Output Card User Manual PCI-DIO User Manual Document Part N° Document Reference Document Issue Level 0127-0192 PCI-DIO\..\0127-0192.doc 2.1 Manual covers PCBs identified PCI-DIO Issue. 2.x (x is any digit) All rights reserved. No part of this publication may be reproduced, stored in any retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopied, recorded or otherwise, without the prior permission, in writing, from the publisher. Information offered in this manual is correct at the time of printing. The publisher accepts no responsibility for any inaccuracies. This information is subject to change without notice. All trademarks and registered names acknowledged. Amendment History Issue Level 1.0 2.0 Issue Date 20/11/97 9/12/97 Author Amendment Details PDJ PDJ 2.1 20/01/98 EGW First Issue as P/N 127-192 Change output latency and PCB layout diagram Reference “Readme.txt” file. Rename CISReg A & B. Counter clocks were 1 MHz Contents Contents INTRODUCTION.......................................................................................1 ABOUT THE MANUAL ............................................................................2 INSTALLING THE PCI-DIO ....................................................................3 CONNECTION DETAILS .........................................................................4 Suitable Interface Signal Types .................................................................5 PROGRAMMING DETAILS.....................................................................6 Address Map.............................................................................................6 Digital Outputs..........................................................................................6 Digital Inputs ............................................................................................7 i8254 / µPD71054 Counter / Timer ...........................................................7 Counter / Timer Modes .............................................................................7 Counter Control ........................................................................................9 Interrupt Selection...................................................................................11 TECHNICAL SPECIFICATIONS ...........................................................13 Electromagnetic Compatibility (EMC) ....................................................15 PCB LAYOUT DIAGRAM ......................................................................17 01270192.doc Introduction Page 1 INTRODUCTION The PCI-DIO is a PCI-compatible half-card which provides isolated digital inputs, outputs and counter/timers. There are 16 galvanically isolated digital inputs available on the board, which will accept up to 35 volts DC or AC peak, and which switch at nominally 3.5 volts DC or AC peak. There are 16 open collector digital outputs which are isolated from the digital inputs and the host PC but share a common ground connection. There are also three programmable counter/timers, the enable and clock inputs being available, isolated externally, if required , and the outputs being accessible isolated, externally and as interrupt sources. A 4 MHz crystal oscillator is available on board to allow the counter/timers to act as accurate timebases. All Input/Output lines are available at an industry standard 50 way D-type plug connector. One PCI interrupt line may be selectively driven by the five interrupt sources on the board, the interrupting source being readily identified by software interrogation of the on-board registers. The five interrupt sources are the three counter \timer outputs and a change of state detector on each byte of the digital inputs. The PCI-DIO is intended to be installed with the minimum of user interaction. The board is configured by the system BIOS and by the application drivers and no on-board links are required to select functionality. 01270192.doc About the Manual Page 2 ABOUT THE MANUAL This manual is organised into four chapters. Each chapter covers a different aspect of using the PCI-DIO. In order to get the best results from the product, the user is urged to read all chapters, paying particular note to Chapter 1 which deals with the initial installation of the card. Chapter 1 Explains how to install the card in your computer. Chapter 2 Details the connections to and from the card. Chapter 3 Gives details of the card’s address mapping and internal register details allowing the user to write custom software to control the card. Chapter 4 Presents the card’s technical specification. Use this section to determine the card’s suitability for a particular application This manual describes the complete hardware functionality of the PCI-DIO board. All the functions may not necessarily be supported by the current release of the NT driver and DLL set. 01270192.doc Chapter 1 Installation Page 3 CHAPTER 1 INSTALLING THE PCI-DIO The card is installed by removing the cover of the host computer and inserting the card into a free PCI slot. The rear panel of the card should then be secured to the rear panel of the host computer with the screw supplied with the computer. When the computer is switched on, the BIOS will detect the presence of the card and will allocate it with a base address and an interrupt. These parameters may then be used to configure application software to access the card. If the card is to be directly accessed by a users DOS application, it will be necessary for the application to find out where the BIOS has located the card. To this end a software function has been provided. Refer to the “Readme.txt” file on the supplied disk for details. 01270192.doc Chapter 2 Connection Details Page 4 CHAPTER 2 CONNECTION DETAILS The following table refers to the 50 way D-type plug at the rear of the card. PIN USAGE 1 Digital Input 1 or counter timer 0 clock (+ve) 2 Digital Input 2 or counter timer 0 enable (+ve) 3 Digital Input 3 or counter timer 1 clock (+ve) 4 Digital Input 4 or counter timer 1 enable (+ve) 5 Digital Input 5 or counter timer 2 clock (+ve) 6 Digital Input 6 or counter timer 2 enable (+ve) 7 Digital Input 7 (+ve) 8 Digital Input 8 (+ve) 9 Digital Input 9 (+ve) 10 Digital Input 10 (+ve) 11 Digital Input 11 (+ve) 12 Digital Input 12 (+ve) 13 Digital Input 13 (+ve) 14 Digital Input 14 (+ve) PIN USAGE 18 Digital Input 1 or counter timer 0 clock (-ve) 19 Digital Input 2 or counter timer 0 enable (-ve) 20 Digital Input 3 or counter timer 0 clock (-ve) 21 Digital Input 4 or counter timer 1 enable (-ve) 22 Digital Input 5 or counter timer 2 clock(-ve) 23 Digital Input 6 or counter timer 2 enable (-ve) 24 Digital Input 7 (-ve) 25 Digital Input 8 (-ve) 26 Digital Input 9 (-ve) 27 Digital Input 10 (-ve) 28 Digital Input 11 (-ve) 29 Digital Input 12 (-ve) 30 Digital Input 13 (-ve) 31 Digital Input 14 (-ve) PIN USAGE 34 Digital output 1 (+ve) 15 Digital Input 15 (+ve) 32 Digital Input 15 (-ve) 48 16 Digital Input 16 (+ve) 33 Digital Input 16 (-ve) 49 17 Digital Output Ground 35 Digital output 2 (+ve) 36 Digital output 3 (+ve) 37 Digital output 4 (+ve) 38 Digital output 5 (+ve) 39 Digital output 6 (+ve) 40 41 42 43 44 45 46 47 Digital output 7 (+ve) Digital output 8 (+ve) Digital output 9 (+ve) Digital output 10 (+ve) Digital output 11 (+ve) Digital output 12 (+ve) Digital output 13 (+ve) Digital output 14 or counter/timer 0 out (+ve) Digital output 15 or counter/timer 1 out (+ve) Digital output 16 or counter/timer 2 out (+ve) Digital Output Ground 50 01270192.doc Chapter 2 Connection Details Page 5 Suitable Interface Signal Types Each PCI-DIO digital input has two connections across which a voltage is connected. This voltage may be between -50 volts and +50 volts. Any voltage between -50 volts and +2.4 volts will be interpreted as logic zero, and any voltage between +4.4 volts and +50 volts will be interpreted as logic 1. The input current for on each input signal is a constant 1mA, when the input conforms to the logic 1 requirements, and 5uA (max) for a logic 0. The digital output connections are open collector with a pair of common ground connections. When energised, an output will sink up to 500mA. with a saturation voltage of 1.6volts at 350mA. load. When de-energised, the outputs will withstand 80 volts DC. There is no electrical connection between the each of the input circuits, the outputs circuits and the host PC. If an output is driving any form of inductive load, it is recommended that a reverse biased diode is connected across the load to catch back EMFs generated when the output is de-energised and the current falls to zero. 01270192.doc Chapter 3 Programming Details Page 6 CHAPTER 3 PROGRAMMING DETAILS This chapter provides details of the cards internal registers. Address Map The address map for the PCI-DIO occupies a 12-byte block of addresses. All the following addresses are relative to PCI base address register 2, located at address 18 (hex) in the PCI configuration space. ADDRESS Base + 0 Base + 1 Base +2 Base + 3 Base + 4 Base + 6 Base + 8 Base + 9 Base + A Base + B FUNCTION Interrupt enable register Interrupt status register Counter Input Select Register A Counter Input Select Register B Data output buffer Data input buffer Counter/timer 0 Count Register Counter/timer 1 Count Register Counter/timer 2 Count Register Counter/timer Control Register Data width Byte Byte Byte Byte Word Word Byte Byte Byte Byte READ/ WRITE R/W R W W W R R/W R/W R/W W Digital Outputs By writing a byte or word to the Data Output Buffer (word write to base + 4), the digital outputs may be controlled. A logic 1 written to the register causes the open collector output to turn on, and pull the output low. Consequently there is a logic inversion through the digital outputs of the card. Bit 0 (LSbit) of the Data Output Buffer controls Digital Output 1, and bit 15 (MSbit) controls Digital Output 16. It should be noted that there is a latency of 2.4 mS between writing to the output buffer and the output changing state. 01270192.doc Chapter 3 Programming Details Page 7 Digital Inputs When the Data Input Buffer is read Buffer (word read to base + 6), it reflects the true status of the digital inputs at the time when the read takes place. Bit 0 (LSbit) of the Data Input Buffer reflects the state of Digital Input 1 and bit 15 (MSbit) reflects the state of Digital Input 16 i8254 / µPD71054 Counter / Timer The counter/timer circuit contains three independent 16-bit counters which may be operated in a variety of modes. There are five basic modes of operation with each mode providing a different output signal. Presented here is a brief summary of some of the modes possible by programming the counter / timer’s internal registers. All three counter/timers may be operated independently, with separate clocks and enable controls. Counter 0, Counter 1 and Counter 2 may be connected in series. Counter 0 output to Counter 1 clock input and/or Counter 1 output to Counter 2 clock input, to allow the facility of generating very long delay periods. The outputs from any counter/timer may be configured to generate an interrupt when going high or low, and may also be made accessible on the back panel connector. The clock and enable inputs of the counter/timers may also be made accessible on the back panel connector. Counter / Timer Modes The following modes of operation exist by programming the control register within the i8254 / µPD71054. N.B. The interrupts may be generated when the Counter/timer outputs go low or high, selected by bits in the counter control registers. 01270192.doc Chapter 3 Programming Details Page 8 Mode 0 When programmed, the output pin will go LOW. When the counter decrements from the value loaded into the count registers to zero, the output pin will go HIGH. It will remain high until the count is re-programmed into the count registers. Mode 1 When the count registers are programmed the output pin will be HIGH. When a LOW going signal is applied to the gate input, the count starts and the output will fall LOW, returning HIGH at the end of the count. Mode 2 This mode operates as a frequency divider. When programmed the output pin is HIGH. When the count decrements to a value of 1 the output pin will go LOW for ONE clock cycle only and then return HIGH. This cycle repeats continuously without the need to re-program the count value. Mode 3 When programmed the output pin will toggle each time the count register decrements to its base level from the value programmed into it. If the count value loaded is an odd number then the counter will reach zero before the output pin toggles. This mode therefore acts as a frequency divider with an approximate 1:1 mark-space ratio. Mode 4 This mode is similar to mode 2 but the output pin pulses when the count reaches zero instead of 1. Mode 5 This mode is similar to mode 4 except that the count sequence is triggered by the gate line. 01270192.doc Chapter 3 Programming Details Page 9 Counter Control The control and output lines of the counter/timer may be accessed on the rear panel connector by sacrificing some of the digital I/O lines. The clock inputs of the i8254 counter/timer are selected using the Counter Input Select Register A at Base + 2 (Hex), as shown below:- Counter Input Select Register A (Base + 2) Function Bit no. b7 b6 Not used Counter 0 interrupt level:- b5..b4 Counter 2 clock source:- b3..b2 Counter 1 clock source:- b1..b0 Counter 0 clock source:- 0 = Interrupt on counter out low 1 = Interrupt on counter out high 00 = 4 MHz clock 01 = IN5 input line 10 = Counter 1 output 11 = IN9 input line 00 = 4 MHz clock 01 = IN3 input line 10 = Counter 0 output 11 = IN9 input line 00 = 4 MHz clock 01 = IN1 input line 10 = Counter 2 output 11 = IN9 input line The digital input bandwidth is limited such that the external clock inputs cannot be guaranteed at frequencies in excess of 10kHz. Similarly, the external enable inputs can only time external events to an accuracy of 100µS. 01270192.doc Chapter 3 Programming Details Page 10 The enable inputs and the destination of the outputs of the i8254 counter are selected using the Counter Input Select Register B at Base + 3 (Hex), as shown below:- Bit no. b7 b6 b5 b4 b3 b2 b1 b0 Counter Input Select Register B (Base + 3) Function Counter 2 interrupt level:0 = Interrupt on counter out low 1 = Interrupt on counter out high Counter 1 interrupt level:0 = Interrupt on counter out low 1 = Interrupt on counter out high Output 16 source 0 = Bit 15 data output buffer 1 = Counter/timer 2 output Output 15 source 0 = Bit 14 data output buffer 1 = Counter/timer 1 output Output 14 source 0 = Bit 13 data output buffer 1 = Counter/timer 0 output Counter 2 enable source:0 = Permanently enabled 1 = IN6 input line Counter 1 enable source:0 = Permanently enabled 1 = IN4 input line Counter 0 enable source:0 = Permanently enabled 1 = IN2 input line One or more of the counter timer outputs may be made available to the user at Digital Outputs 14 to 16. It should be noted that the 2.4 mS latency between the counter/timer output changing state and the output pin reflecting that change will still exist, so the accuracy of the output time periods generated cannot be guaranteed to be better than this delay. 01270192.doc Chapter 3 Programming Details Page 11 Interrupt Selection A total of five sources of interrupt are available from the digital inputs and the counter/timers. These interrupts are summarised below:• INT1 (COS0) is asserted whenever any of Digital Inputs 1 to 8 change state. • INT2 (COS1) is asserted whenever any of Digital Inputs 9 to 16 change state. • INT3 (OUT0) is the output from Counter/timer 0, and may be used to generate interrupts on timed events. • INT4 (OUT1) is the output from Counter/timer 1, and may be used to generate interrupts on timed events. • INT5 (OUT2) is the output from Counter/timer 2, and may be used to generate interrupts on timed events. The use of interrupts is not essential but greatly enhances the functionality of the card. 01270192.doc Chapter 3 Programming Details Page 12 To enable the generation of an interrupt or a combination of interrupts, an enable word must be written to the Interrupt Enable Register at Base + 0 (Hex), as shown below:- Bit no. b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Enable Register (Base + 0) Function Not used Not used Not used Counter/timer 2 interrupt control (1 = Enable, 0 = Disable) Counter/timer 1 interrupt control (1 = Enable, 0 = Disable) Counter/timer 0 interrupt control (1 = Enable, 0 = Disable) Change of state 1 interrupt control (1 = Enable, 0 = Disable) Change of state 0 interrupt control (1 = Enable, 0 = Disable) When an interrupt is recognised by the processor, the source or sources of interrupt may be read from the Interrupt status register at Base + 1 (Hex), as shown below:- Bit no. b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Status Register (Base + 1) Function Not used Not used Not used Counter/timer 2 interrupt occurred Counter/timer 1 interrupt occurred Counter/timer 0 interrupt occurred Change of state 1 interrupt occurred Change of state 0 interrupt occurred Having serviced an interrupt, the source may be cleared by momentarily clearing the relevant bit in the interrupt enable register. 01270192.doc Chapter 4 Technical Specifications Page 13 CHAPTER 4 TECHNICAL SPECIFICATIONS Number Of Input Channels: 16 Maximum input voltage: ±50 Volt DC or AC peak Input Threshold (Vth): 2.4 volts minimum. 4.4 volts maximum. Input current: 1mA ±200µA for Vth < Vin < 50 V DC +5 µA (max) for -50 V DC < Vin < Vth. Input Bandwidth: 10kHz. Number of Output Channels: 16 Maximum ON state current: 500mA. ON state voltage: 1.6 volts (max.) @ Iout = 350mA. Max. board output dissipation: 2 watts for each group of 8 outputs (Outputs 1 to 8 and 9 to 16) Maximum OFF state voltage: 80 volts DC Output latency: 2.4 mS max. Maximum Isolation Voltage: 350 volts DC or AC peak. Counter/timers: 3 x 16 Bit. Counter/timers 0, 1 and 2 may be cascaded to provide a single 48 bit Counter/timer. All Counter/timers may be clocked externally at a maximum rate of 10 kHz. On board Oscillator: Frequency 4 MHz. Stability ñ 100ppm 0 - 70øC 01270192.doc Chapter 4 Technical Specifications Page 14 Interrupt Sources: Register selectable to 3 Counter/timer outputs, and 2 input change of state detection groups. Interrupt Levels Supported: All PCI interrupts Address Overhead: 12 contiguous addresses in 12 byte block Board Power Requirement: +5 Volts, 1.0 W maximum Signal Connections: 1 x 50 way male ‘D-type’ plug Dimensions: 125 (L) x 91 (H) board only 135 (L) x 122 (H) x 22 (W) including bracket 01270192.doc Chapter 4 Technical Specifications Page 15 Electromagnetic Compatibility (EMC) This product meets the requirements of the European EMC Directive (89/336/EEC) and is eligible to bear the CE mark. It has been assessed operating in our standard industrial PC. However, because the board can be installed in a variety of computers, certain conditions have to be applied to ensure that the compatibility is maintained. It meets the requirements of EN55022:1995 for a Class A product subject to those conditions. • The board must be installed in a computer system which provides screening suitable for an industrial environment. • Any recommendations made by the computer system manufacturer/supplier must be complied with regarding earthing and the installation of boards. • The board must be installed with the backplate securely screwed to the chassis of the computer to ensure good metal-to-metal (i.e. earth) contact. • Most EMC problems are caused by the external cabling to boards. It is imperative that any external cabling to the board is totally screened, and that the screen of the cable connects to the metal end bracket of the board and hence to earth. It is recommended that round screened cables with a braided wire screen are used in preference to those with a foil screen and drain wire. Use metal connector shells which connect around the full circumference of the screen; they are far superior to those which earth the screen by a simple “pig-tail”. Standard ribbon cable will not be adequate unless it is contained wholly within the cabinetry housing the industrial PC. • Ensure that the screen of the external cable is bonded to a good RF earth at the remote end of the cable. Failure to observe these recommendations may invalidate the EMC compliance. 01270192.doc Chapter 4 Technical Specifications Page 16 Warning This is a Class A product. In a domestic environment this product may cause radio-interference in which case the user may be required to take adequate measures. EMC Specification A suitably compliant industrial PC fitted with this card meets the following specification: Emissions EN 55022:1995 Radiated Class A Conducted Class A & B Immunity EN 50082-2:1995 incorporating: Electrostatic Discharge EN 61000-4-2 Radio Frequency Susceptibility ENV50140 ENV50204 Fast Burst Transients EN 61000-4-4 01270192.doc Chapter 4 Technical Specifications Page 17 PCB LAYOUT DIAGRAM 01270192.doc