REVISION NUMBER : REV 2 PAGES : 1 of 13 DATE : 2-13-04 PI6049A Contact Image Sensor Data Sheet PI6049A Data Sheet __________________________________________________________________________________________ Key Features • • • • • • • • • • • • 600 dots per inch (dpi) 344 image sensor elements (pixels) 42.3 µm pixel center-to-center spacing (23.62 dots/mm) On-chip amplifier Single 5.0V power supply 5.0V input clocks 2.5 MHz maximum pixel rate Parallel / integrate and transfer Power down circuit High sensitivity Low power Low noise General Description Peripheral Imaging Corporation’s PI6049A Contact Image sensor is a 600 dpi resolution linear image sensor, which employs PIC’s proprietary CMOS Image Sensing Technology. The sensor contains an on-chip output amplifier, power down circuitry and parallel transfer features that are uniquely combined with present-day activepixel-sensor technology. The image sensors are designed to be cascaded end-to-end on a printed circuit board (PCB) and packaged in an image sensing module. Applications for the sensor array includes facsimiles, PC scanners, check readers, and office automation equipment. Figure 1 is a block diagram of the sensor. Each sensor consists of 344 active pixels, their associated multiplexing switches, buffers, and an output amplifier circuit with a power down feature. The detector’s element-to-element spacing is approximately 42.3 µm. The size of each sensor without the scribe lines is 14560 µm by 380 µm. 14560µm 42.3µm 1 3 2 4 341 Row of 344 Pixels and Video Line Multiplexer 342 343 344 380µm Parallel Transfer, Storage Cells and Readout Registers Amplifier, PowerDown and Offset Control GBST SI SIC CLK AVDD DVDD AVSS DVSS VOUT Figure 1. Sensor Block Diagram Page 2 of 13, Revised 2-13-04 OR OS VR SO PI6049A Data Sheet __________________________________________________________________________________________ PI6049A Unique Features There are five unique features incorporated in the PI6049A which improve the sensor’s performance. 1. Pixel-to-Pixel Offset Cancellation Circuit The sensor employs a pixel-to-pixel offset cancellation circuit, which reduces the Fix Pattern Noise (FPN), and amplifier offsets. In addition, this innovative circuit design greatly improves the optical linearity and low noise sensitivity. 2. Parallel Integrate, Transfer and Hold The sensor has a parallel integrate, transfer and hold feature, which allows the sensor to be read out while photon integration is taking place. These features are approached through the use of an integrate and hold cell, located at each pixel site. Each pixel’s charge is read from its storage site as the sensor’s shift register sequentially transfers each pixel’s charge onto a common video line. 3. Dual Scan Initiation Inputs, GBST and SI Each sensor has two scan initiation inputs, the Global Start Pulse (GBST) and the Start Pulse (SI). These clocks help to reduce the sensor-to-sensor transition Fix Pattern Noise by initializing and preprocessing all sensors simultaneously before they start their readout scan. The internal shift register starts the scan after GBST is clocked in on the falling edge of the Clock input (CLK). The Start Input Control (SIC) selects the first sensor in a sequence of cascaded sensors to operate with 29 clock cycles of delay by connecting it to Vdd on the first sensor, and to Ground for all subsequent sensors. Then, only the first sensor clocks out 29 inactive pixels before accessing its first active pixel. During these 29 clock cycles, the first sensor and all of the subsequent cascaded sensors cycle through their pre-scan initialization process. After initialization, only the first sensor starts its read cycle with its first-active pixel appearing on the 30th clock cycle. The second and subsequent sensors await the entry of their Start Pulse (SI). Furthermore, the first sensor’s Start Pulse (SI) is left unconnected, while the subsequent sensors all have their Start Pulse’s (SI) connected to the SO of their respective preceding sensor. The external scan Start Pulse (SI) is connected to all of the sensors' Global Start Pulse (GBST) inputs. As the first sensor completes its scan, its End-of-Scan (SO), appears 1 pixel before its last pixel. The second and subsequent sensors will then start their registers 1 clock cycle before the appearance of their respective first pixels, and their SO also appears 1 pixel before their last pixel. 4. Power Saving Each sensor incorporates a power-saving feature when multiple sensors are cascaded together to form a linear imaging array. The Start Input Control (SIC) on each sensor selects a unique feature of powering up a particular sensor’s output amplifier when it’s selected and powering it down when not selected. For the PI6049A, only the first sensors’ amplifier is used and all subsequent sensors have their amplifiers turned off. The pixels from each sensor are transferred onto a common video line which is connected to the amplifier of the first sensor. The advantage of using only one active amplifier is two fold; saving on power consumption and reducing sensor-tosensor FPN. 5. Common Reference Voltage between Cascaded Sensors Each sensor has an input/output bias control (VR), which serves as an offset voltage reference. Each bias control pad is connected to an internal bias source and tied to its own amplifier’s reference bias input. In operation, these pads on every sensor are connected together. Each sensor then “shares” the same bias level to maintain a constant bias among all of the sensors. Page 3 of 13, Revised 2-13-04 PI6049A Data Sheet __________________________________________________________________________________________ Functional Description ¾ Input / Output Terminals The PI6049A image sensor has 13 input and output (I/O) pads. Their symbols and function descriptions are listed in Table 1. Symbol I/O GBST I SI I SIC I CLK I AVDD DVDD AVSS DVSS I I I I VOUT O OR OS O O VR I SO O Description Global Start Pulse: Globally initializes the start inputs of all sensors and starts the scanning process of the first sensor. (See discussion of the sensors unique features for further details). Start Pulse: Input to start a line scan. (See discussion of the sensors unique features for further details). Start Input Control: Input to control the Start Pulse to the first sensor. (See discussion of the sensors unique features for further details). Clock: Clock Input for the Shift Register. Analog Power Supply. Digital Power Supply. Analog Signal Ground. Digital Signal Ground. Video Output Voltage: Output Video Signal from the Amplifier. Differential Reference Output. Differential Video Output. Reference Voltage: Reference input voltage for the Amplifier Output. Sets the Output’s reset (dark) level End of Scan Pulse: Output from the Shift Register at the end of a scan. Table 1. Input and Output Terminals Page 4 of 13, Revised 2-13-04 PI6049A Data Sheet __________________________________________________________________________________________ ¾ Bonding Pad Layout Diagram Figure 2 shows the bonding pad locations for the PI6049A sensor. 14560µm 380µm Figure 2. Bonding Pad Locations ¾ Wafer Scribe Line Figure 3 outlines the scribe line dimensions surrounding the sensor die on a wafer. 60µm 15µm 380µm 55µm 14560µm 60µm Figure 3. Wafer Scribe Line Page 5 of 13, Revised 2-13-04 55µm PI6049A Data Sheet __________________________________________________________________________________________ Electro-Optical Specifications Table 2 lists the electro-optical specifications of the PI6049A sensor at 25oC and Vdd = 5.0 volts. Parameter Number of Pixels Pixel-to-Pixel Spacing Sensitivity (1) Saturation Voltage (2) Photo-Response Non-Uniformity (3) Adjacent Photo-Response Non-Uniformity(4) Dark Output Voltage Level (5) Dark Output Non-Uniformity (6) Random Thermal Noise (rms) (7) Sensor-to-Sensor Photo-Response NonUniformity (8) Photo Response Linearity (9) Symbol Min 344 42.3 Typical Sv Vsat Up Upn Vd Ud Vno Max 344 42.3 665 2.0 7.5 7.5 0.7 100 4 Units µm V / µJ / cm2 V % % V mV mV Usensor 7.5 % PRL 2.0 % Table 2. Electro-Optical Specifications • Notes for the above Table 2 are listed on the next page under “Definitions of Electro-Optical Specifications”. Page 6 of 13, Revised 2-13-04 PI6049A Data Sheet __________________________________________________________________________________________ Definitions of Electro-Optical Specifications All electrical specifications are measured at a pixel rate of 2.0 MHz, a temperature of 25oC, Vdd=5.0 volts, and at an integration time of 2.2ms. The average output voltage (Vpavg), is adjusted to approximately 1.0V, unless stated otherwise. The modules’ internal Green LED (525 ± 20 nm) was used as the light source for measurements requiring illumination. As a guideline, the recommended load on the output should be 1KΩ<RL<10kΩ. All measurements were taken with a 2k ohm load on the output. 1. Sensitivity (Sv) is defined as the slope of the Vpavg vs Exposure curve. 2. Saturation Voltage (VSat) is defined as the maximum video output voltage swing measured from the dark level to the saturation level. It is measured by using the module LED light source with the module imaging a uniform white target. The LED light level is increased until the output voltage no longer increases with an increase in the LED brightness. The dark level is set by the voltage on VR and in a typical CIS module application, sits at approximately 0.7V. 3. Photo-Response Non-Uniformity (Up). Up = ((Vpmax-Vpavg)/Vpavg) x 100% or ((Vpavg-Vpmin)/Vpavg) x 100%, whichever is the greater, where Vpmax is the maximum pixel output voltage in the light, Vpmin is the minimum pixel output voltage in the light and Vpavg is average output voltage of all pixels in the light. 4. Adjacent Photo-Response Non-Uniformity (Upn). Upn = Max ((Vpn – Vpn+1) / Min (Vpn, Vpn+1)) x 100%, where Vpn is the pixel output voltage of pixel n in the light. 5. Dark Output Voltage (Vd). Vd is the average dark output level and is essentially the offset level of the video output in the dark. The dark level is set by the voltage on VR and in a typical CIS module application, sits at approximately 0.7V. 6. Dark Output Non-Uniformity (Ud). Ud = Vdmax-Vdmin, where Vdmax is the maximum pixel output voltage in the dark and Vdmin is the minimum pixel output voltage in the dark. 7. Random Thermal Noise (rms), (Vno), is the standard deviation of n pixels in the dark. A sample size n=64 was used. A 4 mV rms value has a peak-peak equivalent of 24 mV. 8. Sensor-to-Sensor Photo-Response Non-Uniformity (Usensor). Usensor = (Vpavg – Wavg) / Wavg), where Wavg is the average output of all sensors on the same wafer that pass all other specifications. 9. Photo-Response Linearity (PRL). Photo-Response Linearity is defined as the max deviation of response compared to a best fit line. The data points plotted are those that lie within 10% of the saturation level and 90% of the saturation level. Outside these ranges the module is operating close to non-linearity. Page 7 of 13, Revised 2-13-04 PI6049A Data Sheet __________________________________________________________________________________________ Recommended Operating Conditions Table 3 lists the recommended operating conditions @ 25oC. Parameter Power Supply Clock Input Voltage high level (1) Clock Input Voltage low level (1) Power Supply Current Reference Voltage (2) Clock Frequency (3) Pixel Rate Integration Time (Line Scan Rate) (4) First Die Subsequent Die Clock Pulse Duty Cycle (5) Symbol Vdd IDD (sensor selected) IDD (sensor not selected) VR Tint Min 4.5 2.8 0 0.6 0.5 0.5 Typ 5.0 Vdd 0 3.2 2.6 0.7 2.0 2.0 Max 5.5 Vdd 0.8 5 4 1.1 2.5 2.5 Units V V V mA mA V MHz MHz µs µs / die 150 138 75 % Table 3. Recommended Operating Conditions @ 25oC Notes: 1. Applies to all clocks; GBST, SIC, SI and CLK. 2. The dark level is set by the voltage on the VR input pad, which is internally set to a typical value of 0.7 volts. Alternatively, if the user wishes to use a dark level greater than this, then VR can be supplied externally. 3. Although the device will operate with a pixel rate of less than 500 KHz, it is recommended that the device be operated above 500 KHz to maintain performance characteristics. Operating below 500 KHz may result in a significant integration of dark current. 4. Tint is the integration time of a single sensor and is the time between two Start Pulses. The minimum integration time is the time it takes to clock out 29 inactive pixels and 344 active pixels. If several sensors are cascaded together in a module then the minimum integration time is the time it takes to clock out 29 inactive pixels and 344 active pixels from the first sensor and 344 pixels from each of all subsequent sensors, at a given frequency. 5. The clock duty cycle is defined as the ratio of the positive duration of the clock to its period. Page 8 of 13, Revised 2-13-04 PI6049A Data Sheet __________________________________________________________________________________________ Absolute Maximum Ratings Table 4 lists the absolute maximum ratings. Parameter Power Supply Voltage (Vdd) Clock Input Voltage high level (1) Clock Input Voltage low level (1) Operating Temperature Operating Humidity Storage Temperature Storage Humidity Max 10 Vdd + 0.5 -0.5 -10 to +50 +10 to +85 -25 to +75 +10 to +90 Table 4. Absolute Maximum Ratings Note 1. Applies to all clocks; GBST, SIC, SI and CLK Page 9 of 13, Revised 2-13-04 Units V V V °C RH% °C RH% PI6049A Data Sheet __________________________________________________________________________________________ Timing Requirements The timing requirements and their symbols are listed in Table 5 and its accompanying timing diagrams are shown in Figures 4 and 5. Parameter Clock (CLK) Period Clock (CLK) Pulse Width Symbol Min Typ Max Units CLKp 400 500 2000 ns CLKpw Clock (CLK) Duty Cycle Data Setup Time Data Hold Time (1) (1) 375 ns 75 % Tset 20 ns Thold 25 ns Clock (CLK) rise time (2) CLKrt 70 ns Clock (CLK) fall Time (2) CLKft 70 End of Scan Rise Time (2) ns SOrt 50 ns End of Scan Fall Time (2) SOft 50 ns Global Start Rise Time (3) GBSTrt 70 ns GBSTft 70 ns Global Start Fall Time Pixel Rise Time Pixel Fall Time (4,5) (4,5) (3) Prt 115 ns Pft 75 ns Table 5. Timing Requirements Notes: 1. The shift register will load on all falling CLK edges, so setup and hold times (Tset, Thold) are needed to prevent the loading of multiple start pulses. This would occur if the GBST remains high during two fallings edges of the CLK signal. 2. SI starts the register scanning and the first active pixel is read out on the 30th clock cycle of the CLK signal. However, when multiple sensors are sequentially scanned, as in CIS modules, the SO from the predecessor sensor becomes the SI to the subsequent sensor, hence the SI clock = the SO clock. 3. As discussed under the third unique feature, the GBST starts the initialization process and preprocesses all sensors simultaneously in the first 29 clock cycles (29 pixels) before the first pixel is scanned onto the video line from the first sensor. 4. The transition between pixels does not always reach the dark offset level as shown in Figure 4 (Vout). Figure 4 shows the transition doing so for illustration purposes; however a stable pixel sampling point does exist for every pixel. 5. The pixel rise time is defined as the time from when the CLK’s rising edge has reached 50% of its maximum amplitude to the point when a pixel has reached 90% of its maximum amplitude. The pixel fall time is defined as the time from when a pixel’s charge begins to decrease from its maximum amplitude to within 10% of the lowest point before the next pixel begins to rise. Page 10 of 13, Revised 2-13-04 PI6049A Data Sheet __________________________________________________________________________________________ Figure 4 shows the initialization of the first sensor in relation to its subsequent cascaded sensors. The Start Input Control (SIC) selects the first sensor to operate with 29 clock cycles of delay by connecting it to Vdd on the first sensor and to Ground for all subsequent sensors. Hence the first sensor will operate with 29 inactive pixels being clocked out before its first active pixel is clocked out. The rise and fall times are listed in table 5 above. The End of Scan Pulse comes out in line with the second last active pixel, and the last active pixel of each sensor is the 344th pixel which coincides with the 344th clock cycle. GBST Last pixel of preceding sensor First pixel of succeding sensor CLK 28 29 30 31 32 33 34 35 36 373 27 372 26 371 3 370 2 369 1 1 2 3 1 2 3 4 SO 6 7 5 344 Active Pixels (344 Clocks) 344 4 3 343 CLKpw 2 342 1 29 Inactive pixels (29 Clocks) 341 VOUT CLKp CLKpw 50% CLK Thold CLKrt CLKft Tset GBST GRSTft GRSTrt prt 90% pft VOUT 10% Figure 4. Overall Timing Diagram CLK Thold 1 Thold 2 29 30 31 32 Tset GBST Tset Video Signal (Vout) 1 2 Figure 5. Timing of GBST-to-First Pixel of the First Sensor Page 11 of 13, Revised 2-13-04 3 4 PI6049A Data Sheet __________________________________________________________________________________________ PI6049A Image Sensors in a CIS Module Figure 6 shows a partial schematic detailing how numerous image sensors are serially concatenated in a CIS module. Since only the first sensor in the series of sensors is connected differently from the remaining sensors, only the first three sensors are shown. Note OS and OR are used as internal monitors and are not connected to the external module connector. Figure 6. CIS Module with PI6049A Image Sensors Page 12 of 13, Revised 2-13-04 PI6049A Data Sheet __________________________________________________________________________________________ 2004 Peripheral Imaging Corporation. Printed in USA. All rights reserved. Specifications are subject to change without notice. Contents may not be reproduced in whole or in part without the express prior written permission of Peripheral Imaging Corporation. Information furnished herein is believed to be accurate and reliable. However, no responsibility is assumed by Peripheral Imaging Corporation for its use nor for any infringement of patents or other rights granted by implication or otherwise under any patent or patent rights of Peripheral Imaging Corporation Page 13 of 13, Revised 2-13-04