PI6C2409 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero-Delay Clock Buffer Product Features Functional Description • • • • Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to output delay, less than 200ps Internal feedback allows outputs to be synchronized to the clock input • Operates at 3.3V VDD • Space-saving Packages: 150-mil SOIC (W) 173-mil TSSOP (L) The PI6C2409 is a PLL based, zero-delay buffer, with the ability to distribute nine outputs of up to 133MHz at 3.3V. All the outputs are distributed from a single clock input CLKIN and output OUT0 performs zero delay by connecting a feedback to PLL. Block Diagram Pin Configuration PI6C2409 has two banks of four outputs that can be controlled by the selection inputs, SEL1 & SEL2. It also has a powersparing feature: when input SEL1 is 0 and SEL2 is 1, PLL is turned off and all outputs are referenced from CLKIN. PI6C2409 is available in high drive and industrial environment versions. An internal feedback on OUT0 is used to synchronize the outputs to the input; the relationship between loading of this signal and the outputs determines the input-output delay. PI6C2409 are characterized for both commercial and industrial operation OUT0 CLKIN PLL MUX CLKIN OUTA1 OUTA2 VDD GND OUTB1 OUTB2 SEL2 OUTA1 OUTA2 OUTA3 SEL1 SEL2 Decode Logic OUTA4 OUTB1 1 2 3 4 5 6 7 8 16 15 16-Pin 14 W, L 13 12 11 10 9 OUT0 OUTA4 OUTA3 VDD GND OUTB4 OUTB3 SEL1 OUTB2 PI6C2409(-1, -1H) OUTB3 OUTB4 1 PS8613A 07/15/03 PI6C2409 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Input Select Decoding SEL2 SEL1 OUTA [1-4] OUTB [1-4] Output Source (OUT0) PLL 0 0 3- State 3- State PLL ON 0 1 PLL 3- State PLL ON 1 0 CLK IN CLK IN CLK IN O FF 1 1 PLL PLL PLL ON Pin Description Pin Signal D e s cription 1 C LK IN Input clock reference frequency (weak pull- down) 2, 3, 14, 15 O UTA[1- 4] C lock outputs, Bank A 4, 13 VDD 3.3V supply 5, 12 GN D Ground 6, 7, 10 ,11 O UTB[1- 4] C lock outputs, Bank B 8 SEL2 Select input, bit 2 (weak pull- up) 9 SEL1 Select input, bit 1 (weak pull- up) 16 O UT0 C lock O utput , internal PLL feedback 2 PS8613A 07/15/03 PI6C2409 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero Delay and Skew Control CLKIN Input to OUTx Delay vs. Difference in Loading between OUT0 pin and OUTx pins CLKIN - Input to OUTx Delay (ps) 800 600 400 200 0 -25 -20 -15 -10 0 -5 5 10 15 20 25 -200 -400 PI6C2409-1H -600 -800 PI6C2409-1 -900 -1000 Output Load Difference: OUT0 Load - OUTx Load (pF) The relationship between loading of the OUT0 signal and other outputs determines the input-output delay. Zero delay is achieved when all outputs, including feedback, are loaded equally. Maximum Ratings Supply Voltage to Ground Potential ............................................................................................................................. –0.5V to +7.0V DC Input Voltage (Except CLKIN) ........................................................................................................................ –0.5V to VDD +0.5V DC Input Voltage CLKIN ...................................................................................................................................................... –0.5 to 7V Storage Temperature ................................................................................................................................................... –65ºC to +150ºC Maximum Soldering Temperature (10 seconds) ........................................................................................................................... 260ºC Junction Temperature .................................................................................................................................................................. 150ºC Static Discharge Voltage (per MIL-STD-883, Method 3015) .................................................................................................... >2000V Operating Conditions (VCC = 3.3V ±0.3V) Parame te r VDD TA CL CIN De s cription M in. M a x. Units 3.0 3.6 V 0 70 Industrial Operating Temperature –40 85 Load Capacitance, below 100 MHz 30 Load Capacitance, from 100 MHz to 133 MHz 15 Input Capacitance 7 Supply Voltage Commerical Operating Temperature 3 ºC pF PS8613A 07/15/03 PI6C2409 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics for Industrial Temperature Devices Parame te r De s cription Te s t Conditions M in. M a x. VIL Input LOW Voltage 0.8 VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V 50.0 IIH Input HIGH Current VIN = VDD 125 VO L Output LOW Voltage IO L = 8mA (–1); IO L = 12mA (–1H) 0.4 VO H Output HIGH Voltage IO H = –8mA (–1); IO H = –12mA (–1H) IDD Bypass, PLL OFF SEL1 = 0, SEL2 = 1 1.0 IDD Supply Current Unloaded outputs 100 MHz, Select inputs at VDD or GND 54.0 Unloaded outputs 66 MHz, CLKIN 39.0 2.0 2.4 Units V µA V mA mA AC Electrical Characteristics for Industrial Temperature Devices Parame te rs FO N ame O utput Frequency Te s t Conditions 30pF load (–1, –1H) 10pF load, (–1, –1H) M in. Typ. M ax. Units 100 10.0 133 MHz Duty C ycle(1) (–1, –1H) Measured at VDD/2, FOUT = 66.67MHz 40.0 Duty C ycle(1) (–1H) Measured at VDD/2V, FOUT <50MHz 45.0 Rise Time(1) (–1) Measured between 0.8V and 2.0V 2.5 Rise Time(1) (–1H) Measured between 0.8V and 2.0V 1.5 Measured between 0.8V and 2.0V 2.5 Fall Time(1) (–1H) Measured between 0.8V and 2.0V 1.5 O utput to O utput Skew (–1,–1H)(1) All outputs equally loaded t0 Delay, C LK IN Rising Edge to O UT0 Rising Edge(1) (–1, –1H) Measured at VDD/2 0 ± 350 tSK(D) Device- to- Device Skew(1) (–1, –1H) Measured at VDD/2 on O UT0 pins of devices 0 700 tSLEW O utput Slew Rate(1) (–1, –1H) Measured between 0.8V & 2.0V on –1H device using Test C rt #2 C ycle- to- C ycle Jitter(1) (–1,–1H) Measured at 66.67 MHz, loaded 30pF load 200 ps PLL Lock Time(1) (–1, –1H) Stable power supply, valid clocks presented on C LK IN pin 1.0 ms tDC tR tF tSK(O) tJIT tLOCK Fall Time(1) (–1) 50 60.0 55.0 % ns 250 1 ps V/ns Notes: 1.See Switching Waveforms on page 6. 4 PS8613A 07/15/03 PI6C2409 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics for Commercial Temperature Devices Parame te r De s cription Te s t Conditions M in. M a x. VIL Input LOW Voltage 0.8 VIH Input HIGH Voltage 2.0 IIL Input LOW Current VIN = 0V 50 IIH Input HIGH Current VIN = VDD 125 VO L Output LOW Voltage IO L = 8mA (–1); IO L = 12mA (–1H) 0.4 VO H Output HIGH Voltage IO H = –8mA (–1); IO H = –12mA (–1H) 2.4 IDD Bypass, PLL off SEL1 = 0 SEL2 = 1 1.0 IDD Supply Current Unloaded outputs, 66.67 MHz, Select inputs at VDD or GND 39 IDD Supply Current Unloaded outputs 100 MHz Select Inputs @ VDD or GND 54 Units V µA V mA AC Electrical Characteristics for Commercial Temperature Device N ame 1 Parame te rs Te s t Conditions 30pF load (–1, –1H) M in. Typ. M ax. Units 100 FO O utput Frequency tDC Duty C ycle (–1H) Measured at VDD/2, FO < 50 MHz 45 50 55 Duty C ycle (–1,–1H) Measured at VDD/2, FO = 66 MHz 40 50 60 tR 133 Rise Time (–1) Rise Time (–1H) tF 10pF load, (–1, –1H) 10 Fall Time (–1) % 2.5 1.5 Measured between 0.8V and 2.0V 2.5 Fall Time (–1H) tS K (O ) MHz ns 1.5 O utput to O utput Skew (–1,–1H) All outputs equally loaded, VDD/2 t0 Input to O utput Delay, C LK IN Rising Edge to O UT0 Rising Edge (–1,–1H) Measured at VDD/2 0 ± 350 tS K (D) Device to Device Skew (–1,–1H) Measured at VDD/2 on O UT0 pins of devices 0 700 tS LEW O utput Slew Rate (–1,–1H) Measured between 0.8V and 2.0V on –1H device using Test C ircuit #2 C ycle- to- C ycle Jitter (–1,–1H) Measured at 66.67 MHz, loaded 30pF outputs 200 ps PLL Lock Time (–1,–1H) Stable power supply, valid clocks presented on C LK IN pins 1.0 ms tJIT tLO C K 250 1 ps V/ns Notes: 1. See Switching Waveforms on page 6 5 PS8613A 07/15/03 PI6C2409 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Waveforms thigh Duty Cycle Timing VDD/2 tlow VDD/2 tDC = thigh thigh+tlow VDD/2 All Outputs Rise/Fall Time OUTPUT Output-Output Skew OUTPUT 2.0V 0.8V tR 3.3V 2.0V 0.8V tF 0V VDD/2 VDD/2 OUTPUT tSK(O) Device-Device Skew OUTPUT Device 1 VDD/2 VDD/2 OUTPUT Device 2 tSK(D) Input-Output Propagation Delay INPUT VDD/2 VDD/2 OUTPUT t0 Test Circuit 1 0.1µF Test Circuit 2 0.1µF VDD OUTPUTS CLK out VDD 1kΩ CLOAD 0.1µF VDD GND CLK out OUTPUTS 0.1µF GND GND 1kΩ VDD 10pF GND Test Circuit for tSLEW ,Output slew rate on –1H device Test Circuit for all parameters except tSLEW 6 PS8613A 07/15/03 PI6C2409 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Packaging Mechanical: 16-Pin SOIC (W16) 16 3.78 3.99 .149 .157 .0099 .0196 0.25 x 45˚ 0.50 1 .0075 .0098 0-8˚ .386 .393 9.80 10.00 0.41 1.27 .053 .068 .0155 .0260 0.393 0.660 REF 1.35 1.75 .016 .050 .2284 .2440 5.80 6.20 SEATING PLANE .050 BSC 1.27 0.19 0.25 .0040 0.10 .0098 0.25 .013 .020 0.330 0.508 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Packaging Mechanical: 16-Pin TSSOP (L16) 16 .169 .177 4.3 4.5 1 .193 .201 4.9 5.1 .004 .008 .047 max. 1.20 0.45 .018 0.75 .030 SEATING PLANE .0256 BSC 0.65 .007 .012 .002 .006 0.09 0.20 .252 BSC 6.4 0.05 0.15 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS 0.19 0.30 Note: Controlling dimensions in millimeters. Ref: JEDEC MS - 012 AC 7 PS8613A 07/15/03 PI6C2409 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Ordering Information Orde ring Code Package Name Package Type W16 16- pin 150- mil SOIC PI6C2409- 1HL L16 16- pin TSSOP PI6C2409- 1HWI W16 16- pin 150- mil SOIC L16 16- pin TSSOP PI6C2409 - 1W PI6C2409- 1HW PI6C2409- 1LI PI6C2409- 1HLI Ope rating Range Commercial Industrial Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 8 PS8613A 07/15/03