PI6C2516 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Phase-Locked Loop Clock Driver with 16 Clock Outputs Product Features Description High Performance Phase-Locked Loop Clock Distribution for Synchronous DRAM, server and networking applications. The PI6C2516 family is a low-skew, low jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM, server and networking applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK input to any clock output will be nearly zero. This zero-delay feature allows the CLK input clock to be distributed, providing 4 banks of four outputs. Zero Input-to-Output delay: Distribute One Clock Input to four banks of four outputs, with separate output enables for each bank. Allow Clock Input to have Spread Spectrum modulation for EMI reduction. The clock outputs track the Clock Input modulation. For test purposes, the PLL can be bypassed by strapping the AVCC to ground. Maximum clock frequency of 150 MHz. The PI6C2516 family has the same pinout as the TI CDC2516, with the added feature of allowing Spread Spectrum clock input. Low jitter: Cycle-to-Cycle jitter ±100ps max Operates at 3.3V VCC Available Packaging: 48-pin TSSOP (Thin Shrink Small Outline) (A) Pin Description VCC 1Y0 1Y1 GND GND 1Y2 1Y3 VCC 1G GND AVCC CLK AGND AGND GND 2G VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC Block Diagram 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 48-Pin 39 11 A 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 VCC 4Y0 4Y1 GND GND 4Y2 4Y3 VCC 1G 4 2G 4 3G 4 1Y [0:3] 2Y [0:3] 3Y [0:3] 4G 4G GND AVCC FB_IN AGND FB_OUT GND 3G VCC 3Y0 3Y1 GND GND 3Y2 3Y3 VCC 4 CLK 4Y [0:3] PLL FB_IN FB_OUT AVCC 1 PS8440C 07/24/01 PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Functions Pin Name Pin Numbe r Type D e s cription CLK 12 I Clock input. CLK allows spread spectrum. FB_IN 37 I Feedback input. FB_IN provides the feedback signal to the internal PLL. CLK ↑ and FB_IN↑ are synchronized so that there is normally zero phase error between CLK and FB_IN. 1G 9 I O utput bank enable. When 1G is LO W, outputs 1Y[0:3] are disabled to a logic low state. When 1G is HIGH, all outputs 1Y[0:3] are enabled and switched at the same frequency as CLK . 2G 16 I O utput bank enable. When 2G is LO W, outputs 2Y[0:3] are disabled to a logic low state. When 2G is HIGH, all outputs 2Y[0:3] are enabled and switched at the same frequency as CLK . 3G 33 I O utput bank enable. When 3G is LO W, outputs 3Y[0:3] are disabled to a logic low state. When 3G is HIGH, all outputs 3Y[0:3] are enabled and switched at the same frequency as CLK . 4G 40 I O utput bank enable. When 4G is LO W, outputs 4Y[0:3] are disabled to a logic low state. When 4G is HIGH, all outputs 4Y[0:3] are enabled and switched at the same frequency as CLK . FB_O UT 35 O Feedback output. FB_O UT is dedicated for external feedback. FB_O UT has an embedded 25Ω series- damping resistor of the same value as the clock outputs. 1Y[0:3] 2,3,6,7 O Clock outputs. These outputs provide low- skew copies of CLK _IN. Each output has an embedded 25Ω series- damping resistor of the same value as the clock outputs. 2Y[0:3] 18,19,22,23 O Clock outputs. These outputs provide low- skew copies of CLK _IN. Each output has an embedded 25Ω series- damping resistor of the same value as the clock outputs. 3Y[0:3] 26,27,30,31 O Clock outputs. These outputs provide low- skew copies of CLK _IN. Each output has an embedded 25Ω series- damping resistor of the same value as the clock outputs. 4Y[0:3] 42,43,46,47 O Clock outputs. These outputs provide low- skew copies of CLK _IN. Each output has an embedded 25Ω series- damping resistor of the same value as the clock outputs. AVCC 11,38 Power AGND 13,14,36 VC C 1,8,17,24,25,32,41,48 Power GND 4,5,10,15,20,21,28,29, 34,39,44,45 Ground Ground Analog power supply. AVCC can be also used to bypass the PLL for test purposes. When AVC C is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Ground Analog ground. AGND provides the ground reference for the analog circuitry. Power supply 2 PS8440C 07/24/01 PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Absolute Maximum Ratings (Over Operating Free-Air Temperature Range, unless otherwise noted) Symbol Parame te r M in. M ax. VCC Supply voltage range 0.5 4.6 VI Input voltage range(1) 0.5 6.5 VO Voltage range applied to any output(1,2) 0.5 VCC + 0.5 VIK Input Clamp Current 50 Units V IO_DC Continuous output current (VO = 0 or VCC) ±50 IO_DC Continuous output through VCC or ground ±100 Power Maximum power dissipation at TA= 55oC in still air(3) 0.85 W TSTG Storage temperature 150 oC 65 mA Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect reliability. Notes: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6V maximum. 3. Maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. Recommended Operating Conditions (4) Symbol Parame te r M in. M ax. 3.6 VCC Supply voltage 3.0 VIH High level input voltage 2.0 VIL Low level input voltage VI Input voltage TA Operating free- air temperature IOH IOL 0.8 Units V 0.0 VCC 0 70 ºC High level output current 12 mA Low level output current 12 Note 4. Unused inputs must be held high or low to prevent them from floating. 3 PS8440C 07/24/01 PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Function Table xG L L H H CLK L H L H xY [0:3] L L L H FB_OUT L H L H Note: x is from 1 to 4 Electrical Characteristics (Over Recommended Operating Free-air Temperature Range) Symbol VIK, Input clamp voltage Te s t Condition VCC Input current at 18mA 3V IOH = 100µA VOH Min. to Max. IOH = 12mA 3V IOH = 6mA IOL = 100µA VOL Min. to Max. IOL = 12mA 3V IOL = 6mA II, Input current Clock input voltage = VCC or GND Analog supply current, ICC Clock input voltage = VCC or GND ∆ICC CI Input voltage = VCC or GND CO O utput voltage = VCC or GND M in. 3.3V to 3.6V 4 M ax. 0.79 1.2 VCC 0.2 2.99 2.1 2.66 2.4 2.83 0.2 0.3 0.8 0.15 0.55 4.0 ±5 µA 12 mA 4.0 6.0 5.0 Units V 0.01 3.6V 3.3V O ne input @ VCC 0.6V, other inputs @VCC or GND Typ. 500 PS8440C pF µA 07/24/01 PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements (Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature) Symbol Parame te r M in. M ax. 25 150 6 133 Stabilization time after power up(3) 1 ms Input clock duty cycle 40 60 % O perator clock frequency FCLKOP Application clock tCLKAPP tSTABLILIZATION DCYI (1) frequency(2,4) Units MHz Notes: 1. Operating Clock Frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for low-speed system debug). 2. Application Clock Frequency indicates a range over which the PLL must meet all of the timing parameters. 3. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. 4. Frequency and loading condition should not exceed 0.85 watt power dissipation (package limitation). Please refer to Graph 1. 350 ICC (mA) 300 250 Load = 22pF 200 Load = 10pF 150 100 50 0 0 50 100 150 Clock Frequency (MHz) Graph 1. Dynamic Current vs. Clock Frequency (VCC = 3.6V, TA = 25°C) Switching Characteristics (Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature, CL = 22pF) (1,3) Parame te r From (Input) To (Output) tphase error CLKIN↑ = 100MHz FBIN↑ tsk(O)(2) Any Y or FBOUT Jitter(pk- pk) F(CLKIN > 66MHz) Duty cycle tr tf F(CLKIN ≤ 66MHz) F(CLKIN > 66MHz) VCC = 3.3V ± 0.165V M in. Typ. M ax. VCC = 3.3V ± 0.3V M in. 150 Typ. M ax. +170 200 Any Y or FBOUT CLKIN = 50 to 150MHz from 20% to 80% Units 100 100 45 55 45 55 1.3 2.1 0.7 2.1 1.7 2.5 1.2 2.5 ps % ns Notes: 1. These parameters are not production tested. 2. The tsk(O) specification is only valid for equal loading of all outputs. 3. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 5 PS8440C 07/24/01 PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Parameter Measurement Information 3V Input 50% VCC 50% VCC From Output Under Test 0V tpd 500Ω 22pF Output 80% 20% tr Load Circuit VOH 80% 50% VCC 20% VOL tf Voltage Waveforms Propagation Delay times Notes: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: CLKIN ≤ 100MHz, ZO = 50 ohms, tr ≤ 1.2ns, tf ≤ 1.2ns. 3. The outputs are measured one at a time with one transition per measurement. CLKIN FBIN tphase error FBOUT Any Y tsk(O) Any Y Any Y tsk(O) Phase Error and Skew Calculations 6 PS8440C 07/24/01 PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 48-pin Thin Shrink Small-OutlinePackage (A) 48 .236 .244 1 6.0 6.2 .488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE .004 0.09 .008 0.20 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS .002 .006 0.05 0.15 .007 .010 .0197 BSC 0.50 0.17 0.27 0.45 .018 0.75 .030 .319 BSC 8.1 Ordering Information Part Numbe r Orde ring P/N Package PI6C2516 PI6C2516A 48- pin TSSO P Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 7 PS8440C 07/24/01