ADVANCE INFORMATION PI6CV855-02 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 200 MHz SSTL_2 PLL Clock Driver Product Features Product Description PLL clock distribution optimized for SSTL_2 Distributes one differential clock input pair to five differential clock output pairs. Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the input clocks. Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.5V for differential output drivers Packaging: Plastic 28-pin TSSOP (L28) The PI6CV855-02 PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to five differential pairs of clock outputs (Y[0:4], Y[0:4]) and one differential pair feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the Analog Power input (AVDD). When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. Block Diagram Pin Configuration CLK CLK FBIN PLL The PI6CV855-02 is able to track Spread Spectrum Clocking to reduce EMI. Y0 GND 1 28 Y4 Y0 Y0 2 27 Y1 Y0 3 26 Y4 VDDQ Y1 VDDQ 4 25 GND Y2 CLK 5 24 FBOUT CLK AVDD AGND 6 23 22 FBOUT VDDQ 8 21 FBIN GND 9 20 FBIN Y1 10 19 Y1 11 18 GND VDDQ FBOUT VDDQ 12 17 Y3 FBOUT Y2 13 16 Y3 Y2 14 15 GND Y2 FBIN Y3 Y3 Y4 Y4 AVDD Logic and Test Ciruit 1 7 28-Pin L P.01 05/08/02 ADVANCE INFORMATION PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pinout Table Pin Name Pin No. I/O Type CLK CLK 5 6 I Y[0:4] 3,11,13,17,27 Y[0:4] 2,10,14,16,28 FBOUT FBOUT 23 24 FBIN FBIN 21 20 VDDQ 4,12,18,22,26 AVDD 7 AGND 8 GND 1,9,15,19,25 De s cription Reference Clock input Clock outputs. O Complement Clock outputs. Feedback output, and Complement Feedback Output I Feedback input, and Complement Feedback input Power Supply for I/O pins. Power Analog/core power supply. AV can be used to bypass the PLL for testing purposes. When DD AVDD is strapped to ground, PLL is bypassed & CLK is buffered directly to the device outputs. Ground Analog/core ground. Provides the ground reference for the analog/core circuitry Ground for I/O pins. Function Table Inputs Outputs PLL State AVDD CLK CLK Y[0:4] Y[0:4] FBO UT FBO UT GND L H L H L H Bypassed/O ff GND H L H L H L Bypassed/O ff 2.5V(nom) L H L H L H On 2.5V(nom) H L H L H L On 2 P.01 05/08/02 ADVANCE INFORMATION PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Absolute Maximum Ratings (Over operating free-air temperature range) Symbol M in. M ax. I/O supply voltage range and analog/core supply voltage range 0.5 3.6 VI Input voltage range 0.5 VO Output voltage range 0.5 Tstg Storage temperature 65 VDDQ, AVDD Parame te r Units V VDDQ+0.5 oC 150 Note: Stress beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Timing Requirements (Over recommended operating free-air temperature) Symbol AVDD, VDDQ = 2.5V ±0.2V D e s cription Units M in. M ax. O perating clock frequency(1,2) 75 200 Application clock frequency(3) 100 200 tDC Input clock duty cycle 40 60 % tSTAB PLL stabilization time after powerup 100 µs fCK MHz Notes: 1. The PLL is able to handle spread spectrum induced skew. 2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the other timing parameters. (Used for low-speed debug). 3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters. 3 P.01 05/08/02 ADVANCE INFORMATION PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Specifications Recommended Operating Conditions Symbol Parame te r M in. Nom. M ax. Units AVDD Analog/core supply voltage 2.3 2.5 2.7 VDDQ O utput supply voltage 2.3 2.5 2.7 VOH High- level output voltage 1.8 VDDQ VOL Low- level output voltage 0 0.5 VIX Input differential- pair crossing voltage (VDDQ/2) 0.2 (VDDQ/2) +0.2 VOX O utput differential- pair crossing voltage at the SDRAM clock input (VDDQ/2) 0.2 (VDDQ/2) +0.2 VIN Input voltage level 0.3 VDDQ +0.3 VID Input differential voltage between CLK and CLK 0.36 VDDQ +0.6 VOD O utput differential voltage between Y[n] and Y[n] and FBO UT and FBO UT 0.7 VDDQ +0.6 0 70 TA O perating free air temperature V °C Electrical Characteristics Parame te r VIK II IDDQ IADD CI Te s t Conditions AVDD, VDDQ M in. Typ. M ax. Units All inputs II = 18mA 2.3V 1.2 V CLK , FBIN VI = VDDQ or GND 2.7V ±10 µA Dynamic supply current of VDDQ VDD = 2.7V (1) 300 mA Dynamic supply current of AVDD VDD = 2.7V (1) 12 mA 3.0 pF CLK and CLK FBIN and FBIN VI = VDD or GND 2.5V 2.0 Notes: 1. Driving memory chips with 120 Ohm termination resistor for each clock output pair at 134 MHz. 4 P.01 05/08/02 ADVANCE INFORMATION PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 AC Specifications Switching characteristics over recommended operating free-air temperature range, fCLK > 100 MHz (unless otherwise noted). (See Figure 1 and 2) Parame te r De s cription Diagram AVCC, VD D Q = 2.5V ±0.2V M in. Nom. M ax 0 50 t(θ) Static phase offset(1) Figure 4 50 tjit(cc) Cycle- to- cycle jitter Figure 3 75 75 tjit(per) Period jitter Figure 6 75 75 tjit(hper) Half- period jitter Figure 7 100 100 tsl(i) Input clock slew rate(2) Figure 8 1.0 2.0 tsl(o) Output clock slew rate(2) Figure 8 1.0 2.0 tsk(o) Output clock skew Figure 5 Units ps V/ns 100 ps The PLL meets all the above parameters while supporting SSC synthesizers with the following parameters (3) SSC modulation frequency 30.0 50.0 kHz SSC clock input frequency deviation 0.00 0.50 % PLL loop bandwidth 2 Phase angle MHz 0.031 degrees Notes: 1. Static Phase offset does not include jitter. 2. The slew rate is determined from the IBIS model with test load shown in Figure 1. 3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification. 5 P.01 05/08/02 ADVANCE INFORMATION PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 VDD Z = 60Ω Z = 60Ω DDR SDRAM R =120Ω DDR SDRAM Figure 1. IBIS Model Output Load VDDQ/2 Z = 60Ω R =10Ω Z = 50Ω C=14pF R = 50Ω –VDDQ/2 Z = 60Ω R =10Ω Z = 50Ω C=14pF R = 50Ω –VDDQ/2 SCOPE –VDDQ/2 Figure 2. Output Load Test Circuit 6 P.01 05/08/02 ADVANCE INFORMATION PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Yx,FBOUT Yx,FBOUT t cycle n t cycle n+1 t jit(cc) = t cycle n - t cycle n+1 Figure 3. Cycle-to-Cycle Jitter CLK CLK FBIN FBIN t( t( )n ∑ 1 = ) n+1 n=N t t( N )n (N is a large number of samples) Figure 4. Static Phase Offset Yx Yx Yx, FBOUT Yx, FBOUT t sk(o) Figure 5. Output Skew 7 P.01 05/08/02 ADVANCE INFORMATION PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Yx, FBOUT Yx, FBOUT t cycle n Yx, FBOUT Yx, FBOUT 1 fO t jit(per) = t cycle n 1 fO Figure 6. Period Jitter Yx, FBOUT Yx, FBOUT t n+1 half period t half period n 1 fO t jit(hper) = t half period n 1 2*f O Figure 7. Half-Period Jitter 80% Clock Inputs and Outputs VDDQ 80% 20% 20% 0V t sl(i), t sl(o) t sl(i), t sl(o) Figure 8. Input and Output Slew Rates 8 P.01 05/08/02 ADVANCE INFORMATION PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Packaging Mechanical: 28-Pin TSSOP (L28) 28 .169 .177 4.3 4.5 .004 .008 1 .378 .386 9.6 9.8 0.45 0.75 SEATING PLANE .0256 BSC 0.65 .007 .012 0.19 0.30 .018 .030 .252 BSC 6.4 .047 1.20 Max .002 .006 0.09 0.20 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS 0.05 0.15 Ordering Information Orde ring Code PI6CV855- 02L Package Name Package Type L28 28- pin, 4.4mm wide TSSO P Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 9 P.01 05/08/02