ETC PI74ALVTC16373

PI74ALVTC16373
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16-Bit Transparent D-Type Latch
with 3-STATE Outputs
Product Features
Product Description
• PI74ALVTC family is designed for low voltage operation,
VDD = 1.8V to 3.6V
• Supports Live Insertion
• 3.6V I/O Tolerant Inputs and Outputs
• Bus Hold
• High Drive, -32/64mA @ 3.3V
• Uses patented noise reduction circuitry
• Power-off high impedance inputs and outputs
• Industrial operation at –40°C to +85°C
• Packages available:
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 173 mil wide plastic TVSOP (K)
– 48-pin 300 mil wide plastic SSOP (V)
Pericom Semiconductor’s PI74ALVTC series of logic circuits are
produced in the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The PI74ALVTC16373 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as two 8-bit latches or one 16-bit
latch. When the Latch Enable (LE) input is HIGH, the Q outputs
follow the (D) inputs. When LE is taken LOW, the Q outputs are
latched at the levels set up at the D inputs.
A buffered Output Enable (OE) input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or
a high-impedance state in which the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the
increased drive provide the capability to drive bus lines without an
interface or pullup components. OE does not affect internal
operations of the latch. Old data can be retained or new data can be
entered while the ouputs are in the high-impedance state.
Logic Block Diagram
1OE
1LE
To ensure the high-impedance state during power up or power
down, OE should be tied to Vdd through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
1
48
The family offers both I/O Tolerant, which allows it to operate in
mixed 1.8/3.6V systems, and “Bus Hold,” which retains the data
input’s last state whenever the data input goes to high-impedance,
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
C1
2
1D1
47
1Q1
1D
To Seven Other Channels
2OE
2LE
24
25
C1
13
2D1
36
2Q1
1D
To Seven Other Channels
1
PS8355A
11/23/98
PI74ALVTC16373
16-Bit Transparent D-Type Latch With 3-STATE Outputs
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Truth Table(1)
Product Pin Description
Pin Name
OE
LE
Dx
Qx
GND
V CC
Description
Output Enable Input (Active LOW)
Latch Enable (Active HIGH)
Data Inputs
3-State Outputs
Ground
Power
Inputs (1)
1OE
1
48
1LE
1Q1
2
47
1D1
1Q2
3
46
1D2
GND
4
45
GND
1Q3
5
44
1D3
1Q4
6
43
1D4
VCC
7
42
VCC
1Q5
8
41
1D5
1Q6
9
40
1D6
GND
10
39
GND
1Q7
11
38
1D7
1Q8
12
37
1D8
2Q1
13
36
2D1
35
2D2
34
GND
33
2D3
2Q2
14
GND
15
2Q3
16
48-PIN
A48
K48
V48
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X
QO
H
X
X
Z
Note:
1. H
L
X
Z
Product Pin Configuration
2Q4
17
32
2D4
VCC
18
31
VCC
2Q5
19
30
2D5
2Q6
20
29
2D6
GND
21
28
GND
2Q7
22
27
2D7
2Q8
23
26
2D8
2OE
24
25
2LE
2
Outputs (1)
= High Signal Level
= Low Signal Level
= Don’t Care or Irrelevant
= High Impedance
PS8355A
11/23/98
PI74ALVTC16373
16-Bit
Transparent
D-Type
Latch
With
3-STATE Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range, VDD .......................................... –0.5V to 4.6V
Input Voltage Range, VI ................................................. -0.5V to 4.6V
Output Voltage Range, VO (3-Stated) ............................ -0.5V to 4.6V
Output Voltage Range, VO(1) (Active) ................. –0.5V to VDD +0.5V
DC Input Diode Current (IIK) VI<0V ........................................ -50mA
DC Output Diode Current (IOK)
VO<0V ................................................................................... -50mA
VO>VDD ................................................................................ ±50mA
DC Output Source/Sink Current (IOH/IOL) ......................... -64/128mA
DC VDD or GND Current per Supply Pin (ICC or GND) ....... ±100mA
Storage Temperature Range, Tstg ................................. –65°C to150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Recommended Operating Conditions2
M in.
M ax.
O perating
1.8
3.6
Data Retention O nly
1.2
3.6
2.0
VDD
Supply voltage
VIH
High- level input voltage
VDD = 2.7V to 3.6V
VIL
Low- level input voltage
VDD = 2.7V to 3.6V
VI
Input voltage
VO
O utput voltage
O utput current in IOH/IOL
∆t/∆v
TA
Input transistion rise or fall rate(3)
O perating free- air temperature
0.8
- 0.3
3.6
Active State
0
VDD
O ff State
0
3.6
VDD =
VDD =
VDD =
VDD =
Units
V
- 32/64
±24
±18
±6
mA
0
10
ns/V
−40
85
C
3.0V to 3.6V
3.0V to 3.6V
2.3V to 2.7V
1.8V
Notes
1. Absolute maximum of IO must be observed.
2. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3 As measured between 0.8V and 2.0V, VDD = 3.0V.
3
PS8355A
11/23/98
PI74ALVTC16373
16-Bit Transparent D-Type Latch With 3-STATE Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted)
DC Characteristics (2.7V<VDD ≤ 3.6V)
Parame te r
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
Conditions
VDD
2.7
IOH = −18mA
2.2
2.4
3.0
IOH = −32mA
LOW Level Output Voltage
2.2
2.0
V
IOL = 100µA
2.7 - 3.6
0.2
IOL = 12mA
2.7
0.4
IOL = 18mA
0.4
IOL = 24mA
0.45
3.0
IOL = 32mA
0.5
IOL = 64mA
0.55
Input Leakage Current
VI = VDD, or GND
3.6
±5.0
IOZ
3- STATE Output Leakage
VO = 3.6V
2.7
±10
IOFF
Power- OFF Leakage Current
VI or VO ≤ 3.6V
0
10
IODL
Output Current Low
VIN = VIH or VIL, Vo = 1.5V(1)
IODH
Output Current High
VIN = VIH or VIL, Vo = 1.5V(1)
IHOLD
Bus Hold Current
A or B Outputs
II
VI = 0.8V
∆IDD
Quiescent Supply Current
Increase in IDD per input
3.6
3.0
VI = 2.0V
VI = 0 to 3.6V
IDD
Units
VDD - 0.2
IOH = −24mA
VOL
M ax.
0.8
2.7 - 3.6
IOH = −12mA
HIGH Level Output Voltage
Typ.
2.0
IOH = −100µA
VOH
M in.
3.6
VI = VDD or GND
150
334
- 58
- 114
VIH = VDD - 0.6V,
Other inputs at VDD or Gnd
2.7 - 3.6
mA
75
- 75
±500
50
VDD ≤ (VI,VO) ≤ 3.6V
µA
µA
±50
400
Notes
1. Duration of test must not exceed 1 second with only 1 output tested at a time.
4
PS8355A
11/23/98
PI74ALVTC16373
16-Bit
Transparent
D-Type
Latch
With
3-STATE Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted) (continued from previous page)
DC Characteristics (2.3V ≤ VDD ≤ 2.7V)
D e s cription
Parame te rs
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
Conditions
VDD
HIGH Level O utput Voltage
Typ.
2.3 - 2.7
IOH = - 12mA
2.3
IOH = - 18mA
LOW Level O utput Voltage
VDD - 0.2
1.8
V
1.7
0.2
IOL = 12mA
0.4
IOL = 18mA
2.3
0.5
IOL = 24mA
II
0.55
Input Leakage Current
VI = VDD or GND
2.7
±5.0
IOZ
3- STATE O utput Leakage
VO = 3.6V
2.3
±10
IOFF
Power- O FF Leakage Current
VI or VO ≤ 3.6V
0
10
IODL
Output Current Low
VIN = VIH or VIL, VO = 1.5V(2)
O utput Current High
VIN = VIH or VIL, VO =
Bus Hold Current
A or B O utputs
VI = 0.7V
IODH
IHOLD(1)
IDD
∆ΙDD
Q uiescent Supply Current
Increase in IDD per input
Units
0.7
2.3 - 2.7
VOL
M ax.
1.6
IOH = - 100µA
VOH
M in.
1.5V(2)
2.7
2.5
VI = 1.7V
110
264
- 30
- 60
- 90
40
VDD ≤ (VI,VO) ≤ 3.6V
±40
2.3 - 2.7
mA
90
VI = VDD or GND
VIH = VDD - 0.6V,
Inputs at VDD or Gnd
µA
µA
400
Notes:
1. Not Guaranteed
2. Duration of test must not exceed 1 second with only 1 output tested at a time.
5
PS8355A
11/23/98
PI74ALVTC16373
16-Bit Transparent D-Type Latch With 3-STATE Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted) (continued from previous page)
DC Characteristics (1.8V ≤ VDD ≤ 2.3V)
De s cription
Parame te rs
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
Conditions
VDD
1.8 - 2.3
IOH = - 100µA
M in.
Typ.
M ax.
0.7 x VDD
0.2 x VDD
VDD - 0.2
IOH = - 6mA
1.8
V
1.4
IOL = 100µA
0.2
IOL = 6mA
0.3
II
Input Leakage Current
VI = VDD or GND
2.3
±5.0
IOZ
3- State Output Leakage
VO = 3.6V
1.8
±10
IOFF
Power- OFF Leakage Current
VI = VO ≤ 3.6V
0
10
IODL
Output Current Low
VIN = VIH or VIL, VO = 0.9V(2)
Output Current High
VIN = VIH or VIL, VO =
Bus Hold Current
A or B Outputs
VI = 0.4
50
VI = 1.3
- 50
IODH
IHOLD(1)
IDD
Quiescent Supply Current
∆ΙDD
Increase in IDD per input
0.9V(2)
VI = VDD or GND
VDD ≤ (VI,VO) ≤ 3.6V
VI = VDD - 06V,
Other inputs at VDD or Gnd
1.8
1.8
Units
50
137
- 14
- 34
20
µA
mA
µA
±20
400
Notes:
1. Not Guaranteed
2. Duration of test must not exceed 1 second with only 1 output tested at a time.
6
PS8355A
11/23/98
PI74ALVTC16373
16-Bit
Transparent
D-Type
Latch
With
3-STATE Outputs
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AC Electrical Characteristics
TA = -40°C to +85°C, CL = 50pF, RL = 500W
VD D = 3.3V
±0.3V
Symbol
Parame te r
tPLH, tPHL
VD D = 2.5V
±0.2V
VD D = 1.8V
M in.
M ax.
M in.
M ax.
M in.
M ax.
Prop Delay, D to Q
0.5
2.5
1.0
3.2
1.5
4.0
tPLH, tPHL
Prop Delay, LE to Q
1.0
3.1
1.5
4.2
2.0
4.5
tPZH, tPZL
O utput Enable Time
1.0
3.1
1.5
4.7
2.0
4.5
tPHZ, tPLZ
O utput Disable Time
1.5
3.7
1.5
3.5
2.0
5.0
tO S HL
tO S LH
O utput to O utput Skew(1)
0.5
0.5
Units
ns
0.5
Note
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same
direction, either HIGH or LOW (tOSHL) or LOW to HIGH (tOSLH).
AC Setup Requirements
TA=-40ºC to +85ºC, CL =50pF, RL = 500Ω
Symbol
Parame te r
VDD =3.3V ± 0.3V
M in.
Typ.
VDD =2.5V ± 0.2V
M in.
Typ.
VDD =1.8V
M in.
tSU
Setup Time, D to LE
0.5
0
0
tH
Hold Time, D to LE
0.8
0.5
1.0
tW
LE Pulse Width, High
1.5
1.5
1.5
Typ.
Units
ns
Capacitance
Symbol
Parame te r
Conditions
TA = +25°C
Typical
Units
CIN
Input Capacitance
VDD = 1.8, 2.5V or 3.3V, VI = 0V or VDD
6
COUT
Output Capacitance
VI = 0V or VDD, VDD = 1.8V, 2.5V or 3.3V
7
Power Dissipation Capacitance
VI = 0V or VDD, F = 10 MHz
VDD = 1.8V, 2.5V or 3.3V
20
CPD
7
pF
PS8355A
11/23/98
PI74ALVTC16373
16-Bit Transparent D-Type Latch With 3-STATE Outputs
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Test Circuits and Switching Waveforms
Switch Position
Parameter Measurement Information (VDD = 1.8V - 3.6V)
2 x VDD
R1
500Ω
From Output
Under Test
Open
RL
500Ω
50pF
CL
GND
Te s t
S1
tpd
Open
tPLZ/tPZL
2 x VDD
tPHZ/tPZH
GND
Pulse Width
(See Note A)
VDD
Low-High-Low
Pulse
VDD/2
0V
tW
VDD
High-Low-High
Pulse
Setup, Hold, and Release Timing
VDD/2
0V
Data
Input
tSU
Timing
Input
tH
VDD
VDD/2
0V
Propagation Delay
VDD
VDD
VDD/2
0V
VDD/2
Input
0V
tPHL
tPLH
VDD
Output
VDD/2
VOL
tPHL
tPLH
VDD
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions
such that the output is LOW except when disabled by the
output control.
Waveform 2 is for an output with internal conditions
such that the output is HIGH except when disabled by
the output control.
C. All input pulses are supplied by generators having the
following characteristics: PRR ≤ 10 MHz, ZO = 50Ω,
tr ≤ 2ns, tf ≤ 2ns, measured from 10% to 90%, unless
otherwise specified.
D. The outputs are measured one at a time with one transition per measurement.
Opposite Phase
Input Transition
VDD/2
0V
Enable Disable Timing
VDD
Output
Control
(Active LOW)
VDD/2
0V
tPLZ
tPZL
VDD
Output
Waveform 1
S1 at 2xVDD
(see Note B)
Output
Waveform 2
S1 at GND
VDD
VDD/2
+0.15V
tPZH
VOL
tPHZ
-0.15V
VOH
VDD/2
0V
(see Note B)
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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