ETC PI74AVC+16373A

PI74AVC+16373
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2.5V 16-Bit Transparent D-Type Latch
with 3-State Outputs
Product Features
Product Description
• PI74AVC+16373 is designed for low voltage operation,
VCC = 1.65V to 3.6V
Pericom Semiconductor’s PI74AVC+ series of logic circuits are
produced using the Company’s advanced submicron CMOS
technology, achieving industry leading speed.
• True ±24mA Balanced Drive @ 3.3V
The PI74AVC+16373 is particularly suited for implementing buffer
registers, I/O ports, bidirectional bus drivers, and working registers.
This device can be used as two 8-bit latches or one 16-bit latch.
When the Latch Enable (LE) input is HIGH, the Q outputs follow the
(D) inputs. When LE is taken LOW, the Q outputs are latched at the
levels set up at the D inputs.
• Compatible with Philips and T.I. AVC Logic family
• IOFF supports partial power-down operation
• 3.6V I/O Tolerant inputs and outputs
• All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
A buffered Output Enable (OE) input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state in which the outputs neither
load nor drive the bus lines significantly. The high-impedance state
and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not affect
internal operations of the latch. Old data can be retained
or new data can be entered while the outputs are in the high
impedance state.
• Industrial operation at –40°C to +85°C
• Available Packages:
– 48-pin 240-mil wide plastic TSSOP
– 48-pin 173-mil wide plastic TVSOP
Logic Block Diagram
1OE
1LE
To ensure the high impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
1
48
C1
2
1D1
47
1Q1
1D
To Seven Other Channels
2OE
2LE
24
25
C1
13
2D1
36
2Q1
1D
To Seven Other Channels
1
PS8526
03/01/01
PI74AVC+16373
2.5V 16-Bit Transparent D-Type Latch
with 3-State Outputs
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Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.)
Notes:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Supply voltage range, VCC ............................................. –0.5V to +4.6V
Input voltage range, VI ................................................... –0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, VO(1) ...................... –0.5V to +4.6V
Voltage range applied to any output in the
high or low state, VO(1,2) ......................................... –0.5V to VCC +0.5V
Input clamp current, IIK (VI <0) .................................................... –50mA
Output clamp current, IOK (VO <0) .............................................. –50mA
Continuous output current, IO .................................................... ±50mA
Continuous current through each VCC or GND ......................... ±100mA
Package thermal impedance, θJA(3): package A .........................64°C/W
package K ..........................48°C/W
Storage Temperature range, Tstg .................................... –65°C to 150°C
Product Pin Configuration
1. Input & output negative-voltage ratings may be
exceeded if the input and output curent rating are
observed.
2. Output positive-voltage rating may be exceeded up to
4.6V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
Product Pin Description
1OE
1
48
1LE
1Q1
1Q2
2
47
3
46
1D1
1D2
GND
1Q3
4
45
5
44
1Q4
VCC
1Q5
1Q6
6
43
7
42
8
41
9
GND
1Q7
10
48-Pin 40
A,K 39
11
38
1Q8
2Q1
12
37
13
36
2Q2
GND
14
35
15
34
2Q3
2Q4
VCC
2Q5
16
33
17
32
18
31
19
30
2Q6
GND
20
29
21
28
2Q7
2Q8
22
27
23
26
2D7
2D8
2OE
24
25
2LE
Pin Name
OE
LE
Dx
Qx
GND
VCC
GND
1D3
1D4
VCC
1D5
1D6
Description
3-State Output Enable Inputs (Active LOW)
Latch Enable (Active HIGH)
Data Inputs
3-State Outputs
Ground
Power
Truth Table(1)
Inputs
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
Outputs
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
Notes:
1. H = High Signal Level
L = Low Signal Level
X = Don't Care or Irrelevant
Z = High Impedance
2D6
GND
2
PS8526
03/01/01
PI74AVC+16373
2.5V 16-Bit Transparent D-Type Latch
with 3-State Outputs
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Recommended Operating Conditions(1)
VCC
Supply Voltage
M in.
M ax.
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2V
VIH
High- level Input Voltage
VCC
VCC = 1.4V to 1.6V
0.65 x VCC
VCC = 1.65V to 1.95V
0.65 x VCC
VCC = 2.3V to 2.7V
VCC = 3V to 3.6V
1.7
2
VCC = 1.2V
VIL
Low- level Input Voltage
VI
Input Voltage
VO
Output Voltage
IOHS High- level output current
IOLS
Low- level output current
∆t∆v Input transition rise or fall rate
TA
Units
V
GND
VCC = 1.4V to 1.6V
0.35 x VCC
VCC = 1.65V to 1.95V
0.35 x VCC
VCC = 2.3V to 2.7V
0.7
VCC = 3V to 3.6V
0.8
0
3.6
Active State
0
VCC
3- State
0
3.6
VCC = 1.4V to 1.6V
–4
VCC = 1.65V to 1.95V
–6
VCC = 2.3V to 2.7V
– 12
VCC = 3V to 3.6V
– 24
mA
VCC = 1.4V to 1.6V
4
VCC = 1.65V to 1.95V
6
VCC = 2.3V to 2.7V
12
VCC = 3V to 3.6V
24
VCC = 1.4V to 3.6V
5
ns/V
85
°C
Operating free- air temperature
–40
Notes:
1. All unused inputs must be held at VCC or GND to ensure proper device operation.
3
PS8526
03/01/01
PI74AVC+16373
2.5V 16-Bit Transparent D-Type Latch
with 3-State Outputs
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DC Electrical Characteristics (Over the Operating Range, TA = -40°C +85°C)
Te s t Conditions (1)
Parame te rs
IOH = –100µA
VOH
II
M in.
1.4V to 3.6V
VCC –0.2V
IOHS = –4mA
VIH = 0.91V
1.4V
1.05
IOHS = –6mA
VIH = 1.07V
1.65V
1.2
IOHS = –12mA
VIH = 1.7V
2.3V
1.75
IOHS = –24mA
VIH = 2V
3V
2.0
IOLS = 100µA
VOL
VCC
M ax.
1.4V to 3.6V
0.2
IOLS= 4mA
VIL = 0.49V
1.4V
0.4
IOLS= 6mA
VIL = 0.57V
1.65V
0.45
IOLS = 12mA
VIL = 0.7V
2.3V
0.55
IOLS = 24mA
VIL = 0.8V
3V
0.8
Control Inputs
VI = VCC or GND
3.6V
±2.5
IOFF
VI or VO = 3.6V
0
±10
IOZ
VO = VCC or GND
3.6V
±10
ICC
VI = VCC or GND
3.6V
40
IO = 0
Control Inputs
VI = VCC or GND
CI
Data Inputs
CO
Typ.
Outputs
VO = VCC or GND
2.5V
3.5
3.3V
3.5
2.5V
6
3.3V
6
2.5V
6.5
3.3V
6.5
Units
V
µA
pF
Note: Typical values are measured at TA = 25°C.
4
PS8526
03/01/01
PI74AVC+16373
2.5V 16-Bit Transparent D-Type Latch
with 3-State Outputs
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Timing requirements over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
VCC = 1.2V
VCC = 1.5V
± 0.1V
M in.
M in.
M ax.
M ax. M in.
tw Pulse duration, LE HIGH
tsu Setup time, data before LE↓
th Hold time, data after LE↓
VCC = 1.8V
± 0.15V
M ax.
VCC = 2.5V
± 0.2V
M in.
M ax.
VCC = 3.3V
± 0.3V
M in.
2.2
2
1.8
1.7
1.2
1.1
0.9
0.8
2
1.1
1.1
1.1
1
Units
M ax.
ns
Switching Characteristics over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
Parame te rs
tpd
From
(Input)
To
(Output)
D
VCC = 1.2V
Q
LE
VCC = 1.5V
± 0.1V
Typ.
M in.
5.8
1.2
6.8
7.2
1.4
VCC = 1.8V
± 0.15V
M ax. M in.
VCC = 2.5V
± 0.2V
VCC = 3.3V
± 0.3V
M ax.
M in.
M ax.
M in.
M ax.
1
5.7
0.8
3.3
0.7
2.8
8.3
1.1
6.6
0.8
4
0.7
3.2
ten
OE
Q
7.4
1.6
8.8
1.6
6.7
1.4
4.3
0.7
3.4
tdis
OE
Q
8.4
2.5
9.4
2.3
7.8
1.3
4.2
1.2
3.9
Units
ns
Operating Characteristics, TA= 25°C
Parame te rs
Cpd Power Dissipation
Capacitance
Outputs Enabled
Outputs Disabled
Te s t Conditions
CL = 0pF,
f = 10 MHz
5
VCC = 1.8V
±0.15V
VCC = 2.5V
±0.2V
VCC = 3.3V
±0.3V
Typical
Typical
Typical
40
43
47
20
22
24
Units
pF
PS8526
03/01/01
PI74AVC+16373
2.5V 16-Bit Transparent D-Type Latch
with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.2V AND 1.5V ± 0.1V
2xVCC
S1
2Ω
From Output
Under Test
CL = 15pF
Open
GND
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
VOL
tPHZ
VCC/2
VOH –0.1V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
6
PS8526
03/01/01
PI74AVC+16373
2.5V 16-Bit Transparent D-Type Latch
with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.8V ±0.15V
2xVCC
S1
12ΩkΩ
From Output
Under Test
CL = 30
15pF
Open
GND
2Ω
1 kΩ
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
0.15V
VOL
tPHZ
VCC/2
VOH –0.1V
0.15V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 2. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
7
PS8526
03/01/01
PI74AVC+16373
2.5V 16-Bit Transparent D-Type Latch
with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ± 0.2V
2xVCC
S1
500Ω
2Ω
From Output
Under Test
CL =30
15pF
Open
GND
500Ω
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.15V
VOL
tPHZ
VCC/2
VOH –0.15V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 3. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
8
PS8526
03/01/01
PI74AVC+16373
2.5V 16-Bit Transparent D-Type Latch
with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 3.3V ± 0.3V
2xVCC
S1
500Ω
2Ω
From Output
Under Test
CL = 30
15pF
Open
GND
500Ω
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
0.3V
VOL
tPHZ
VCC/2
VOH –0.1V
0.3V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 4. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
9
PS8526
03/01/01
PI74AVC+16373
2.5V 16-Bit Transparent D-Type Latch
with 3-State Outputs
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Packaging Mechanical - 48-pin TSSOP (A-package)
48
.236
.244
1
6.0
6.2
.488 12.4
.496 12.6
.047
1.20 Max
SEATING PLANE
.004 0.09
.008 0.20
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
.0197
BSC
0.50
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.007
.010
0.17
0.27
.319
BSC
8.1
Packaging Mechanical - 48-pin TVSOP (TSSOP) (K-package)
48
.169
.177
4.30
4.50
.0035
.008
.031
.041
0.80
1.05
1
.378 9.60
.386 9.80
0.09
0.20
0.45 .018
0.75 .030
.252
BSC
6.4
SEATING
PLANE
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
.016
BSC
0.40
.0051
.009
0.13
0.23
.002
.006
0.05
0.15
Max.
.047
1.20
Orde ring Information
De s cription
PI74AVC+16373A
48- pin, 240- mil wide plastic TSSO P
PI74AVC+16373K
48- pin, 173- mil wide plastic TVSOP
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8526
03/01/01