PIC12C67X AND PIC12CE67X EPROM Memory Programming Specification This document includes the programming specifications for the following devices: PDIP PIC12C671 PIC12C672 PIC12CE673 PIC12CE674 1.0 VDD GP5/OSC1/CLKIN GP4/OSC2/AN3/ CLKOUT GP3/MCLR/VPP 1 2 3 4 PIC12C67X PIC12CE67X • • • • Pin Diagram: VSS 8 7 6 5 GP0/AN0 GP1/AN1/VREF GP2/T0CKI/ AN2/INT PROGRAMMING THE PIC12C67X AND PIC12CE67X The PIC12C67X and PIC12CE67X can be programmed using a serial method. In serial mode the PIC12C67X and PIC12CE67X can be programmed while in the users system. This allows for increased design flexibility. 1.1 Hardware Requirements The PIC12C67X and PIC12CE67X requires two programmable power supplies, one for VDD (2.0V to 6.0V recommended) and one for VPP (12V to 14V). Both supplies should have a minimum resolution of 0.25V. 1.2 Programming Mode The programming mode for the PIC12C67X and PIC12CE67X allows programming of user program memory, special locations used for ID, and the configuration word for the PIC12C67X and PIC12CE67X. PIN DESCRIPTIONS (DURING PROGRAMMING): PIC12C671/672 and PIC12CE673/674 During Programming Pin Name Pin Name Pin Type GP1 GP0 GP3/MCLR/VPP VDD VSS CLOCK DATA VPP VDD VSS I I/O P P P Pin Description Clock input Data input/output Programming Power Power Supply Ground Legend: I = Input, O = Output, P = Power 1998 Microchip Technology Inc. DS40175A-page 1 PIC12C67X and PIC12CE67X 2.0 PROGRAM MODE ENTRY 2.1 User Program Memory Map The user memory space extends from 0x0000 to 0x1FFF (8K). Table 2-1 shows actual implementation of program memory in the PIC12C67X family. TABLE 2-1: Device PIC12C671/ PIC12CE673 PIC12C672/ PIC12CE674 IMPLEMENTATION OF PROGRAM MEMORY IN THE PIC12C67X Program Memory Size 0x000 - 0x3FF (1K) 0x000 - 0x7FF (2K) In the configuration memory space, 0x2000-0x20FF are utilized. When in configuration memory, as in the user memory, the 0x2000-0x2XFF segment is repeatedly accessed as the PC exceeds 0x2XFF (see Figure 2-1). A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000 : 0x2003]. Note 1: All other locations in PIC configuration memory are reserved and should not be programmed. Note 2: Due to the secure nature of the on-board EEPROM memory in the PIC12CE673/674, it can be accessed only by the user program. When the PC reaches the last location of the implemented program memory, it will wrap around and address a location within the physically implemented memory (see Figure 2-1). In programming mode the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x1FFF and wrap to 0x000 or 0x2000 to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a '1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode, as described in Section 2.2. The last location of the program memory space holds the factory programmed oscillator calibration value. This location should not be programmed except when blank (a non-blank value should not cause the device to fail a blank check). If blank, the programmer should program it to a RETLW XX statement where "XX" is the calibration value. DS40175A-page 2 1998 Microchip Technology Inc. EPROM Memory Programming Specification FIGURE 2-1: PROGRAM MEMORY MAPPING 0 1FF 3FF 400 7FF 800 2000 ID Location 2001 ID Location 2002 ID Location 2003 ID Location BFF C00 2004 Reserved FFF 1000 2005 Reserved 2006 Reserved 1KW 2KW Implemented Implemented Implemented Reserved Reserved 2007 Configuration Word 1FFF 2000 2008 Reserved Reserved Reserved Reserved 2100 3FFF 1998 Microchip Technology Inc. DS40175A-page 3 PIC12C67X and PIC12CE67X 2.2 Program/Verify Mode have a minimum setup and hold time (see AC/DC specs) with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to have a minimum delay of 1µs between the command and the data. After this delay the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first. Therefore, during a read operation the LSB will be transmitted onto pin GP0 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1µs delay is also specified between consecutive commands. The program/verify mode is entered by holding pins GP1 and GP0 low while raising MCLR pin from VIL to VIHH (high voltage). VDD is then raised from VIL to VIH.Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. GP1 is a Schmitt Trigger input in this mode. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (High impedance inputs). All commands are transmitted LSB first. Data words are also transmitted LSB first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1µs is required between a command and a data word (or another command). Note 1: The MCLR pin must be raised from VIL to VIHH before VDD is applied. This is to ensure that the device does not have the PC incremented while in valid operation range. The commands in Table 1-1. Note 2: Do not power GP2, GP4 or GP5 before VDD is applied. 1.0.1 1.0.1.1 PROGRAM/VERIFY OPERATION that are available are listed LOAD CONFIGURATION After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14-bits a “data word” as described above, to be programmed into the configuration memory. A description of the memory mapping schemes for normal operation and configuration mode The GP1 pin is used as a clock input pin, and the GP0 pin is used for entering command bits and data input/output during serial operation. To input a command, the clock pin (GP1) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin GP0 is required to operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL). TABLE 1-1: COMMAND MAPPING Command Load Configuration Load Data Read Data Increment Address Begin programming End Programming DS40175A-page 4 Mapping (MSB ... LSB) Data 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 1 1 0 0, data(14), 0 0, data(14), 0 0, data(14), 0 1998 Microchip Technology Inc. EPROM Memory Programming Specification FIGURE 1-1: PROGRAM FLOW CHART - PIC12C67X AND PIC12CE67X PROGRAM MEMORY Start Set VPP = VIHH1 Set VDD = VDDP• N=0 No N > 25 Program Cycle Read Data Command Yes Report Programming Failure N=N+1 N = # of Program Cycles No Increment Address Command Data Correct? Yes Program Cycle Apply 3N Additional Program Cycles No Load Data Command All Locations Done? Begin Programming Command Yes Verify all Locations @ VDD MIN.• VPP = VIHH2 Wait 100 µs No Data Correct? Report Verify @ VDD MIN. Error End Programming Command Yes Verify all Locations @ VDD MAX. VPP = VIHH2 No Data Correct? Report Verify @ VDD MAX Error Yes Done • VDDP = VDD range for programming (typically 4.75V - 5.25V). VDD MIN. = Minimum VDD for device operation. VDD MAX. = Maximum VDD for device operation. 1998 Microchip Technology Inc. DS40175A-page 5 PIC12C67X and PIC12CE67X FIGURE 1-2: PROGRAM FLOW CHART - PIC12C67X AND PIC12CE67X CONFIGURATION WORD & ID LOCATIONS Start Set VPP = VIHH1 Load Configuration Command N=0 No Program ID Loc? Yes Read Data Command Program Cycle Increment Address Command N=N+1 N = # of Program Cycles No Data Correct? Yes No Address = 2004 No N > 25 Yes Yes Increment Address Command ID/Configuration Error Apply 3N Program Cycles Program Cycle 100 Cycles Read Data Command Increment Address Command Increment Address Command No Data Correct? Yes Report Program ID/Config. Error No Done DS40175A-page 6 Yes Data Correct? No Data Correct? Set VDD = VVDD DDmin min Read Data Command Set VPP = VIHH2 Yes Set VDD = VVDD max DD max Read Data Command Set VPP = VIHH2 1998 Microchip Technology Inc. EPROM Memory Programming Specification 1.0.1.2 LOAD DATA After receiving this command, the chip will load in a 14-bit “data word” when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 4-1. 1.0.1.3 READ DATA After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The GP0 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 4-2. 1.0.1.4 INCREMENT ADDRESS The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 4-3. 1.0.1.5 BEGIN PROGRAMMING A load command (load configuration or load data) must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100µs programming pulses. A programming pulse is defined as the time between the begin programming command and the end programming command. 1.0.1.6 1.1 Programming Algorithm Requires Variable VDD The PIC12C67X and PIC12CE67X uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good “erase margin”. Verification at VDDmax guarantees good “program margin”. The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP = VCC range required during programming. VDD min. = minimum operating VDD spec for the part. VDD max.= maximum operating VDD spec for the part. Programmers must verify the PIC12C67X and PIC12CE67X at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC12C67X and PIC12CE67X with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as “prototype” or “development” programmer but not a “production” quality programmer. END PROGRAMMING After receiving this command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time. 1998 Microchip Technology Inc. DS40175A-page 7 PIC12C67X and PIC12CE67X 2.0 CONFIGURATION WORD The PIC12C67X and PIC12CE67X family members have several configuration bits. These bits can be programmed (reads '0') or left unprogrammed (reads '1') to select various device configurations. Figure 2-1 provides an overview of configuration bits. FIGURE 2-1: CONFIGURATION WORD Bit Number: 13 12 10 11 9 8 7 6 5 4 CP1 CP0 CP1 CP0 CP1 CP0 MCLRE CP1 CP0 PWRTE 3 2 1 0 WDTE FOSC2 FOSC1 FOSC0 Register: Address CONFIG 2007h bit 13-8, 6-5: CP1:CP0: Code Protection bits (1) (2) 11 = Code protection off 10 = 0400h-07FFh code protected; 01 = 0200h-07FFh code protected; 00 = 0000h-07FFh code protected; bit 7: MCLRE: GP3/MCLR pin function select 1 = GP3/MCLR pin function is MCLR 0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to Vdd bit 4: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 3: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0: FOSC2:FOSC0: Oscillator Selection bits 111 = EXTRC oscillator / CLKOUT function on GP4/OSC2/CLKOUT pin 110 = EXTRC oscillator / GP4 function on GP4/OSC2/CLKOUT pin 101 = INTRC oscillator / CLKOUT function on GP4/OSC2/CLKOUT pin 100 = INTRC oscillator / GP4 function on GP4/OSC2/CLKOUT pin 011 = invalid selection 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Note 3: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 4: 07FFh is always uncodeprotected on the 12C672 and 03FFh is always uncodeprotected on the 12C671. This location contains the RETLW xx calibration instruction for the INTRC. DS40175A-page 8 1998 Microchip Technology Inc. EPROM Memory Programming Specification 3.0 CODE PROTECTION The program code written into the EPROM can be protected by writing to the CP0 & CP1 bits of the configuration word. 3.1 For PIC12C67X and PIC12CE67X devices, once code protection is enabled, all protected segments read '0's (or “garbage values”) and are prevented from further programming. All unprotected segments, including ID and configuration word locations , and calibration word location read normally and can be programmed. Embedding Configuration Word and ID Information in the Hex File To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. TABLE 3-1: CONFIGURATION WORD PIC12C671, PIC12CE673 To code protect: • Protect all memory • Protect 0200h-07FFh • No code protection 00 0000 X00X XXXX 01 0101 X01X XXXX 11 1111 X11X XXXX Program Memory Segment Configuration Word (0x2007) Unprotected memory segment Protected memory segment ID Locations (0x2000 : 0x2003) INTRC Calibration Word (0X3FF) R/W in Protected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read All 0’s, Write Disabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled PIC12C672, PIC12CE674 To code protect: • Protect all memory • Protect 0200h-07FFh • Protect 0400h-07FFh • No code protection 00 01 10 11 Program Memory Segment Configuration Word (0x2007) Unprotected memory segment Protected memory segment ID Locations (0x2000 : 0x2003) INTRC Calibration Word (0X7FF) 1998 Microchip Technology Inc. 0000 0101 1010 1111 X00X X01X X10X X11X XXXX XXXX XXXX XXXX R/W in Protected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read All 0’s, Write Disabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled DS40175A-page 9 PIC12C67X and PIC12CE67X 3.2 Checksum 3.2.1 CHECKSUM CALCULATIONS The least significant 16 bits of this sum is the checksum. Checksum is calculated by reading the contents of the PIC12C67X and PIC12CE67X memory locations and adding the opcodes up to the maximum user addressable location, excluding the oscillator calibration location in the last address, e.g., 0x3FE for the PIC12C671/CE673. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC12C67X and PIC12CE67X devices is shown in Table 3-2. The checksum is calculated by summing the following: • The contents of all program memory locations • The configuration word, appropriately masked • Masked ID locations (when applicable) TABLE 3-2: Device PIC12C671 PIC12CE673 PIC12C672 PIC12CE674 The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. CHECKSUM COMPUTATION Code Protect OFF 1/2 ALL OFF 1/2 3/4 ALL Checksum* SUM[0x000:0x3FE] + CFGW & 0x3FFF SUM[0x000:0x1FF] + CFGW & 0x3FFF + SUM_ID CFGW & 0x3FFF + SUM_ID SUM[0x000:0x7FE] + CFGW & 0x3FFF SUM[0x000:0x3FF] + CFGW & 0x3FFF + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3FFF + SUM_ID CFGW & 0x3FFF + SUM_ID Blank Value Ox25E6 at 0 and max address 3B3F 4E5E 3B4E 373F 5D6E 4A5E 374E 070D 0013 071C 030D 0F23 FC13 031C Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND DS40175A-page 10 1998 Microchip Technology Inc. EPROM Memory Programming Specification 4.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS TABLE 4-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: +10°C ≤ TA ≤ +40°C, unless otherwise stated, (25°C is recommended) Operating Voltage: 4.5V ≤ VDD ≤ 5.5V, unless otherwise stated. Parameter No. Sym. Characteristic Min. Typ. Max. Units 4.75 5.0 5.25 V 20 mA Conditions General PD1 VDDP Supply voltage during programming PD2 IDDP PD3 VDDV Supply voltage during verify VDDmin VDDmax V Note 1 PD4 VIHH1 Voltage on MCLR/VPP during programming 12.75 13.25 V Note 2 PD5 VIHH2 Voltage on MCLR/VPP during verify VDD + 4.0 13.5 Supply current (from VDD) during programming Programming supply current (from VPP) 50 mA PD6 IPP PD9 VIH1 (GP0, GP1) input high level 0.8 VDD V Schmitt Trigger input PD8 VIL1 (GP0, GP1) input low level 0.2 VDD V Schmitt Trigger input Serial Program Verify P1 P2 TR MCLR/VPP rise time (VSS to VIHH) for test mode entry Tf MCLR Fall time 8.0 µs 8.0 µs P3 Tset1 Data in setup time before clock ↓ 100 P4 Thld1 Data in hold time after clock ↓ 100 ns P5 Tdly1 Data input not driven to next clock input (delay required between command/data or command/command) 1.0 µs P6 Tdly2 Delay between clock ↓ to clock ↑ of next command or data 1.0 µs P7 Tdly3 Clock ↑ to data out valid (during read data) 200 ns ns P8 Thld0 Hold time after VDD↑ 2 µs P9 TPPDP Hold time after VPP↑ 5 µs Note 1: Program must be verified at the minimum and maximum VDD limits for the part. Note 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode. 1998 Microchip Technology Inc. DS40175A-page 11 EPROM Memory Programming Specification FIGURE 4-1: LOAD DATA COMMAND (PROGRAM/VERIFY) VDD P9 VIHH MCLR/VPP 100ns P8 1 P6 3 2 4 5 6 GP1 (CLOCK) GP0 (DATA) 0 100ns 0 1 0 0 1 1µs min. 2 4 5 15 0 0 0 P5 P3 P3 1µs min. P4 P4 } } } } 100ns min. 100ns min. Program/Verify Mode Reset FIGURE 4-2: 3 READ DATA COMMAND (PROGRAM/VERIFY) VDD P9 VIHH MCLR/VPP 100ns P8 1 P6 2 3 4 5 6 1µs min. GP1 (CLOCK) GP0 (DATA) 0 100ns 1 0 0 0 1 2 3 4 5 15 P7 0 P5 P4 1µs min. P3 } } 100ns min. RB7 input RB7 = output Program/Verify Mode Reset FIGURE 4-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) VDD P9 VIHH MCLR/VPP 1 2 3 4 5 P6 1µs min. 6 Next Command 1 2 GP1 (CLOCK) GP0 (DATA) 0 1 1 0 0 0 0 0 P5 P3 P4 1µs min. } } 100ns min Program/Verify Mode Reset 1998 Microchip Technology Inc. DS40175A-page 12 EPROM Memory Programming Specification NOTES: 1998 Microchip Technology Inc. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 Microchip Technology Taiwan Singapore Branch 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Toronto Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253 All rights reserved. © 1998, Microchip Technology Incorporated, USA. 2/98 1/13/98 Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicro™ 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO). Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS40175A-page 14 1998 Microchip Technology Inc.