PM 11 :43 :05 PM5365 02 TM nT hu rsd ay ,1 TEMAP 9S ep tem be r, 20 TEMAP Errata Do wn loa de db yV inv ef uo fo liv ett io VT/TU Mapper and M13 Multiplexer Proprietary and Confidential Released Issue 3: August, 2002 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 PM TEMAP Production Release Errata Released :05 Legal Information :43 Copyright 11 © 2002 PMC-Sierra, Inc. r, 20 02 The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In any event, you cannot reproduce any part of this document, in any form, without the express written consent of PMC-Sierra, Inc. tem be PMC-2001480 (R3) ep Disclaimer nT hu rsd ay ,1 9S None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. fo liv ett io In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. ef uo Trademarks inv TEMAP, SBI, and PMC-Sierra are trademarks of PMC-Sierra, Inc. db yV Patents Do wn loa de The technology discussed is protected by one or more Patents. Relevant patent applications and other patents may also exist. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 2 PM TEMAP Production Release Errata Released :05 Contacting PMC-Sierra 11 :43 PMC-Sierra 8555 Baxter Place Burnaby, BC Canada V5A 4V7 20 02 Tel: +1.604.415.6000 Fax: +1.604.415.6204 9S ep tem be r, Document Information: [email protected] Corporate Information: [email protected] Technical Support: [email protected] Web Site: http://www.pmc-sierra.com ay ,1 Revision History Issue Date Details of Change 3 August 2002 Notification of additional information and errors to TEMAP Data Sheet Issue R3, TEMAP Register Description R2 and TEMAP Programmer’s Reference Guide R3. nT hu rsd Issue No. Added items 2.2 to 2.5, 3.7 to 3.20. October 1, 2001 Updated to reflect new PM5365 TEMAP Datasheet issued August 2001 (PMC-1991148 r3) and the PM5365 TEMAP Register Description issued July 2001 (PMC-1990682 r2). 1 July 12, 2001 This document is a notice of additional information and error corrections to be inserted into the PM5365 TEMAP Datasheet, document number PMC01991148, Issued February 2000 and the PM5365 TEMAP Register Description, document number PMC-1990682, Issued March 2000. Do wn loa de db yV inv ef uo fo liv ett io 2 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 3 PM TEMAP Production Release Errata Released :05 Table of Contents :43 Legal Information ................................................................................................................ 2 Contacting PMC-Sierra ....................................................................................................... 3 02 Device Identification............................................................................................ 6 1.2 References ......................................................................................................... 6 r, 20 1.1 tem be Device Functional Deficiency List ............................................................................... 7 VT-AIS Tributary Corruption................................................................................ 7 2.2 DS3 PRGD block limits useable repeating patterns in unchannelized M23 mode ............................................................................................................................ 7 Workaround............................................................................................ 8 2.2.3 Performance with Workaround .............................................................. 8 2.2.4 Performance without Workaround ......................................................... 9 ay rsd hu Description ............................................................................................. 9 2.3.2 Workaround............................................................................................ 9 2.3.3 Performance with Workaround .............................................................. 9 2.3.4 Performance without Workaround ......................................................... 9 fo liv ett io 2.3.1 Incorrect Link Rate Octet generated when demapping DS3 from SONET ...... 10 2.4.1 Description ........................................................................................... 10 2.4.2 Workaround.......................................................................................... 10 2.4.3 Performance with Workaround ............................................................ 10 db Performance without Workaround ....................................................... 10 TEMAP Not Recommended for E1 Applications Requiring G.783 Jitter Compliance .......................................................................................................................... 10 Do wn loa de 3 nT Demapping DS3 when CLK52M = 51.84 MHz is not recommended ................. 9 2.4.4 2.5 9S 2.2.2 ,1 Description ............................................................................................. 7 uo 2.4 2.2.1 ef 2.3 ep 2.1 inv 2 Introduction.................................................................................................................. 6 yV 1 11 Table of Contents ................................................................................................................ 4 Documentation Deficiency List .................................................................................. 12 3.1 Duplication of Ground Pin Descriptions............................................................ 12 3.2 Connecting to the Telecom ADD bus via an External MUX.............................. 12 3.3 Telecom ADD Bus Parity Generation................................................................ 12 3.4 Telecom DROP Bus Parity Detection ............................................................... 12 3.5 AIS Insertion in DS3 Diagnostic Loopback....................................................... 13 3.6 Path Signal Label Mismatch State.................................................................... 13 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 4 TEMAP Production Release Errata Released Transmultiplexing Mode Clarification................................................................ 14 3.8 CENT bit description of TJAT and RJAT Configuration registers are incorrect 15 3.9 M13 TJAT and RJAT settings incorrect in Programmer’s Guide ...................... 15 :43 :05 PM 3.7 3.10 IILPU max spec limit has been revised ............................................................ 15 11 3.11 Tolerance of TICLK not stated in pin description .............................................. 16 02 3.12 CLK52M Clarification ........................................................................................ 16 20 3.13 Recommended RTDM Leak Rate incorrect...................................................... 16 tem be r, 3.14 Behavior of FIFO status handling needs clarification ....................................... 16 3.15 RJAT SYNC bit description in EXSBI CLK_MODE field clarified ..................... 17 3.16 Miscellaneous Pins Incorrect............................................................................ 17 ep 3.17 Missing Diagrams ............................................................................................. 18 9S 3.18 Revision ID Bits Section clarification. ............................................................... 23 ,1 3.19 Byte Deletion/Insertion in VT/TU Mapping Mode ............................................. 23 Do wn loa de db yV inv ef uo fo liv ett io nT hu rsd ay Notes ................................................................................................................................. 24 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 5 Introduction :05 1 PM TEMAP Production Release Errata Released :43 In this document: Section 2 lists the known functional errata for the Production Released Version of the PM5365 TEMAP. · Section 3 lists documentation errors found in the PM5365 TEMAP Datasheet issued August 2001 (PMC-1991148, Issue 3) and the PM5365 TEMAP Register Description issued July 2001 (PMC-1990682, Issue 2). Device Identification tem be 1.1 r, 20 02 11 · ,1 9S ep The information contained in Section 2 relates to the Production Released version of the PM5365 TEMAP device only. This version is identified by the letter E at the end of the wafer batch code, which is the device revision code, and the designation –PI at the end of the part number instead of the designation –PI-P. rsd ay Register 0002H: Revision/Global PMON Update identifies the Production Release revision of the PM5365 TEMAP using ID[3:0]=0101. io nT hu Note: This errata only applies to issues specific to the production released PM5365-PI TEMAP device. It does not apply to any of the prototype TEMAP devices. ett Figure 1 PM5365 Branding Diagram liv Ball A1 Index Marks fo uo ef yV inv Do wn loa de db Country of Origin 1.2 PMC Logo TEMAP Logo TM TEMAP PM5365-PI C E Myyww Philippines Part Number Wafer Batch Code Assembly Date Code References · · Issue 3 of the PM5365 TEMAP Datasheet (PMC-1991148). Issue 2 of the PM5365 TEMAP Register Description (PMC-1990682). Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 6 Device Functional Deficiency List :05 2 PM TEMAP Production Release Errata Released 11 :43 This section lists the known functional deficiencies for the Production Released version of the PM5365 TEMAP as of the publication date of this document. VT-AIS Tributary Corruption 20 2.1 02 Please report any functional deficiencies not covered in this errata to PMC-Sierra. tem be r, An issue in the TEMUX demapper results in the VT-AIS causing corruption to the previous tributary of SPE#3 only. DS3 PRGD block limits useable repeating patterns in unchannelized M23 mode ay ,1 2.2 9S ep To circumvent this issue, apply the software workaround outlined in Section 16 of the Programmer’s Reference Guide (PMC-1991268). rsd 2.2.1 Description liv 84 bits 84 bits 84 bits 84 bits F2 C2 F3 C3 F4 C1 F2 C2 F3 C3 F4 C1 C1 F2 C2 F3 C3 F4 F1 C1 F2 C2 F3 C3 F4 F1 C1 F2 C2 F3 C3 F4 F1 C1 F2 C2 F3 C3 F4 uo F1 F1 inv F1 F2 C2 F3 C3 F4 Do wn loa de db M-subframe 7 M3 84 bits C1 fo F1 yV M-subframe 4 P 2 M-subframe 5 M1 M-subframe 6 M2 84 bits ef M-subframe 1 X 1 M-subframe 2 X 2 M-subframe 3 P 1 84 bits ett 84 bits io nT hu As described in the TEMAP Data Sheet, Section 12.1: DS3 Framing Format, the TEMAP device provides support for both the C-bit parity and M23 DS3 framing formats. The DS3 frame format is shown in Figure 17 of the Data Sheet (copied below): The C-bit Parity ID bit is the first C-bit (C1) of the M-subframe 1. In the receive direction, the CBITV register bit in the DS3 FRMR Status register is used to report the state of this C-bit Parity ID. If the ID bit is 1, the DS3 frame received is assumed to be C-bit parity. If the C-bit Parity ID is 0 or toggling, the DS3 signal stream received is assumed to be M23. Unchannelized repeating patterns are regenerated each time the PRGD Pattern Insertion Register #4 is written to (Register 103BH). In M23 mode, the DS3 PRGD always sets all C-bits to the same value based on the last transmitted bit. For an all-1’s pattern, all C-bits will be 1. Similarly for an all-0’s pattern, all C-bits will be 0. For an alternating 10101010 pattern for instance, there is a 50/50 chance of all C-bits being 1. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 7 TEMAP Production Release Errata Released 11 :43 :05 PM An issue arises when attempting to generate an unchannelized all-1’s M23 pattern. Recall that an M23 signal stream requires the C-bit Parity ID to be 0 or toggling. However, the DS3 PRGD will set all C-bits (and hence the C-Bit Parity ID) to 1 when generating an all-1’s pattern. The receiver will therefore interpret the DS3 frame to be C-bit parity rather than the correct M23 format. As a result, a frame mismatch is declared if an all-1’s is generated in M23 mode. tem be r, 20 02 Similarly, an alternating 10101010 M23 pattern has a 50/50 chance of being misinterpreted as a C-bit parity DS3 stream while in unchannelized DS3. For patterns containing one or more 0’s, the occurrence of this problem is related to the 1’s density of the pattern. An example is a 31ones, 1-zero pattern in M23 mode. On average, this pattern will work without frame mismatch one every 32 tries, as there is a 1/32 chance of C-bit parity ID being 0. ep In C-bit parity mode, there are no problems passing all-1’s because the ID bit is always overwritten with a 1. 9S 2.2.2 Workaround rsd ay ,1 There is no way to generate an all-1s pattern while in unchannelized M23 mode without seeing frame mismatch errors. Because the DS3 PRGD block limitation applies to unchannelized DS3 only, utilizing C-bit parity mode (instead of M23) allows the generation of an all-1’s pattern. io nT hu In the event that unchannelized M23 mode must be used, several other patterns can be used without declaring DS3 frame mismatch. For patterns containing one or more 0’s, the occurrence of this mistaken M23 signal for C-bit parity is related to the 1’s density of the pattern. ett The following algorithm can be used to generate patterns other than all-1’s in M23 mode: Write to PRGD Pattern Insertion Register #4 (Register 103BH) to generate unchannelized repeating patterns. · At the receiver, check the framer for a DS3 frame mismatch. If using a loopback or another TEMAP, the DS3 framing circuitry of the TEMAP reports the frame mismatch using DS3 FRMR status bit CBITV. · If frame mismatch has occurred, repeat. Else, transmitted pattern is correct. db yV inv ef uo fo liv · Do wn loa de An all-0’s pattern can always be transmitted correctly while the TEMAP is in unchannelized M23 mode. 2.2.3 Performance with Workaround There is no workaround to implement the generation of an all-1s pattern while in unchannelized M23 mode. Using C-bit parity DS3 framing format is recommended to generate all-1’s. The TEMAP device will operate normally in DS3 testing scenarios with the suggested workaround in place for M23 mode. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 8 2.2.4 Performance without Workaround Demapping DS3 when CLK52M = 51.84 MHz is not recommended 11 2.3 :43 :05 DS3 Frame Mismatch will be declared when attempting to generate all-1’s pattern in unchannelized M23 mode. PM TEMAP Production Release Errata Released 20 02 2.3.1 Description tem be r, In the TEMAP Data Sheet, there is a choice between two clock frequencies for CLK52M input (Pin P3): ep " The 52 MHz clock reference is used to generate a gapped DS3 clock when demapping a DS3 from the SONET stream and also to generate a gapped DS3 clock when receiving a DS3 from the SBI bus interface. This clock has two nominal values. ,1 9S The first is a nominal 51.84 MHz 50% duty cycle clock. The second is a nominal 44.928 MHz 50% duty cycle clock. rsd ay When this clock is not used this input must be connected to ground." nT hu Repetitive data corruption with demapped DS3 may occur in systems using the 51.84 MHz clock. It has been confirmed that this is not an issue if the alternate clock frequency, 44.928 MHz, is used. uo fo liv ett io When 51.84 MHz is synchronized to LREFCLK, errors still occur as long as the incoming DS3 ppm offset is greater than the relative offset of the 51.84 MHz. The data corruption is theoretically possible with or without incoming STS level pointer movements. At this time however, no errors have been observed in the absence of STS level pointer movements. Also, standard test equipment used as the mapped DS3 source has yet to produce the error condition. Only a TEMAP device mapping the DS3 causes the errors. inv ef 2.3.2 Workaround Do wn loa de db yV When configured to demap DS3 payloads from SONET STS1/SDH AU3, the CLK52M input at 44.928 MHz would avoid this possible data corruption to the DS3 stream. Thus, the FASTCLKFREQ bit of Register 1209H must be cleared to logic 0. Using the 44.928 MHz clock has always been a fully supported mode of the TEMAP. 2.3.3 Performance with Workaround If the 44.928 MHz clock frequency is used for CLK52M while demapping DS3s from SONET STS1/SDH AU3, the risk of data corruption in this mode no longer exists. PMC-Sierra highly recommends using this clock frequency when demapping DS3s in new TEMAP designs. 2.3.4 Performance without Workaround When demapping DS3s from SONET/SDH payloads, if the CLK52M input is set to 51.84 MHz, there is a risk of data corruption. PMC-Sierra highly recommends using 44.928 MHz crystals for new designs. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 9 TEMAP Production Release Errata Released PM Incorrect Link Rate Octet generated when demapping DS3 from SONET :05 2.4 :43 2.4.1 Description 20 02 11 When the TEMAP device is in DS3 framer-only mode, the linkrate clock rate field over the SBI bus tolerates approximately 4 UI of jitter in a 500uS (2kHz) period. When demapping a DS3 from SONET, gapping the CLK52M reference clock generates the serial DS3 clock. The gapping procedure utilizes FIFO depth to control the gapping algorithm. 9S ep tem be r, The gapping algorithm used by the DS3 demapper exceeds the jitter tolerance of the SBI linkrate. Data taken by the link layer SBI devices via their EXSBI FIFO is derived from these faulty linkrate values. These values no longer match the actual data rate. With the clock rate octet enabled in layer 2 SBI devices, the DS3 clock could only be varied by a few ppm before the EXSBI FIFO underflows or overflows. As a result, data corruption can occur. rsd ay ,1 Therefore, when demapping DS3s from SONET in the TEMAP, the layer 2 SBI devices cannot rely upon link rate octet to regenerate clocking. Rather, the DS3 serial clocks need to be routed around the SBI bus. hu 2.4.2 Workaround ett io nT In data applications involving FREEDM packet processing and IMA ATM, the FIFO method is used to pass data across the SBI bus when demapping DS3 from SONET. Hence, an incorrect link rate octet does not affect these applications. uo fo liv However, for AAL1 circuit emulation (CES) applications that demap DS3 from SONET, the serial DS3 clocks (generated by gapping CLK52M) need to be routed around the SBI bus. This is normally done for serial DS3 but in addition, a DS3 JAT is required for demapping applications. ef Refer to PMC-1990887 “AAL1gator-32 CES Reference Design”, Issue 5 for details. yV inv 2.4.3 Performance with Workaround db If the serial DS3 clocks are routed around the SBI bus in DS3 demapping CES applications, there will be no excess jitter introduced. Do wn loa de 2.4.4 Performance without Workaround Data corruption may occur when demapping DS3s from SONET in AAL1 circuit emulation. 2.5 TEMAP Not Recommended for E1 Applications Requiring G.783 Jitter Compliance TEMAP does not meet G.783 Jitter specification for demapping E1 from SDH in the presence of pointer movements. Specification allows 0.4 UIpp jitter between 20 Hz and 100 kHz and 0.075 UIpp between 18 kHz and 100 kHz. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 10 TEMAP Production Release Errata Released :43 :05 PM Preliminary testing has shown that values greater than 0.4 UI pp and 0.075 UI pp can be measured for their respective frequency bands when using either the PM4314 QDSX connected to the TEMAP’s clock and data interface or the PM4318 OCTLIU connected to the TEMAP’s SBI bus. 11 At no time are there any data corruption issues. Do wn loa de db yV inv ef uo fo liv ett io nT hu rsd ay ,1 9S ep tem be r, 20 02 If customer designs require these specifications to be met, consideration should be given to migrating these designs to PMC-Sierra’s PM5366, TEMAP-84. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 11 Documentation Deficiency List :05 3 PM TEMAP Production Release Errata Released 11 :43 This section of the document is a notification of additional information and known documentation deficiencies for Issue 3 of the PM5365 TEMAP Datasheet and Issue 2 of the PM5365 TEMAP Register Description, as of the publication date of this document. Duplication of Ground Pin Descriptions r, 3.1 20 02 Please report any documentation deficiencies not covered in this errata to PMC-Sierra. Connecting to the Telecom ADD bus via an External MUX ,1 3.2 9S ep tem be The description of ground pins N3, Y12, L20 and B12 has been duplicated in two rows of the pin description section, pins VSSQ[1:4] and VSS3.3[19:22]. These pins should only be described in the VSS3.3 row. The VSSQ row should be eliminated. In any event these pins should be connected to GND as described. ett Telecom ADD Bus Parity Generation liv 3.3 io nT hu rsd ay The pin description for LAC1J1V1 may need clarification. When connecting the TEMAP to the TelecomBus via an external MUX (instead of simply tri-stating the bus), the LAC1J1V1 signal should not be muxed. This means that when there are three TEMAPs connected to a Spectra’s TelecomBus through the MUX, the LAC1J1V1 signal from only one of the three TEMAPs should be connected to the SPECTRA. The other two LAC1J1V1 signals should remain unconnected. All TEMAPs must have the LOCK0 bit in registers 1202H and 15E5H set the same. Telecom DROP Bus Parity Detection yV 3.4 inv ef uo fo The TEMAP device cannot generate parity on the Telecom ADD bus when LAC1J1V1 is set to participate in the egress parity generation. Parity generation only helps check integrity of the bus connections and has no effect on the data path or with control of the device. If egress parity needs to be generated, LAC1J1V1 should not be used. Do wn loa de db The TEMAP device can correctly detect parity on the Telecom DROP bus when LDC1J1V1 is set to participate in the ingress parity detection. The Register Description documentation is erroneously missing this optionally selectable feature. Accordingly, Register 1201H of the Register Description document should be amended as follows: Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 12 PM TEMAP Production Release Errata Released Type Function Default Bit 7 R/W LDPE 0 Bit 6 R/W ITMFEN 0 Bit 5 R/W IVTPPBYP 0 Bit 4 R/W ITSEN 0 Bit 3 R/W INCLDPL 0 Bit 2 R/W INCLDC1J1V1 0 LDOP 0 R/W ICONCAT 0 11 02 20 r, R/W Bit 0 tem be Bit 1 :43 Bit :05 Register 1201H: SONET/SDH Master Ingress Configuration 9S ep INCLDC1J1V1: hu AIS Insertion in DS3 Diagnostic Loopback nT 3.5 rsd ay ,1 The INCLDC1J1V1 bit controls whether the LDC1J1V1 input signal participates in the incoming parity calculations. When INCLDC1J1V1 is set high, the parity signal set includes the LDC1J1V1 input. When INCLDC1J1V1 is set low, parity is calculated without regard to the state of LDC1J1V1. Selection of odd or even parity is controlled by the LDOP bit. Path Signal Label Mismatch State fo 3.6 liv ett io In the datasheet, Figure 25: DS3 Diagnostic Loopback Diagram states that AIS can optionally be inserted into the transmit datapath when a DS3 is in diagnostic loopback. This is incorrect. AIS cannot be inserted in the transmit path when in DS3 diagnostic loopback mode. inv ef uo In the datasheet, Table 2: Path Signal Label Mismatch State is incorrect. It incorrectly references PDI code. - Path Signal Label Mismatch State db Table 2 yV The table should read as follows: Accepted PSL PSLM State 000 000 MATCH 000 001 MISMATCH 000 XXX ¹ 000 MISMATCH 001 000 MISMATCH 001 001 MATCH 001 XXX ¹ 001 MATCH Do wn loa de Expected PSL Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 13 Accepted PSL PSLM State XXX ¹ 000, 001 000 MISMATCH XXX ¹ 000, 001 001 MATCH XXX ¹ 000, 001 XXX MATCH XXX ¹ 000, 001 YYY MISMATCH Transmultiplexing Mode Clarification tem be 3.7 r, 20 02 11 :43 :05 Expected PSL PM TEMAP Production Release Errata Released 9S ep Transmultiplexing mode (“transmux”) is not adequately described in the current TEMAP datasheet. This mode enables the exchange of 1.544 Mbps tributaries between SONET/SDH TelecomBus and DS3 line interface. ay ,1 The following excerpt should be added to Section 9: Functional Description: io nT hu rsd Transmultiplexing (“transmux”) is the operating mode that enables 1.544 Mbps clearchannel tributaries to be exchanged between the SONET/SDH Telecom Bus and the DS3 line interface. It is enabled by setting the TEMAP Configuration register’s OPMODE[1:0] bits to 10 and its LINEOPT [1:0] bits to 00. The system interface is unused in this mode. uo fo liv ett The TEMAP will receive a channelized DS3 stream from the serial DS3 interface. It will frame up to the DS3 and de-multiplex the individual 1.544 Mbps tributaries. The tributaries are jitter attenuated, bit asynchronously mapped into VT1.5/TU11s and presented on the Telecom Add bus. yV inv ef In the reverse direction, VT1.5/TU11s are bit asynchronously de-mapped from the Telecom Drop bus. The 1.544 Mbps tributaries are jitter attenuated and multiplexed into a DS3, which is presented on the serial DS3 interface. Do wn loa de db Performance monitoring of T1 framing status and errors can be performed on the tributaries. On a per-tributary basis, the TXPMON context bit programmed through Register 000H+80H*N: T1/E1 Master Configuration register selects either the SONET/SDH mapper transmit or DS3 transmit T1 tributary for performance monitoring. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 14 CENT bit description of TJAT and RJAT Configuration registers are incorrect :43 :05 3.8 PM TEMAP Production Release Errata Released 02 11 The following text should be ignored from the CENT bit description of the T1/E1 TJAT and RJAT Configuration Registers, Register 0017H + 80H*N and Register 0013H + 80H*N respectively: 20 “It is recommended to set this bit to 1”. ep M13 TJAT and RJAT settings incorrect in Programmer’s Guide 9S 3.9 tem be r, For the recommended setting of the TJAT and RJAT Configuration Register bits, refer to Section 16 of the Programmer’s Guide for VT/TU mapping modes and to Errata item 3.9, below, for the DS3 M13 operational modes. ay ,1 The TJAT and RJAT Configuration Register recommendations are incorrect in the TEMAP Programmer’s Guide for channelized DS3 applications. nT hu rsd Sections 6.2.1 (T1) and 7.1.1 (E1) state the TJAT and RJAT manual centering procedures setting Register 0017H + 80H*N TJAT Configuration and Register 0013H + 80H*N RJAT Configuration to values of 0x20. fo liv ett io Neither centering procedure should be followed for channelized DS3 T1 or E1 applications. Rather, these two registers should be programmed with values of 0x31 upon initialization for all modes. The only exception is where PM73122 AAL1gator-32 is connected to the TEMAP’s system side SBI bus and operating in SRTS mode. In this particular application, the RJAT Configuration Register 0013H + 80H*N must be set to 0x23. inv ef uo The TEMAP Programmers Guide’s TU mapping mode recommendations for TJAT and RJAT Configuration registers in Section 16 are correct and should be followed. This includes the manual centering routine for the TJAT and RJAT in Section 16.1.1. yV 3.10 IILPU max spec limit has been revised Do wn loa de db In Table 33, the D.C. Characteristics table, the input low current parameter, IILPU maximum has been changed from +100 mA to +150 mA. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 15 PM TEMAP Production Release Errata Released :05 3.11 Tolerance of TICLK not stated in pin description :43 The following Text should be added to the TICLK pin description: 02 11 TICLK input pin AA6: - This input requires a 44.736 MHz +/- 20ppm clock source. 20 3.12 CLK52M Clarification tem be r, In Section 9.19.3 DS3 Desynchronizer of the TEMAP Data Sheet, the following statement is misleading: ,1 9S ep “The Desynchronizer monitors the Elastic Store level to control the de-stuffing algorithm to avoid overflow and underflow conditions. The Desynchronizer assumes either a 51.84 MHz clock (provided internally) or a 44.928 MHz clock (provided via input CLK52M).” rsd ay The 51.84MHz clock option is not provided internally within the TEMAP device. Hence, DS3 signals cannot be transported without connecting CLK52M. hu Refer also to Errata Section 2.3 for CLK52M discussion when demapping DS3s. io nT 3.13 Recommended RTDM Leak Rate incorrect liv ett It was incorrectly recommended in the TEMAP Programmer’s Guide, Section 16.4 b) “Register 12E0H: RTDM Pointer Justification Rate Control” that E1RATE[1:0] be set to 10. uo fo The recommended settings should read E1RATE[1:0]=00, the default and slowest leak rate settings to ensure no degradation of jitter performance. inv ef 3.14 Behavior of FIFO status handling needs clarification Do wn loa de db yV In the extract and insert SBI (EXSBI, INSBI) FIFOs, the TEMAP has a priority mechanism for reporting underruns and overruns on certain tributaries. In general, lower-numbered tributaries can seemingly block the reporting of FIFO events on higher-numbered tributaries. Consider an example where all tributaries underrun continuously. After reading status register errors for the first few tributaries, it may be the case that new underrun events are registered. In this case, errors will appear again for lower number tributaries before errors for higher number tributaries can be read. In general, errors for a particular tributary cannot be read from the status register if an error on any lower numbered tributary has not been read. This behavior will only become evident in the rare event that several tributaries are simultaneously exhibiting FIFO errors. Note that this priority mechanism does not inhibit normal behavior of the TEMAP device. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 16 TEMAP Production Release Errata Released PM 3.15 RJAT SYNC bit description in EXSBI CLK_MODE field clarified :43 :05 In Register 1716H: EXSBI Tributary Control Indirect Access Data, the CLK_MODE[1:0] bit description includes the following statement: 02 11 "When using the phase field of the Link Rate octet, the SYNC bit in the RJAT configuration register needs to be set." tem be r, 20 For clarification, the TEMAP RJAT is not usually connected to the TEMAP EXSBI. Hence, this comment about the “phase field” is more relevant to the device that uses this information, PM73122 AAL1gator-32’s EXSBI, rather than TEMAP. ep 3.16 Miscellaneous Pins Incorrect Do wn loa de db yV inv ef uo fo liv ett io nT hu rsd ay ,1 9S In Section 8, the Pin Description section, of the Datasheet, Pin AA22 was wrapped and read AA2 and 2. The Miscellaneous Pins table should read: Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 17 PM TEMAP Production Release Errata Released ett io nT hu rsd ay ,1 9S ep tem be r, 20 02 11 :43 No Connect. These pins are not connected to any internal logic. liv A1 B2 AA2 V3 W20 AA22 Y21 W21 K22 K21 Y1 W1 F4 G1 V20 Y22 K20 J19 W4 V1 E1 U19 R22 J22 J20 K1 K2 T4 A1 B2 uo fo NO CONNECT :05 Miscellaneous Pins inv ef 3.17 Missing Diagrams Do wn loa de db yV Several diagrams were omitted from the TEMAP Data Sheet. These diagrams are reproduced here with the associated Data Sheet Figure Number. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 18 TEMAP Production Release Errata Released 11 :43 :05 40 PM Figure 11 DJAT Minimum Jitter Tolerance vs. XCLK Accuracy E1 Modes 20 34 29 250 0 32 300 354 Hz 100 ± ppm hu Figure 12 DJAT Jitter Transfer T1 Modes io nT 0 uo fo liv 62411 min -20 62411 max 43802 max DJAT response inv ef -30 Do wn loa de db yV -40 -50 ett -10 Jitter Gain (dB) rsd ay XCLK Accuracy 200 9S 25 100 ep tem be r, 30 ,1 Max frequency offset (PLL Ref to XCLK) 02 35 DJAT Minimum Jitter Tolerance UI pp 36 1 10 6.6 100 1k Jitter Frequency, Hz Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 10k 19 TEMAP Production Release Errata Released hu rsd ay ,1 9S ep tem be r, 20 02 11 :43 :05 PM Figure 13 DJAT Jitter Transfer E1 Modes F1 C1 84 bits 84 bits 84 bits 84 bits C2 F3 C3 F4 F2 C2 F3 C3 F4 C1 F2 C2 F3 C3 F4 C1 F2 C2 F3 C3 F4 F1 C1 F2 C2 F3 C3 F4 F1 C1 F2 C2 F3 C3 F4 F1 fo ef F1 C1 F2 C2 F3 C3 F4 Do wn loa de db yV inv M-subframe 6 M2 M-subframe 7 M3 84 bits F2 ett C1 liv F1 F1 M-subframe 4 P 2 M-subframe 5 M1 84 bits uo M-subframe 1 X 1 M-subframe 2 X 2 M-subframe 3 P 1 84 bits io 84 bits nT Figure 17 DS3 Frame Structure Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 20 TEMAP Production Release Errata Released :05 PM Figure 18 FER Count vs. BER (E1 mode) :43 8 6 11 Average Count Over Many 1 Second Intervals 7 02 5 20 4 r, 3 2 tem be Bit Error Rate (x 10 -3 ) 9 1 50 100 150 200 250 9S 0 ep 0 hu rsd ay Figure 25 DS3 Diagnostic Loopback Diagram ,1 Framing Bit Error Count Per Second RCLK RPOS/ RDAT RNEG/ RLCV MX23 uo fo liv ett io nT DS3 FRMR UNI Do wn loa de db Optional AIS Insertion DS3 TRAN yV inv ef TCLK TPOS/ TDAT TNEG/ TMFP F MX12 #7 F R MX12 #6 RM F R MX12 #5 M R F MR MX12 #4 R F MR MX12 #3 RR F M MX12 #2 R F R MX12 #1 RM MR R Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 21 TEMAP Production Release Errata Released :05 PM Figure 26 DS3 Line Loopback Diagram F MX12 #7 F R MX12 #6 RM F R MX12 #5 M R F MR MX12 #4 R F MR MX12 #3 R F MR MX12 #2 F RR MX12 #1 RM MR R :43 RCLK RPOS/ RDAT RNEG/ RLCV TCLK TPOS/ TDAT TNEG/ TMFP tem be r, MX23 20 02 11 DS3 FRMR ,1 9S ep DS3 TRAN rsd ay Figure 30 PRGD Pattern Generator 2 3 32 ef uo fo 1 liv ett io nT hu LENGTH PS TAP db yV inv Figure 44 RSTB Timing tV RSTB Do wn loa de RSTB Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 22 TEMAP Production Release Errata Released PM Figure 65 XCLK Input Timing :43 :05 t H XCLK 11 XCLK 20 02 t XCLK t L XCLK tem be r, 3.18 Revision ID Bits Section clarification. ep The TEMAP Revision ID is located in ID[3:0] bits of Register 0x02. In the TEMAP, this field will have a value of “0101”. ,1 9S (Issue 1 of this document, PMC-2001480, TEMAP Datasheet Errata, Issue 1, Section 7, incorrectly stated that TYPE[3:0] contained the Revision ID). rsd ay 3.19 Byte Deletion/Insertion in VT/TU Mapping Mode inv ef uo fo liv ett io nT hu While rare, it is possible for jitter on XCLK or the selected T1/ E1 transmit clock to cause an overflow or underflow in the transmit mapper (TTMP) FIFO. The T1/E1 transmit timing can be sourced from the two clock master sources, the CTCLK input or the recovered T1/E1 clock, or from the two clock slave sources, an ECLK[x] input or the SBI tributary rate received on the SBI add bus. By design, underflow or overflow will result in the loss of a byte of data. The initialization procedure shown in Section 16 of the Programmer’s Reference Guide will push the FIFO closer to the center such that it can withstand more jitter from these clocks to reduce any impact on the datapath. If the FIFO is close to an underflow or overflow condition and jitter does push it over or under, the FIFO will insert or delete a byte of data, pushing itself away from these states and giving itself at least another 8 UI of margin against future jitter events on XCLK or the selected T1/E1 transmit clock. Do wn loa de db yV You should use the initialization sequence shown in Section 16 of the Programmer’s Reference Guide (PMC-1991268). Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 23 PM TEMAP Production Release Errata Released Do wn loa de db yV inv ef uo fo liv ett io nT hu rsd ay ,1 9S ep tem be r, 20 02 11 :43 :05 Notes Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2001480, Issue 3 24