RENESAS R5F213M8KNXXXNP

Datasheet
R8C/3MK Group
RENESAS MCU
1.
R01DS0038EJ0100
Rev.1.00
Feb 25, 2011
Overview
1.1
Features
The R8C/3MK Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions
for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high
speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/3MK Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1
Applications
Peripherals (USB applicable), audio components, cameras, televisions, household appliances, office equipment,
communication devices, mobile devices, industrial equipment, and other applications.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 1 of 56
R8C/3MK Group
1.1.2
1. Overview
Specifications
Tables 1.1 and 1.2 outline the Specifications for R8C/3MK Group.
Table 1.1
Item
CPU
Specifications for R8C/3MK Group (1)
Function
Central processing
unit
Memory
ROM, RAM,
Data flash
Power Supply Voltage detection
Voltage
circuit
Detection
I/O Ports
Programmable I/O
ports
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DTC (Data Transfer Controller)
Timer
Timer RA
Timer RB
Timer RC
Serial
Interface
UART0, UART1,
UART3
UART2
Synchronous Serial
Communication Unit (SSU)
I2C bus
LIN Module
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Specification
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.3 Product List for R8C/3MK Group
• Power-on reset
• Voltage detection 3 (detection level of voltage detection 0 and voltage
detection 1 selectable)
• CMOS I/O ports: 30, selectable pull-up resistor
• High current drive ports: 30
• 4 circuits: XIN clock oscillation circuit,
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
PLL frequency synthesizer
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (XIN clock, PLL frequency synthesizer, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
• Interrupt Vectors: 69
• External: 9 sources (INT × 5, key input × 4)
• Priority levels: 7 levels
• 14 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
• Activation sources: 26
• Transfer modes: 2 (normal mode, repeat mode)
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
Clock synchronous serial I/O/UART × 3 channel
Clock synchronous serial I/O, UART, multiprocessor communication function
1 (shared with I2C bus)
1 (shared with SSU)
Hardware LIN: 1 (timer RA, UART0)
Page 2 of 56
R8C/3MK Group
Table 1.2
Item
USB Functions
1. Overview
Specifications for R8C/3MK Group (2)
Function
A/D Converter
Comparator B
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
Operating Ambient Temperature
Package
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Specification
• USB 2.0 specification compliant, Full speed (12 Mbps) supported
• USB Device Controller (UDC), transceiver for USB2.0 are incorporated, and
on-chip USB transceiver
• 5 pipes provided with individual FIFO
Arbitrary EP numbers can be specified for PIPE4 to 7
• FIFO size (total 448 bytes:
DCP (EP0) = 64 bytes,
PIPE4 and PIPE5 = 128 bytes (64-byte double buffer),
PIPE6 and PIPE7 = 64 bytes
• Supported transfer:
DCP = Control transfer IN/OUT,
PIPE4 and PIPE5 = Bulk transfer IN/OUT,
PIPE6 and PIPE7 = Interrupt transfer IN/OUT
• When the host controller is selected
Automatic scheduling for SOF and packet transmissions
Programmable intervals for interrupt transfers
10-bit resolution × 10 channels, includes sample and hold function, with sweep
mode
2 circuits
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function (data flash)
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)(USB not used)
f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V)(USB not used)
Typ. 7.0 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 4.0 µA (VCC = 3.0 V, wait mode)
Typ. 2.0 µA (VCC = 3.0 V, stop mode)
−20 to 85°C (N version)
40-pin QFN
Package code: PWQN0040KB-B (previous code: 40PJS-B)
Page 3 of 56
R8C/3MK Group
1.2
1. Overview
Product List
Table 1.3 lists Product List for R8C/3MK Group. Figure 1.1 shows a Part Number, Memory Size, and Package of
R8C/3MK Group.
Table 1.3
Product List for R8C/3MK Group
ROM Capacity
Part No.
Program
Data flash
ROM
R5F213M8KNNP
64 Kbytes 1 Kbyte × 4
R5F213MCKNNP
128Kbytes 1 Kbyte × 4
R5F213M8KNXXXNP 64Kbytes 1 Kbyte × 4
R5F213MCKNXXXNP 128Kbytes 1 Kbyte × 4
Current of Feb 2011
RAM
Capacity
8 Kbytes
10 Kbytes
8 Kbytes
10 Kbytes
Package Type
Remarks
PWQN0040KB-B N version
PWQN0040KB-B
PWQN0040KB-B N version
PWQN0040KB-B
Factory
programmin
g product (1)
Note:
1. The user ROM is programmed before shipment.
Part No. R 5 F 21 3M 8 K N XXX NP
Package type:
NP: PWQN0040KB-B
ROM number
Classification
N: Operating ambient temperature -20°C to 85°C
ROM capacity
8: 64 KB
C: 128 KB
R8C/3MK Group
R8C/3x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/3MK Group
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 4 of 56
R8C/3MK Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a Block Diagram.
I/O ports
6
8
5
Port P0
Port P1
Port P3
3
Port P4
3
2
3
Port P6
Port P7
Port P8
Peripheral functions
Timers
UART or
clock synchronous serial I/O
(8 bits × 4)
System clock generation
circuit
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
I2C bus or SSU
(8 bits × 1)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
PLL frequency synthesizer
Comparator B
Watchdog timer
(14 bits)
Low-speed on-chip oscillator
for watchdog timer
USB Function
(USB2.0 Full speed)
A/D converter
(10 bits × 10 channels)
Voltage detection circuit
USB FIFO
(448 bytes)
DTC
LIN module
Memory
R8C CPU core
R0H
R1H
R0L
R1L
R2
R3
ROM (1)
SB
USP
ISP
RAM (2)
INTB
A0
A1
FB
PC
FLG
Multiplier
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.2
Block Diagram
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 5 of 56
R8C/3MK Group
1.4
1. Overview
Pin Assignment
P1_2/KI2/AN10(/TRCIOB)
P1_3/KI3/AN11/TRBO(/TRCIOC)
P1_4(/TXD0/TRCCLK)
P1_5(/INT1/RXD0/TRAIO)
P1_6/IVREF1(/CLK0)
P1_7/IVCMP1/INT1(/TRAIO)
P4_5/ADTRG/INT0(/RXD2)
P6_5/INT4(/CLK2/CLK1)
P6_6/INT2(/TXD2)
P6_7/INT3(/TRCIOD)
28
27
26
25
24
23
22
21
5
6
7
8
9
10
P4_7/XOUT
VSS/AVSS
P4_6/XIN
VCC/AVCC
P3_7/SSO/SDA/TRAO
P8_2(/TXD3)
RESET
P8_3(/RXD3)
4
P0_0/AN7(/TRCIOA/TRCTRG)
PWQN0040KB-B (40PJS-B)
(Top view)
MODE
37
38
39
40
3
P0_1/AN6(/TXD1/TRCIOA/TRCTRG)
VREF
36
R8C/3MK Group
2
P0_2/AN5(/RXD1/TRCIOA/TRCTRG)
P0_4/AN3(/TRCIOB)
1
P0_3/AN4(/CLK1/TRCIOB)
33
34
35
P0_7/AN0(/TRCIOC)
30
31
32
P8_1(/CLK3)
P1_0/AN8/KI0(/TRCIOD)
P3_0(/TRAO)
P1_1/AN9/KI1(/TRCIOA/TRCTRG)
29
Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines the Pin Name Information by Pin Number.
20
USB_DPUPE
19
USB_VCC
18
17
16
15
14
USB_DP
13
12
11
P3_3/IVCMP3/SCS(/CTS2/RTS2/TRCCLK)
USB_DM
USB_VBUS
P7_6/USB_OVRCURA
P7_7/USB_VBUSEN
P3_4/IVREF3/SSI(/TRCIOC)
P3_5/SCL/SSCK(/TRCIOD)
Notes:
1. Can be assigned to the pin in parentheses by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.3
Pin Assignment (Top View)
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 6 of 56
R8C/3MK Group
Table 1.4
1. Overview
Pin Name Information by Pin Number
Pin
Control Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
Port
Interrupt
P8_1
P3_0
Timer
I/O Pin Functions for Peripheral Modules
Serial
I2C
USB
SSU
Interface
bus
(CLK3)
A/D Converter,
Comparator B
(TRAO)
VREF
MODE
RESET
XOUT
P4_7
VSS/AVSS
XIN
P4_6
VCC/AVCC
P3_7
P3_5
P3_4
TRAO
(TRCIOD)
(TRCIOC)
SSO SDA
SSCK SCL
SSI
13
P3_3
14
15
16
17
18
19
20
P7_7
P7_6
21
P6_7
INT3
22
P6_6
INT2
(TXD2)
23
P6_5
INT4
(CLK2/CLK1)
24
P4_5
INT0
(RXD2)
(INT1)
25
P1_7
26
P1_6
27
P1_5
28
P1_4
29
30
(TRCCLK) (CTS2/RTS2)
IVREF3
IVCMP3
SCS
USB_VBUSEN
USB_OVRCURA
USB_VBUS
USB_DM
USB_DP
USB_VCC
USB_DPUPE
(TRCIOD)
(TRAIO)
ADTRG
IVCMP1
(CLK0)
IVREF1
INT1
(TRAIO)
(RXD0)
(TXD0)
P1_3
KI3
(TRCCLK)
TRBO
(/TRCIOC)
P1_2
KI2
(TRCIOB)
AN10
AN9
AN11
31
P1_1
KI1
(TRCIOA/
TRCTRG)
32
P1_0
KI0
(TRCIOD)
AN8
33
34
35
P0_7
P0_4
P0_3
(CLK1)
AN0
AN3
AN4
36
P0_2
(RXD1)
AN5
37
P0_1
(TXD1)
AN6
38
P0_0
(TRCIOC)
(TRCIOB)
(TRCIOB)
(TRCIOA/
TRCTRG)
(TRCIOA/
TRCTRG)
(TRCIOA/
TRCTRG)
39
40
P8_3
P8_2
AN7
(RXD3)
(TXD3)
Note:
1. Can be assigned to the pin in parentheses by a program.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 7 of 56
R8C/3MK Group
1.5
1. Overview
Pin Functions
Tables 1.5 and 1.6 list Pin Functions.
Table 1.5
Pin Functions (1)
Item
Pin Name
Power supply input VCC, VSS
Analog power
supply input
Reset input
MODE
XIN clock input
XIN clock output
INT interrupt input
Key input interrupt
Timer RA
Timer RB
Timer RC
Serial interface
SSU
I2C bus
AVCC, AVSS
RESET
MODE
XIN
XOUT
INT0 to INT4
KI0 to KI3
TRAIO
TRAO
TRBO
TRCCLK
TRCTRG
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
CLK0, CLK1, CLK2,
CLK3
RXD0, RXD1, RXD2,
RXD3
TXD0, TXD1, TXD2,
TXD3
I/O Type
Description
—
Apply 1.8 to 5.5 V to the VCC pin.
Apply 0 V to the VSS pin.
—
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
I
Input “L” on this pin resets the MCU.
I
I
I/O
I
I
Connect this pin to VCC via a resistor.
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins. (1)
To use an external clock, input it to the XOUT pin and leave
the XIN pin open.
INT interrupt input pins.
Key input interrupt input pins.
I/O
O
O
I
I
I/O
Timer RA I/O pin.
Timer RA output pin.
Timer RB output pin.
External clock input pin.
External trigger input pin.
Timer RC I/O pins.
I/O
Transfer clock I/O pins.
I
Serial data input pins.
O
Serial data output pins.
CTS2
I
Transmission control input pin.
RTS2
SSI
O
Reception control output pin.
I/O
I/O
Data I/O pin.
Chip-select signal I/O pin.
I/O
I/O
I/O
I/O
Clock I/O pin.
Data I/O pin.
Clock I/O pin.
Data I/O pin.
SCS
SSCK
SSO
SCL
SDA
I: Input
O: Output
I/O: Input and output
Note:
1. Refer to the oscillator manufacturer for oscillation characteristics.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 8 of 56
R8C/3MK Group
1. Overview
Table 1.6
Pin Functions (2)
Item
Pin Name
USB_DP/USB_DM
USB
USB_VBUS
USB_VBUSEN
USB_OVRCURA
USB_DPUPE
Reference voltage
input
A/D converter
Comparator B
I/O port
I: Input
USB_VCC
VREF
AN0, AN3 to AN11
ADTRG
IVCMP1, IVCMP3
IVREF1, IVREF3
P0_0 to P0_4, P0_7,
P1_0 to P1_7,
P3_0, P3_3 to P3_5,
P3_7,
P4_5 to P4_7,
P6_5 to P6_7,
P7_6, P7_7
P8_1 to P8_3
O: Output
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
I/O Type
Description
I/O
D+/D- I/O pin of the USB on-chip transceiver.
Connect this pin to the D+/D- pin of the USB bus.
I
USB cable connection monitor pin.
Connect this pin to VBUS of the USB bus. Whether VBUS is
connected or disconnected can be detected during operation
as a function.
O
VBUS (5 V) supply enable signal for external power supply
chip.
I
External overcurrent detection signal should be connected to
this pin. VBUS comparator signals should be connected to
these pins when the USB host power supply chip is
connected.
O
1.5 kΩ pull-up resistor control signal for USB D+ signal when
operating as a function controller.
I/O
USB power supply pin.
I
Reference voltage input pin to A/D converter.
I
I
I
I
I/O
Analog input pins to A/D converter.
AD external trigger input pin.
Comparator B analog voltage input pins.
Comparator B reference voltage input pins.
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
I/O: Input and output
Page 9 of 56
R8C/3MK Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
Data registers (1)
R2
R3
A0
A1
FB
b19
b15
Address registers (1)
Frame base register (1)
b0
Interrupt table register
INTBL
INTBH
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Note:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 10 of 56
R8C/3MK Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 11 of 56
R8C/3MK Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 12 of 56
R8C/3MK Group
3.
3. Memory
Memory
3.1
R8C/3MK Group
Figure 3.1 is a Memory Map of R8C/3MK Group. The R8C/3MK Group has a 1-Mbyte address space from
addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with
address 0FFFFh. A 64-Kbyte internal ROM area is allocated addresses 04000h to 13FFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 8-Kbyte internal
RAM area is allocated addresses 00400h to 023FFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas
for the DTC and other modules). Peripheral function control registers are allocated here. All unallocated spaces
within the SFRs are reserved and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special Function
Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXXh
02C00h
02FFFh
03000h
SFR
(2)
(Refer to 4. Special Function
Registers (SFRs))
0FFDCh
Internal ROM
(data flash) (1)
03FFFh
0YYYYh
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. The data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. The SFR areas for the DTC and other modules are allocated to addresses 02C00h to 02FFFh.
3. The blank areas are reserved and cannot be accessed by users.
Part Number
Internal ROM
Internal RAM
Size
Address 0YYYYh
Address ZZZZZh
Size
Address 0XXXXh
R5F213M8KNNP
R5F213M8KNXXXNP
64 Kbytes
04000h
13FFFh
8 Kbytes
023FFh
R5F213MCKNNP
R5F213MCKNXXXNP
128 Kbytes
04000h
23FFFh
10 Kbytes
02BFFh
Figure 3.1
Memory Map of R8C/3MK Group
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 13 of 56
R8C/3MK Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.15 list the special
function registers. Table 4.16 lists the ID Code Areas and Option Function Select Area.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
SFR Information (1) (1)
Register
Symbol
After Reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
PM0
PM1
CM0
CM1
MSTCR
CM3
PRCR
RSTFR
OCD
WDTR
WDTS
WDTC
00h
00h
00101000b
00100000b
00h
00h
00h
0XXXXXXXb (2)
00000100b
XXh
XXh
00111111b
High-Speed On-Chip Oscillator Control Register 7
FRA7
When shipping
Count Source Protection Mode Register
CSPR
00h
10000000b (3)
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
On-Chip Reference Voltage Control Register
FRA0
FRA1
FRA2
OCVREFCR
00h
When shipping
00h
00h
Clock Prescaler Reset Flag
High-Speed On-Chip Oscillator Control Register 4
High-Speed On-Chip Oscillator Control Register 5
High-Speed On-Chip Oscillator Control Register 6
CPSRF
FRA4
FRA5
FRA6
00h
When shipping
When shipping
When shipping
High-Speed On-Chip Oscillator Control Register 3
Voltage Monitor Circuit Control Register
Voltage Monitor Circuit Edge Select Register
FRA3
CMPA
VCAC
When shipping
00h
00h
Voltage Detect Register 1
Voltage Detect Register 2
VCA1
VCA2
00001000b
00h (4)
00100000b (5)
Voltage Detection 1 Level Select Register
VD1LS
00000111b
Voltage Monitor 0 Circuit Control Register
VW0C
Voltage Monitor 1 Circuit Control Register
VW1C
1100X010b (4)
1100X011b (5)
10001010b
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, software reset, or watchdog timer
reset does not affect this bit.
3. The CSPROINI bit in the OFS register is set to 0.
4. The LVDAS bit in the OFS register is set to 1.
5. The LVDAS bit in the OFS register is set to 0.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 14 of 56
R8C/3MK Group
Table 4.2
Address
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
4. Special Function Registers (SFRs)
SFR Information (2) (1)
Register
Voltage Monitor 2 Circuit Control Register
VW2C
Symbol
After Reset
10000010b
Flash Memory Ready Interrupt Control Register
FMRDYIC
XXXXX000b
INT4 Interrupt Control Register
Timer RC Interrupt Control Register
INT4IC
TRCIC
XX00X000b
XXXXX000b
USB RESUME Interrupt Control Register
USBRSMIC
XXXXX000b
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
SSU Interrupt Control Register/IIC bus Interrupt Control Register (2)
S2TIC
S2RIC
KUPIC
ADIC
SSUIC/IICIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
INT2 Interrupt Control Register
Timer RA Interrupt Control Register
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TRAIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
INT0 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
INT0IC
U2BCNIC
XX00X000b
XXXXX000b
USB INT Interrupt Control Register
UART3 Transmit Interrupt Control Register
UART3 Receive Interrupt Control Register
USBINTIC
S3RIC
S3TIC
XXXXX000b
XXXXX000b
XXXXX000b
Voltage Monitor 1 Interrupt Control Register
Voltage Monitor 2 Interrupt Control Register
VCMP1IC
VCMP2IC
XXXXX000b
XXXXX000b
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by the IICSEL bit in the SSUIICSR register.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 15 of 56
R8C/3MK Group
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
4. Special Function Registers (SFRs)
SFR Information (3) (1)
DTC Activation Control Register
Register
Symbol
DTCTL
00h
After Reset
DTC Activation Enable Register 0
DTC Activation Enable Register 1
DTC Activation Enable Register 2
DTC Activation Enable Register 3
DTCEN0
DTCEN1
DTCEN2
DTCEN3
00h
00h
00h
00h
DTC Activation Enable Register 6
DTCEN6
00h
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
U2MR
U2BRG
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
UART2 Digital Filter Function Select Register
URXDF
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
UART2 Special Mode Register 5
U2SMR5
00h
UART2 Special Mode Register 3
U2SMR3
000X0X0Xb
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 16 of 56
R8C/3MK Group
Table 4.4
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
4. Special Function Registers (SFRs)
SFR Information (4) (1)
Register
Symbol
After Reset
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
A/D Register 0
AD0
A/D Register 1
AD1
A/D Register 2
AD2
A/D Register 3
AD3
A/D Register 4
AD4
A/D Register 5
AD5
A/D Register 6
AD6
A/D Register 7
AD7
A/D Mode Register
A/D Input Select Register
A/D Control Register 0
A/D Control Register 1
ADMOD
ADINSEL
ADCON0
ADCON1
00h
11000000b
00h
00h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
P0
P1
PD0
PD1
XXh
XXh
00h
00h
Port P3 Register
P3
XXh
Port P3 Direction Register
Port P4 Register
PD3
P4
00h
XXh
Port P4 Direction Register
PD4
00h
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
P6
P7
PD6
PD7
P8
XXh
XXh
00h
00h
XXh
Port P8 Direction Register
PD8
00h
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 17 of 56
R8C/3MK Group
Table 4.5
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
4. Special Function Registers (SFRs)
SFR Information (5) (1)
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
LIN Control Register 2
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
LINCR2
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
Timer RC Mode Register
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
Timer RC General Register A
TRCGRA
Timer RC General Register B
TRCGRB
Timer RC General Register C
TRCGRC
Timer RC General Register D
TRCGRD
Timer RC Control Register 2
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
TRCCR2
TRCDF
TRCOER
After Reset
00h
00h
00h
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011000b
00h
01111111b
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 18 of 56
R8C/3MK Group
Table 4.6
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
4. Special Function Registers (SFRs)
SFR Information (6) (1)
Register
Symbol
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
UART3 Transmit/Receive Mode Register
UART3 Bit Rate Register
UART3 Transmit Buffer Register
U3MR
U3BRG
U3TB
UART3 Transmit/Receive Control Register 0
UART3 Transmit/Receive Control Register 1
UART3 Receive Buffer Register
U3C0
U3C1
U3RB
After Reset
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 19 of 56
R8C/3MK Group
Table 4.7
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
4. Special Function Registers (SFRs)
SFR Information (7) (1)
Timer RA Pin Select Register
Timer RC Pin Select Register
Timer RC Pin Select Register 0
Timer RC Pin Select Register 1
Register
Symbol
TRASR
TRBRCSR
TRCPSR0
TRCPSR1
00h
00h
00h
00h
After Reset
UART0 Pin Select Register
UART1 Pin Select Register
UART2 Pin Select Register 0
UART2 Pin Select Register 1
SSU/IIC Pin Select Register
U0SR
U1SR
U2SR0
U2SR1
SSUIICSR
00h
00h
00h
00h
00h
INT Interrupt Input Pin Select Register
I/O Function Pin Select Register
INTSR
PINSR
00h
00h
SS Bit Counter Register
SS Transmit Data Register L / IIC bus Transmit Data Register (2)
SS Transmit Data Register H (2)
SS Receive Data Register L / IIC bus Receive Data Register (2)
SS Receive Data Register H (2)
SS Control Register H / IIC bus Control Register 1 (2)
SS Control Register L / IIC bus Control Register 2 (2)
SS Mode Register / IIC bus Mode Register (2)
SS Enable Register / IIC bus Interrupt Enable Register (2)
SS Status Register / IIC bus Status Register (2)
SS Mode Register 2 / Slave Address Register (2)
SSBR
SSTDR / ICDRT
SSTDRH
SSRDR / ICDRR
SSRDRH
SSCRH / ICCR1
SSCRL / ICCR2
SSMR / ICMR
SSER / ICIER
SSSR / ICSR
SSMR2 / SAR
11111000b
FFh
FFh
FFh
FFh
00h
01111101b
00010000b / 00011000b
00h
00h / 0000X000b
00h
Flash Memory Status Register
FST
10000X00b
Flash Memory Control Register 0
Flash Memory Control Register 1
Flash Memory Control Register 2
FMR0
FMR1
FMR2
00h
00h
00h
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by the IICSEL bit in the SSUIICSR register.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 20 of 56
R8C/3MK Group
Table 4.8
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
4. Special Function Registers (SFRs)
SFR Information (8) (1)
Address Match Interrupt Register 0
Register
Symbol
RMAD0
Address Match Interrupt Enable Register 0
Address Match Interrupt Register 1
AIER0
RMAD1
Address Match Interrupt Enable Register 1
AIER1
After Reset
XXh
XXh
0000XXXXb
00h
XXh
XXh
0000XXXXb
00h
Pull-Up Control Register 0
Pull-Up Control Register 1
Pull-Up Control Register 2
PUR0
PUR1
PUR2
00h
00h
00h
Port P1 Drive Capacity Control Register
P1DRR
00h
Drive Capacity Control Register 0
Drive Capacity Control Register 1
Drive Capacity Control Register 2
Input Threshold Control Register 0
Input Threshold Control Register 1
Input Threshold Control Register 2
Comparator B Control Register 0
DRR0
DRR1
DRR2
VLT0
VLT1
VLT2
INTCMP
00h
00h
00h
00h
00h
00h
00h
External Input Enable Register 0
External Input Enable Register 1
INT Input Filter Select Register 0
INT Input Filter Select Register 1
Key Input Enable Register 0
INTEN
INTEN1
INTF
INTF1
KIEN
00h
00h
00h
00h
00h
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 21 of 56
R8C/3MK Group
Table 4.9
Address
2C00h
2C01h
2C02h
2C03h
2C04h
2C05h
2C06h
2C07h
2C08h
2C09h
2C0Ah
:
:
2C3Ah
2C3Bh
2C3Ch
2C3Dh
2C3Eh
2C3Fh
2C40h
2C41h
2C42h
2C43h
2C44h
2C45h
2C46h
2C47h
2C48h
2C49h
2C4Ah
2C4Bh
2C4Ch
2C4Dh
2C4Eh
2C4Fh
2C50h
2C51h
2C52h
2C53h
2C54h
2C55h
2C56h
2C57h
2C58h
2C59h
2C5Ah
2C5Bh
2C5Ch
2C5Dh
2C5Eh
2C5Fh
2C60h
2C61h
2C62h
2C63h
2C64h
2C65h
2C66h
2C67h
2C68h
2C69h
2C6Ah
2C6Bh
2C6Ch
2C6Dh
2C6Eh
2C6Fh
4. Special Function Registers (SFRs)
SFR Information (9) (1)
Register
Symbol
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Control Data 0
DTCD0
DTC Control Data 1
DTCD1
DTC Control Data 2
DTCD2
DTC Control Data 3
DTCD3
DTC Control Data 4
DTCD4
DTC Control Data 5
DTCD5
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 22 of 56
R8C/3MK Group
Table 4.10
Address
2C70h
2C71h
2C72h
2C73h
2C74h
2C75h
2C76h
2C77h
2C78h
2C79h
2C7Ah
2C7Bh
2C7Ch
2C7Dh
2C7Eh
2C7Fh
2C80h
2C81h
2C82h
2C83h
2C84h
2C85h
2C86h
2C87h
2C88h
2C89h
2C8Ah
2C8Bh
2C8Ch
2C8Dh
2C8Eh
2C8Fh
2C90h
2C91h
2C92h
2C93h
2C94h
2C95h
2C96h
2C97h
2C98h
2C99h
2C9Ah
2C9Bh
2C9Ch
2C9Dh
2C9Eh
2C9Fh
2CA0h
2CA1h
2CA2h
2CA3h
2CA4h
2CA5h
2CA6h
2CA7h
2CA8h
2CA9h
2CAAh
2CABh
2CACh
2CADh
2CAEh
2CAFh
4. Special Function Registers (SFRs)
SFR Information (10) (1)
DTC Control Data 6
Register
Symbol
DTCD6
DTC Control Data 7
DTCD7
DTC Control Data 8
DTCD8
DTC Control Data 9
DTCD9
DTC Control Data 10
DTCD10
DTC Control Data 11
DTCD11
DTC Control Data 12
DTCD12
DTC Control Data 13
DTCD13
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 23 of 56
R8C/3MK Group
Table 4.11
Address
2CB0h
2CB1h
2CB2h
2CB3h
2CB4h
2CB5h
2CB6h
2CB7h
2CB8h
2CB9h
2CBAh
2CBBh
2CBCh
2CBDh
2CBEh
2CBFh
2CC0h
2CC1h
2CC2h
2CC3h
2CC4h
2CC5h
2CC6h
2CC7h
2CC8h
2CC9h
2CCAh
2CCBh
2CCCh
2CCDh
2CCEh
2CCFh
2CD0h
2CD1h
2CD2h
2CD3h
2CD4h
2CD5h
2CD6h
2CD7h
2CD8h
2CD9h
2CDAh
2CDBh
2CDCh
2CDDh
2CDEh
2CDFh
2CE0h
2CE1h
2CE2h
2CE3h
2CE4h
2CE5h
2CE6h
2CE7h
2CE8h
2CE9h
2CEAh
2CEBh
2CECh
2CEDh
2CEEh
2CEFh
4. Special Function Registers (SFRs)
SFR Information (11) (1)
DTC Control Data 14
Register
Symbol
DTCD14
DTC Control Data 15
DTCD15
DTC Control Data 16
DTCD16
DTC Control Data 17
DTCD17
DTC Control Data 18
DTCD18
DTC Control Data 19
DTCD19
DTC Control Data 20
DTCD20
DTC Control Data 21
DTCD21
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 24 of 56
R8C/3MK Group
Table 4.12
Address
2CF0h
2CF1h
2CF2h
2CF3h
2CF4h
2CF5h
2CF6h
2CF7h
2CF8h
2CF9h
2CFAh
2CFBh
2CFCh
2CFDh
2CFEh
2CFFh
2D00h
:
2DFFh
2E00h
2E01h
2E02h
2E03h
2E04h
2E05h
2E06h
2E07h
2E08h
2E09h
2E0Ah
2E0Bh
2E0Ch
2E0Dh
2E0Eh
2E0Fh
2E10h
2E11h
2E12h
2E13h
2E14h
2E15h
2E16h
2E17h
2E18h
2E19h
2E1Ah
2E1Bh
2E1Ch
2E1Dh
2E1Eh
2E1Fh
2E20h
2E21h
2E22h
2E23h
2E24h
2E25h
2E26h
2E27h
2E28h
2E29h
2E2Ah
2E2Bh
2E2Ch
2E2Dh
2E2Eh
2E2Fh
4. Special Function Registers (SFRs)
SFR Information (12) (1)
DTC Control Data 22
Register
Symbol
DTCD22
After Reset
DTC Control Data 23
DTCD23
System Configuration Control Register
SYSCFG
00h
00h
System Configuration Status Register 0
SYSSTS0
00000X00b
XX000000b
Device State Control Register 0
DVSTCTR0
00h
00h
CFIFO Port Register
CFIFO
00h
00h
CFIFO Port Select Register
CFIFOSEL
CFIFO Port Control Register
CFIFOCTR
00h
00h
00h
00h
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 25 of 56
R8C/3MK Group
Table 4.13
Address
2E30h
2E31h
2E32h
2E33h
2E34h
2E35h
2E36h
2E37h
2E38h
2E39h
2E3Ah
2E3Bh
2E3Ch
2E3Dh
2E3Eh
2E3Fh
2E40h
2E41h
2E42h
2E43h
2E44h
2E45h
2E46h
2E47h
2E48h
2E49h
2E4Ah
2E4Bh
2E4Ch
2E4Dh
2E4Eh
2E4Fh
2E50h
2E51h
2E52h
2E53h
2E54h
2E55h
2E56h
2E57h
2E58h
2E59h
2E5Ah
2E5Bh
2E5Ch
2E5Dh
2E5Eh
2E5Fh
2E60h
2E61h
2E62h
2E63h
2E64h
2E65h
2E66h
2E67h
2E68h
2E69h
2E6Ah
2E6Bh
2E6Ch
2E6Dh
2E6Eh
2E6Fh
4. Special Function Registers (SFRs)
SFR Information (13) (1)
Interrupt Enable Register 0
Register
Symbol
INTENB0
After Reset
Interrupt Enable Register 1
INTENB1
BRDY Interrupt Enable Register
BRDYENB
NRDY Interrupt Enable Register
NRDYENB
BEMP Interrupt Enable Register
BEMPENB
SOF Output Configuration Register
SOFCFG
Interrupt Status Register 0
INTSTS0
Interrupt Status Register 1
INTSTS1
BRDY Interrupt Status Register
BRDYSTS
NRDY Interrupt Status Register
NRDYSTS
BEMP Interrupt Status Register
BEMPSTS
Frame Number Register
FRMNUM
USB Address Register
USBADDR
00h
00h
USB Request Type Register
USBREQ
USB Request Value Register
USBVAL
USB Request Index Register
USBINDX
USB Request Length Register
USBLENG
DCP Configuration Register
DCPCFG
DCP Max Packet Size Register
DCPMAXP
DCP Control Register
DCPCTR
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Pipe Window Select Register
PIPESEL
00h
00h
Pipe Window Configuration Register
PIPECFG
00h
00h
Pipe Max Packet Size Register
PIPEMAXP
Pipe Period Control Register
PIPEPERI
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
X0000000b
X0000000b
00h
XX0X0000b
00h
00h
00h
00h
00h
00h
00h
00h
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 26 of 56
R8C/3MK Group
Table 4.14
Address
2E70h
2E71h
2E72h
2E73h
2E74h
2E75h
2E76h
2E77h
2E78h
2E79h
2E7Ah
2E7Bh
2E7Ch
2E7Dh
2E7Eh
2E7Fh
2E80h
:
2E8Fh
2E90h
2E91h
2E92h
2E93h
2E94h
2E95h
2E96h
2E97h
2E98h
2E99h
2E9Ah
2E9Bh
2E9Ch
2E9Dh
2E9Eh
2E9Fh
2EA0h
2EA1h
2EA2h
2EA3h
2EA4h
2EA5h
2EA6h
2EA7h
2EA8h
2EA9h
2EAAh
2EABh
2EACh
2EADh
:
2ECFh
2ED0h
2ED1h
2ED2h
2ED3h
2ED4h
2ED5h
2ED6h
2ED7h
2ED8h
2ED9h
2EDAh
2EDBh
2EDCh
2EDDh
:
2EFFh
4. Special Function Registers (SFRs)
SFR Information (14) (1)
Register
Symbol
After Reset
Pipe 4 Control Register
PIPE4CTR
00h
00h
00h
00h
00h
00h
00h
00h
Pipe 5 Control Register
PIPE5CTR
Pipe 6 Control Register
PIPE6CTR
Pipe 7 Control Register
PIPE7CTR
Pipe 4 Transaction Counter Enable Register
PIPE4TRE
Pipe 4 Transaction Counter Register
PIPE4TRN
Pipe 5 Transaction Counter Enable Register
PIPE5TRE
Pipe 5 Transaction Counter Register
PIPE5TRN
Device Address 0 Configuration Register
DEVADD0
00h
00h
Device Address 4 Configuration Register
DEVADD4
Device Address 5 Configuration Register
DEVADD5
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 27 of 56
R8C/3MK Group
SFR Information (15) (1)
Table 4.15
Address
2F00h
2F01h
2F02h
2F03h
2F04h
2F05h
2F06h
2F07h
2F08h
2F09h
2F0Ah
2F0Bh
2F0Ch
2F0Dh
2F0Eh
2F0Fh
2F10h
2F11h
2F12h
2F13h
2F14h
2F15h
2F16h
2F17h
2F18h
2F19h
2F1Ah
2F1Bh
2F1Ch
2F1Dh
2F1Eh
2F1Fh
:
2FFFh
4. Special Function Registers (SFRs)
USB Module Control Register
PLL Control Register 0
PLL Control Register 1
PLL Division Control Register
Register
Symbol
USBMC
PLC0
PLC1
PLDIV
After Reset
00X10000b
0010X000b
00001100b
00001011b
USB Pin Select Register 0
USBSR0
00h
UART3 Pin Select Register
U3SR
00h
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
Table 4.16
ID Code Areas and Option Function Select Area
Address
:
FFDBh
:
FFDFh
:
FFE3h
:
FFEBh
:
FFEFh
:
FFF3h
:
FFF7h
:
FFFBh
:
FFFFh
Area Name
Option Function Select Register 2
Symbol
OFS2
After Reset
(Note 1)
ID1
(Note 2)
ID2
(Note 2)
ID3
(Note 2)
ID4
(Note 2)
ID5
(Note 2)
ID6
(Note 2)
ID7
(Note 2)
Option Function Select Register
OFS
(Note 1)
Notes:
1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select
area is set to FFh.
When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user.
When factory-programming products are shipped, the value of the option function select area is the value programmed by the user.
2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh.
When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user.
When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 28 of 56
R8C/3MK Group
5.
5. Electrical Characteristics
Electrical Characteristics
Table 5.1
Absolute Maximum Ratings
Symbol
Parameter
Condition
VCC/AVCC Supply voltage
Rated Value
Unit
−0.3 to 6.5
V
V
VI
Input voltage
−0.3 to VCC + 0.3
VO
Output voltage
−0.3 to VCC + 0.3
V
Pd
Power dissipation
500
mW
Topr
Operating ambient temperature
Tstg
Storage temperature
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
−20°C ≤ Topr ≤ 85°C
−20 to 85 (N version)
°C
−65 to 150
°C
Page 29 of 56
R8C/3MK Group
Table 5.2
5. Electrical Characteristics
Recommended Operating Conditions (1)
Symbol
Parameter
VCC/AVCC Supply voltage
UVCC
USB Supply
Voltage (When
UVCC pin is
input)
When USB function is used
When USB function is not used
When USB function is used
Conditions
VCC/AVCC = 3.0 to
3.6 V
Min.
3.0
1.8
—
Standard
Typ.
5.0
5.0
VCC/
AVCC
Max.
5.5
5.5
—
Unit
V
V
V
(4)
When USB function is not used
VCC/AVCC = 1.8 to
5.5 V
—
VCC/
AVCC
—
V
(4)
VSS/AVSS
VIH
Supply voltage
Input “H” voltage Other than CMOS input
CMOS Input level Input level selection:
input
switching 0.35 VCC
function
(I/O port) Input level selection:
0.5 VCC
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
Input level selection: 4.0 V ≤ VCC ≤ 5.5 V
0.7 VCC
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
External clock input (XOUT)
Input “L” voltage Other than CMOS input
VIL
CMOS Input level Input level selection: 4.0 V ≤ VCC ≤ 5.5 V
input
switching 0.35 VCC
2.7 V ≤ VCC < 4.0 V
function
1.8 V ≤ VCC < 2.7 V
(I/O port) Input level selection: 4.0 V ≤ VCC ≤ 5.5 V
0.5 VCC
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
Input level selection: 4.0 V ≤ VCC ≤ 5.5 V
0.7 VCC
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
External clock input (XOUT)
Peak sum output “H”
Sum of all pins IOH(peak)
IOH(sum)
current
IOH(sum)
Average sum output “H” Sum of all pins IOH(avg)
current
Peak output “H” current
Drive capacity Low
IOH(peak)
Drive capacity High
Average output “H”
Drive capacity Low
IOH(avg)
current
Drive capacity High
Peak sum output “L”
Sum of all pins IOL(peak)
IOL(sum)
current
IOL(sum)
Average sum output “L”
Sum of all pins IOL(avg)
current
IOL(peak)
Peak output “L” current
Drive capacity Low
Drive capacity High
Average output “L”
Drive capacity Low
IOL(avg)
current
Drive capacity High
XIN clock input oscillation frequency
2.7 V ≤ VCC ≤ 5.5 V
f(XIN)
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
fOCO40M When used as the count source for timer RC (3)
fOCO-F
fOCO-F frequency
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
—
System clock frequency
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
CPU clock frequency
2.7 V ≤ VCC ≤ 5.5 V
f(BCLK)
1.8 V ≤ VCC < 2.7 V
—
0.8 VCC
0.5 VCC
0.55 VCC
0.65 VCC
0.65 VCC
0.7 VCC
0.8 VCC
0.85 VCC
0.85 VCC
0.85 VCC
1.2
0
0
0
0
0
0
0
0
0
0
0
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
0.2 VCC
0.2 VCC
0.2 VCC
0.2 VCC
0.4 VCC
0.3 VCC
0.2 VCC
0.55 VCC
0.45 VCC
0.35 VCC
0.4
−160
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
—
—
−80
mA
—
—
—
—
—
—
—
—
—
—
−10
−40
−5
−20
160
mA
mA
mA
mA
mA
—
—
80
mA
—
—
—
—
—
—
32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
40
5
20
20
5
40
20
5
20
5
20
5
mA
mA
mA
mA
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Notes:
1. VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
3. fOCO40M can be used as the count source for timer RC in the range of VCC = 2.7 to 5.5 V.
4. Connect VCC/AVCC for the UVCC pin input.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 30 of 56
R8C/3MK Group
5. Electrical Characteristics
P0
P1
P3
P4
P6
P7
P8
Figure 5.1
30pF
Ports P0, P1, P3, P4, P6, P7 and P8 Timing Measurement Circuit
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 31 of 56
R8C/3MK Group
Table 5.3
5. Electrical Characteristics
A/D Converter Characteristics
Symbol
Parameter
—
Resolution
—
Absolute accuracy
Vref = AVCC
10-bit mode
8-bit mode
φAD
A/D conversion clock
—
Tolerance level impedance
tCONV
Conversion time
Standard
Conditions
—
10
Bit
—
—
±3
LSB
Vref = AVCC = 3.3 V
AN0, AN3 to AN7
input,
AN8 to AN11 input
—
—
±5
LSB
Vref = AVCC = 3.0 V
AN0, AN3 to AN7
input,
AN8 to AN11 input
—
—
±5
LSB
Vref = AVCC = 2.2 V
AN0, AN3 to AN7
input,
AN8 to AN11 input
—
—
±5
LSB
Vref = AVCC = 5.0 V
AN0, AN3 to AN7
input,
AN8 to AN11 input
—
—
±2
LSB
Vref = AVCC = 3.3 V
AN0, AN3 to AN7
input,
AN8 to AN11 input
—
—
±2
LSB
Vref = AVCC = 3.0 V
AN0, AN3 to AN7
input,
AN8 to AN11 input
—
—
±2
LSB
Vref = AVCC = 2.2 V
AN0, AN3 to AN7
input,
AN8 to AN11 input
—
—
±2
LSB
4.0 V ≤ Vref = AVCC ≤ 5.5 V (2)
2
—
20
MHz
3.2 V ≤ Vref = AVCC ≤ 5.5 V (2)
2
—
16
MHz
2.7 V ≤ Vref = AVCC ≤ 5.5 V (2)
2
—
10
MHz
2.2 V ≤ Vref = AVCC ≤ 5.5 V
2
—
5
MHz
(2)
—
3
—
kΩ
10-bit mode
Vref = AVCC = 5.0 V, φAD = 20 MHz
2.2
—
—
µs
8-bit mode
Vref = AVCC = 5.0 V, φAD = 20 MHz
2.2
—
—
µs
0.8
—
—
µs
VCC = 5.0 V, XIN = f1 = φAD = 20 MHz
Reference voltage
VIA
Analog input voltage(3)
OCVREF
On-chip reference voltage
Unit
—
φAD = 20 MHz
Vref current
Max.
AN0, AN3 to AN7
input,
AN8 to AN11 input
Sampling time
IVref
Typ.
Vref = AVCC = 5.0 V
tSAMP
Vref
Min.
2 MHz ≤ φAD ≤ 4 MHz
—
45
—
µA
2.2
—
AVCC
V
0
—
Vref
V
1.19
1.34
1.49
V
Notes:
1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version), unless otherwise specified.
2. The A/D conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-currentconsumption mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion.
3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 32 of 56
R8C/3MK Group
Table 5.4
5. Electrical Characteristics
Comparator B Electrical Characteristics
Symbol
Parameter
Condition
Vref
IVREF1, IVREF3 input reference voltage
VI
IVCMP1, IVCMP3 input voltage
—
Offset
td
Comparator output delay time (2)
VI = Vref ± 100 mV
ICMP
Comparator operating current
VCC = 5.0 V
Standard
Min.
Typ.
Max.
Unit
0
—
VCC − 1.4
−0.3
—
VCC + 0.3
V
—
5
100
mV
—
0.1
—
µs
—
17.5
—
µA
V
Notes:
1. VCC = 2.7 to 5.5 V and Topr = −20 to 85 °C (N version), unless otherwise specified.
2. When the digital filter is disabled.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 33 of 56
R8C/3MK Group
Table 5.5
5. Electrical Characteristics
USB Characteristics
Symbol
Parameter
Figure 5.2 and 5.3
Typ.
Max.
Unit
2.0
—
—
V
—
—
0.8
V
VDI
Differential input sensitivity
0.2
—
—
V
VCM
Differential common mode range
0.8
—
2.5
V
Output “H” voltage
Figure 5.2 and 5.3
ICH = 200µA
2.8
—
—
V
VOL
Output “L” voltage
Figure 5.2 and 5.3
ICL = 2 mA
—
—
0.3
V
VCRS
Crossover voltage
Figure 5.2 and 5.3
1.3
—
2.0
V
tR
Rise time
Figure 5.2 and 5.3
4.0
—
20.0
ns
tF
Fall time
Figure 5.2 and 5.3
4.0
—
20.0
ns
tRFM
Rise time / Fall time matching
Figure 5.2 and 5.3
(tR/tF)
90.0
—
111.1
%
ZDRV
Output resistance
Figure 5.2 and 5.3
Includes RS = 27Ω
28
—
44.0
Ω
VOH
UVCC
Isusp
Output
characteristics
Input “H” voltage
Standard
Min.
Input “L” voltage
VIH
VIL
Input
characteristics
Condition
UVCC output
voltage
VCC = 4.0 to 5.5V, PXXCON = VDDUSBE = 1
3.0
3.3
3.6
V
PXXCON = 0
—
VCC
—
V
Consumption current of the Internal power supply for
USB
VCC = 4.0 to 5.5 V
UVCC - VSS 0.33 µF
VCC - VSS 0.1 µF
µA
50
Note:
1. Referenced to VCC = 3.0 to 5.5 V, UVCC = 3.0 V, at Topr = -20 to 85 °C (N version) unless otherwise specified.
Rising time
D+ D-
90 %
VCRS
Falling time
90 %
10 %
10 %
tR
Figure 5.2
tF
Data Signal Timing Diagram
D+ RS = 27 Ω
Test point
RS = 27 Ω
Test point
D-
Figure 5.3
Differential
Date Lines
Load Condition
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 34 of 56
R8C/3MK Group
Table 5.6
5. Electrical Characteristics
Flash Memory (Program ROM) Electrical Characteristics
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
1,000 (3)
—
—
times
Byte program time
—
80
500
µs
Block erase time
—
0.3
—
s
td(SR-SUS) Time delay from suspend request until
suspend
—
—
5 + CPU clock
× 3 cycles
ms
—
Interval from erase start/restart until
following suspend request
0
—
—
µs
—
Time from suspend until erase restart
—
—
30 + CPU clock
× 1 cycle
µs
−
−
30 + CPU clock
× 1 cycle
µs
V
—
Program/erase endurance (2)
—
—
td(CMDRST Time from when command is forcibly
-READY)
stopped until reading is enabled
—
Program, erase voltage
2.7
—
5.5
—
Read voltage
1.8
—
5.5
V
—
Program, erase temperature
0
—
60
°C
—
Data hold time (7)
20
—
—
year
Ambient temperature = 55 °C
Notes:
1. VCC = 2.7 to 5.5 V and Topr = 0 to 60 °C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one. However, the same address must not be programmed more than once
per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed.)
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 35 of 56
R8C/3MK Group
Table 5.7
5. Electrical Characteristics
Flash Memory (Data flash Block A to Block D) Electrical Characteristics
Symbol
Parameter
Standard
Conditions
Min.
Typ.
Max.
Unit
10,000 (3)
—
—
times
Byte program time
(program/erase endurance ≤ 1,000 times)
—
160
1500
µs
—
Byte program time
(program/erase endurance > 1,000 times)
—
300
1500
µs
—
Block erase time
(program/erase endurance ≤ 1,000 times)
—
0.2
1
s
—
Block erase time
(program/erase endurance > 1,000 times)
—
0.3
1
s
td(SR-SUS) Time delay from suspend request until
suspend
—
—
5 + CPU clock
× 3 cycles
ms
—
Interval from erase start/restart until
following suspend request
0
—
—
µs
—
Time from suspend until erase restart
—
—
30 + CPU clock
× 1 cycle
µs
−
−
30 + CPU clock
× 1 cycle
µs
V
—
Program/erase endurance (2)
—
td(CMDRST Time from when command is forcibly
-READY)
stopped until reading is enabled
—
Program, erase voltage
2.7
—
5.5
—
Read voltage
1.8
—
5.5
V
—
Program, erase temperature
−20
—
85
°C
—
Data hold time (7)
20
—
—
year
Ambient temperature = 55 °C
Notes:
1. VCC = 2.7 to 5.5 V and Topr = −20 to 85 °C (N version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one. However, the same address must not be programmed more than once
per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed.)
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Suspend request
(FMR21 bit)
FST7 bit
FST6 bit
Fixed time
Clock-dependent
time
Access restart
td(SR-SUS)
FST6, FST7: Bit in FST register
FMR21: Bit in FMR2 register
Figure 5.4
Time delay until Suspend
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 36 of 56
R8C/3MK Group
Table 5.8
5. Electrical Characteristics
Voltage Detection 0 Circuit Electrical Characteristics
Symbol
Vdet0
Parameter
Standard
Unit
Min.
Typ.
Max.
Voltage detection level Vdet0_0 (2)
1.80
1.90
2.05
V
Voltage detection level Vdet0_1 (2)
2.15
2.35
2.50
V
Voltage detection level Vdet0_2 (2)
2.70
2.85
3.05
V
(2)
3.55
3.80
4.05
V
—
6
150
µs
—
1.5
—
µA
—
—
100
µs
Voltage detection level Vdet0_3
—
Condition
Voltage detection 0 circuit response time
(4)
—
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts (3)
At the falling of VCC from
5.0 V to (Vdet0_0 − 0.1) V
VCA25 = 1, VCC = 5.0 V
Notes:
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version).
2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
4. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
Table 5.9
Voltage Detection 1 Circuit Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
Voltage detection level Vdet1_0 (2)
At the falling of VCC
2.00
2.20
2.40
V
Voltage detection level Vdet1_1 (2)
At the falling of VCC
2.15
2.35
2.55
V
Voltage detection level Vdet1_2 (2)
At the falling of VCC
2.30
2.50
2.70
V
Voltage detection level Vdet1_3
(2)
At the falling of VCC
2.45
2.65
2.85
V
Voltage detection level Vdet1_4
(2)
At the falling of VCC
2.60
2.80
3.00
V
Voltage detection level Vdet1_5 (2)
At the falling of VCC
2.75
2.95
3.15
V
Voltage detection level Vdet1_6 (2)
At the falling of VCC
2.85
3.10
3.40
V
Voltage detection level Vdet1_7
(2)
At the falling of VCC
3.00
3.25
3.55
V
Voltage detection level Vdet1_8
(2)
At the falling of VCC
3.15
3.40
3.70
V
Voltage detection level Vdet1_9 (2)
At the falling of VCC
3.30
3.55
3.85
V
Voltage detection level Vdet1_A (2)
At the falling of VCC
3.45
3.70
4.00
V
Voltage detection level Vdet1_B
(2)
At the falling of VCC
3.60
3.85
4.15
V
Voltage detection level Vdet1_C
(2)
At the falling of VCC
3.75
4.00
4.30
V
Voltage detection level Vdet1_D (2)
At the falling of VCC
3.90
4.15
4.45
V
Voltage detection level Vdet1_E (2)
At the falling of VCC
4.05
4.30
4.60
V
Voltage detection level Vdet1_F (2)
At the falling of VCC
4.20
4.45
4.75
V
Hysteresis width at the rising of VCC in voltage
detection 1 circuit
Vdet1_0 to Vdet1_5
selected
—
0.07
—
V
Vdet1_6 to Vdet1_F
selected
—
0.10
—
V
Voltage detection 1 circuit response time (3)
At the falling of VCC from
5.0 V to (Vdet1_0 − 0.1) V
—
60
150
µs
—
Voltage detection circuit self power consumption
VCA26 = 1, VCC = 5.0 V
—
1.7
—
µA
td(E-A)
Waiting time until voltage detection circuit operation
starts (4)
—
—
100
µs
Vdet1
—
—
Notes:
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version).
2. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
3. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
4. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 37 of 56
R8C/3MK Group
Table 5.10
5. Electrical Characteristics
Voltage Detection 2 Circuit Electrical Characteristics
Symbol
Parameter
Standard
Condition
Vdet2
Voltage detection level Vdet2_0
—
Hysteresis width at the rising of VCC in voltage
detection 2 circuit
At the falling of VCC
—
Voltage detection 2 circuit response time (2)
At the falling of VCC from
5.0 V to (Vdet2_0 − 0.1) V
—
Voltage detection circuit self power consumption
VCA27 = 1, VCC = 5.0 V
td(E-A)
Waiting time until voltage detection circuit operation
starts (3)
Unit
Min.
Typ.
Max.
3.70
4.00
4.30
V
—
0.10
—
V
—
20
150
µs
—
1.7
—
µA
—
—
100
µs
Notes:
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Table 5.11
Power-on Reset Circuit (2)
Symbol
Parameter
Condition
External power VCC rise gradient
trth
Standard
Min.
Typ.
Max.
0
—
50,000
(1)
Unit
mV/msec
Notes:
1. The measurement condition is Topr = −20 to 85 °C (N version), unless otherwise specified.
2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Vdet0 (1)
Vdet0 (1)
trth
trth
External
Power VCC
0.5 V
tw(por) (2)
Voltage detection 0
circuit response time
Internal
reset signal
1
× 32
fOCO-S
1
× 32
fOCO-S
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit.
2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
tw(por) for 1 ms or more.
Figure 5.5
Power-on Reset Circuit Electrical Characteristics
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 38 of 56
R8C/3MK Group
Table 5.12
5. Electrical Characteristics
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
—
Parameter
Condition
Standard
Unit
Min.
Typ.
Max.
36.0
40
44.0
MHz
High-speed on-chip oscillator frequency when the VCC = 1.8 V to 5.5 V
FRA4 register correction value is written into the
FRA1 register and the FRA5 register correction
value into the FRA3 register (2)
33.178
36.864
40.550
MHz
High-speed on-chip oscillator frequency when the VCC = 1.8 V to 5.5 V
FRA6 register correction value is written into the
FRA1 register and the FRA7 register correction
value into the FRA3 register
28.8
32
35.2
MHz
High-speed on-chip oscillator frequency after
reset
VCC = 1.8 V to 5.5 V
—
Oscillation stability time
VCC = 5.0 V, Topr = 25 °C
—
0.5
3
ms
—
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25 °C
—
400
—
µA
Notes:
1. VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version), unless otherwise specified.
2. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Table 5.13
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
fOCO-S
Low-speed on-chip oscillator frequency
60
125
250
—
Oscillation stability time
VCC = 5.0 V, Topr = 25 °C
—
30
100
kHz
µs
—
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25 °C
—
2
—
µA
Note:
1. VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version), unless otherwise specified.
Table 5.14
Power Supply Circuit Timing Characteristics
Symbol
td(P-R)
Parameter
Condition
Time for internal power supply stabilization during
power-on (2)
Standard
Min.
Typ.
Max.
—
—
2,000
Unit
µs
Notes:
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 25 °C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 39 of 56
R8C/3MK Group
Table 5.15
Symbol
5. Electrical Characteristics
Timing Requirements of Synchronous Serial Communication Unit (SSU)
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
tSUCYC
SSCK clock cycle time
4
—
—
tCYC (2)
tHI
SSCK clock “H” width
0.4
—
0.6
tSUCYC
tLO
SSCK clock “L” width
0.4
—
0.6
tSUCYC
tRISE
SSCK clock rising
time
—
—
1
tCYC (2)
tFALL
SSCK clock falling
time
—
tSU
SSO, SSI data input setup time
100
tH
SSO, SSI data input hold time
1
tLEAD
Master
Slave
—
—
1
µs
Master
—
—
1
tCYC (2)
—
1
µs
—
—
ns
—
—
tCYC (2)
Slave
SCS setup time
Slave
1tCYC + 50
—
—
ns
tLAG
SCS hold time
Slave
1tCYC + 50
—
—
ns
tOD
SSO, SSI data output delay time
—
—
1
tCYC (2)
tSA
SSI slave access time
2.7 V ≤ VCC ≤ 5.5 V
—
—
1.5tCYC + 100
ns
1.8 V ≤ VCC < 2.7 V
—
—
1.5tCYC + 200
ns
2.7 V ≤ VCC ≤ 5.5 V
—
—
1.5tCYC + 100
ns
1.8 V ≤ VCC < 2.7 V
—
—
1.5tCYC + 200
ns
tOR
SSI slave out open time
Notes:
1. VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 40 of 56
R8C/3MK Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 5.6
I/O Timing of Synchronous Serial Communication Unit (SSU) (Master)
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 41 of 56
R8C/3MK Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.7
I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave)
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 42 of 56
R8C/3MK Group
5. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIL or VOL
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
Figure 5.8
tH
I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous
Communication Mode)
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 43 of 56
R8C/3MK Group
Table 5.16
5. Electrical Characteristics
Timing Requirements of I2C bus Interface
Symbol
Parameter
Standard
Typ.
—
12tCYC + 600 (2)
—
3tCYC + 300 (2)
Condition
Min.
Max.
—
Unit
tSCL
SCL input cycle time
tSCLH
SCL input “H” width
tSCLL
SCL input “L” width
tsf
tSP
SCL, SDA input fall time
SCL, SDA input spike pulse rejection time
tBUF
SDA input bus-free time
5tCYC (2)
—
1tCYC (2)
—
tSTAH
Start condition input hold time
3tCYC (2)
—
—
ns
tSTAS
Retransmit start condition input setup time
3tCYC (2)
—
—
ns
tSTOP
Stop condition input setup time
3tCYC (2)
—
—
ns
tSDAS
Data input setup time
—
—
ns
tSDAH
Data input hold time
1tCYC + 40 (2)
10
—
—
ns
5tCYC + 500
—
—
—
(2)
—
—
ns
—
ns
—
ns
300
ns
ns
ns
Notes:
1. VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOP
SCL
P (2)
S (1)
tSf
Sr (3)
tSCLL
tSr
tSCL
P (2)
tSDAS
tSDAH
Notes:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 5.9
I/O Timing of I2C bus Interface
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 44 of 56
R8C/3MK Group
Table 5.17
5. Electrical Characteristics
Electrical Characteristics (1) [4.2 V ≤ VCC ≤ 5.5 V]
Symbol
Parameter
VOH
Output “H” Other than XOUT
voltage
VOL
Output “L”
voltage
VT+-VT-
IIH
IIL
RPULLUP
RfXIN
VRAM
XOUT
Other than XOUT
XOUT
Hysteresis INT0, INT1, INT2,
INT3, INT4,
KI0, KI1, KI2, KI3,
TRAIO,TRCIOA,
TRCIOB, TRCIOC,
TRCIOD,
USB_OVRCURA,
USB_VBUS,
TRCTRG, TRCCLK,
ADTRG, RXD0,
RXD1, RXD2, RXD3,
CLK0, CLK1, CLK2,
CLK3, CTS2, SSI,
SCL, SDA, SSO,
SSCK, SCS
RESET
Input “H” current
Input “L” current
Pull-up resistance
Feedback XIN
resistance
RAM hold voltage
Condition
Drive capacity High
Drive capacity Low
VCC = 5 V
Drive capacity High
Drive capacity Low
VCC = 5 V
VCC = 5 V
VCC = 5 V
VCC = 5 V
VCC = 5 V
Standard
Min.
Typ.
IOH = −20 mA VCC − 2.0
—
IOH = −5 mA
VCC − 2.0
—
IOH = −200 µA
1.0
—
IOL = 20 mA
—
—
IOL = 5 mA
—
—
IOL = 200 µA
—
—
0.1
1.2
0.1
1.2
VI = 5 V, VCC = 5.0 V
VI = 0 V, VCC = 5.0 V
VI = 0 V, VCC = 5.0 V
—
—
25
—
—
—
50
0.3
During stop mode
1.8
—
Max.
VCC
VCC
VCC
2.0
2.0
0.5
—
Unit
V
V
V
V
V
V
V
—
V
5.0
µA
−5.0
100
—
µA
kΩ
MΩ
—
V
Note:
1. 4.2 V ≤ VCC ≤ 5.5 V, Topr = −20 to 85 °C (N version), and f(XIN) = 20 MHz, unless otherwise specified.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 45 of 56
R8C/3MK Group
Table 5.18
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (2) [3.3 V ≤ VCC ≤ 5.5 V]
(Topr = −20 to 85 °C (N version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 3.3 to 5.5 V) clock mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip
oscillator mode
Low-speed
on-chip
oscillator mode
Wait mode
Stop mode
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-16, MSTIIC = MSTTRC = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR27 = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Min.
—
Standard
Typ. Max.
6.5
15
Unit
mA
—
5.3
12.5
mA
—
3.6
—
mA
—
3.0
—
mA
—
2.2
—
mA
—
1.5
—
mA
—
7.0
15
mA
—
3.0
—
mA
—
1
—
mA
—
90
400
µA
—
15
100
µA
—
4
90
µA
—
3.5
—
µA
—
2.0
5.0
µA
—
15
—
µA
Page 46 of 56
R8C/3MK Group
5. Electrical Characteristics
Timing Requirements
Table 5.19
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V, Topr = 25 °C)
External Clock Input (XOUT)
Symbol
tc(XOUT)
tWH(XOUT)
tWL(XOUT)
Standard
Min.
Max.
50
—
24
—
24
—
Parameter
XOUT input cycle time
XOUT input “H” width
XOUT input “L” width
tC(XOUT)
Unit
ns
ns
ns
VCC = 5 V
tWH(XOUT)
External clock input
tWL(XOUT)
Figure 5.10
Table 5.20
External Clock Input Timing Diagram when VCC = 5 V
TRAIO Input
Symbol
Standard
Min.
Max.
100
—
40
—
40
—
Parameter
tc(TRAIO)
TRAIO input cycle time
tWH(TRAIO) TRAIO input “H” width
tWL(TRAIO) TRAIO input “L” width
tC(TRAIO)
Unit
ns
ns
ns
VCC = 5 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.11
TRAIO Input Timing Diagram when VCC = 5 V
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 47 of 56
R8C/3MK Group
Table 5.21
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
200
—
100
—
100
—
—
50
0
—
50
—
90
—
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 to 3
tC(CK)
VCC = 5 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 3
Figure 5.12
Table 5.22
Serial Interface Timing Diagram when VCC = 5 V
External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)
tW(INH)
INTi input “H” width, KIi input “H” width
Standard
Min.
Max.
(1)
—
250
tW(INL)
INTi input “L” width, KIi input “L” width
250 (2)
Symbol
Parameter
—
Unit
ns
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
INTi input
(i = 0 to 4)
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.13
tW(INH)
Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi
when VCC = 5 V
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 48 of 56
R8C/3MK Group
Table 5.23
5. Electrical Characteristics
Electrical Characteristics (3) [2.7 V ≤ VCC < 4.2 V]
Symbol
Parameter
VOH
Output “H” voltage Other than XOUT
VOL
Output “L” voltage
VT+-VT-
Hysteresis
IIH
IIL
RPULLUP
RfXIN
VRAM
Input “H” current
Input “L” current
Pull-up resistance
Feedback
resistance
RAM hold voltage
XOUT
Other than XOUT
Condition
Drive capacity High
Drive capacity Low
Drive capacity High
Drive capacity Low
XOUT
VCC = 3.0 V
INT0, INT1, INT2,
INT3, INT4,
KI0, KI1, KI2, KI3,
TRAIO, TRCIOA,
TRCIOB, TRCIOC,
TRCIOD,
USB_OVRCURA,
USB_VBUS,
TRCTRG, TRCCLK,
ADTRG, RXD0,
RXD1, RXD2, RXD3,
CLK0, CLK1, CLK2,
CLK3, CTS2, SSI,
SCL, SDA, SSO,
SSCK, SCS
VCC = 3.0 V
RESET
Min.
IOH = −5 mA
VCC − 0.5
IOH = −1 mA
VCC − 0.5
IOH = −200 µA
1.0
IOL = 5 mA
—
IOL = 1 mA
—
IOL = 200 µA
—
0.1
Standard
Typ.
—
—
—
—
—
—
0.4
0.1
0.5
VI = 3 V, VCC = 3.0 V
VI = 0 V, VCC = 3.0 V
VI = 0 V, VCC = 3.0 V
—
—
42
—
—
—
84
0.3
During stop mode
1.8
—
XIN
Max.
VCC
VCC
VCC
0.5
0.5
0.5
—
Unit
V
V
V
V
V
V
V
—
V
4.0
µA
−4.0
168
—
µA
kΩ
MΩ
—
V
Note:
1. 2.7 V ≤ VCC < 4.2 V, Topr = −20 to 85 °C (N version), and f(XIN) = 10 MHz, unless otherwise specified.
2. 3.0 V ≤ VCC < 3.6 V for the USB associated pins.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 49 of 56
R8C/3MK Group
Table 5.24
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (4) [2.7 V ≤ VCC < 3.3 V]
(Topr = −20 to 85 °C (N version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 2.7 to 3.3 V) clock mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip
oscillator mode
Low-speed
on-chip
oscillator mode
Wait mode
Stop mode
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO-F = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-16, MSTIIC = MSTTRC = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR27 = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Min.
—
Standard
Typ. Max.
3.5
10
Unit
mA
—
1.5
7.5
mA
—
7.0
15
mA
—
3.0
—
mA
—
4.0
—
mA
—
1.5
—
mA
—
1
—
mA
—
90
390
µA
—
15
90
µA
—
4
80
µA
—
3.5
—
µA
—
2.0
5.0
µA
—
15
—
µA
Page 50 of 56
R8C/3MK Group
5. Electrical Characteristics
Timing requirements
Table 5.25
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V, Topr = 25 °C)
External Clock Input (XOUT)
Symbol
tc(XOUT)
tWH(XOUT)
tWL(XOUT)
Standard
Min.
Max.
50
—
24
—
24
—
Parameter
XOUT input cycle time
XOUT input “H” width
XOUT input “L” width
tC(XOUT)
Unit
ns
ns
ns
VCC = 3 V
tWH(XOUT)
External clock input
tWL(XOUT)
Figure 5.14
Table 5.26
External Clock Input Timing Diagram when VCC = 3 V
TRAIO Input
Symbol
Standard
Min.
Max.
300
—
120
—
120
—
Parameter
tc(TRAIO)
TRAIO input cycle time
tWH(TRAIO) TRAIO input “H” width
tWL(TRAIO) TRAIO input “L” width
tC(TRAIO)
Unit
ns
ns
ns
VCC = 3 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.15
TRAIO Input Timing Diagram when VCC = 3 V
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 51 of 56
R8C/3MK Group
Table 5.27
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
300
—
150
—
150
—
—
80
0
—
70
—
90
—
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi Input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 to 3
tC(CK)
VCC = 3 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 3
Figure 5.16
Table 5.28
Serial Interface Timing Diagram when VCC = 3 V
External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)
tW(INH)
INTi input “H” width, KIi input “H” width
Standard
Min.
Max.
(1)
—
380
tW(INL)
INTi input “L” width, KIi input “L” width
380 (2)
Symbol
Parameter
—
Unit
ns
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
INTi input
(i = 0 to 4)
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.17
tW(INH)
Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi
when VCC = 3 V
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 52 of 56
R8C/3MK Group
Table 5.29
5. Electrical Characteristics
Electrical Characteristics (5) [1.8 V ≤ VCC < 2.7 V]
Symbol
Parameter
VOH
Output “H” voltage
Other than XOUT
VOL
Output “L” voltage
XOUT
Other than XOUT
VT+-VT-
Hysteresis
IIH
IIL
RPULLUP
RfXIN
Input “H” current
Input “L” current
Pull-up resistance
Feedback
resistance
RAM hold voltage
Condition
Drive capacity High
Drive capacity Low
Drive capacity High
Drive capacity Low
XOUT
NT0, INT1, INT2,
INT3, INT4,
KI0, KI1, KI2, KI3,
TRAIO, TRCIOA,
TRCIOB, TRCIOC,
TRCIOD, TRCTRG,
TRCCLK, ADTRG,
RXD0, RXD1, RXD2,
RXD3, CLK0, CLK1,
CLK2, CLK3, CTS2,
SSI, SCL, SDA,
SSO, SSCK, SCS
Min.
IOH = −2 mA
VCC − 0.5
IOH = −1 mA
VCC − 0.5
IOH = −200 µA
1.0
IOL = 2 mA
—
IOL = 1 mA
—
IOL = 200 µA
—
0.05
Max.
VCC
VCC
VCC
0.5
0.5
0.5
—
Unit
V
V
V
V
V
V
V
0.05
0.20
—
V
VI = 2.2 V, VCC = 2.2 V
VI = 0 V, VCC = 2.2 V
VI = 0 V, VCC = 2.2 V
—
—
70
—
—
—
140
0.3
4.0
−4.0
300
—
µA
µA
kΩ
MΩ
During stop mode
1.8
—
—
V
RESET
VRAM
Standard
Typ.
—
—
—
—
—
—
0.20
XIN
Note:
1. 1.8 V ≤ VCC < 2.7 V, Topr = −20 to 85 °C (N version), and f(XIN) = 5 MHz, unless otherwise specified.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 53 of 56
R8C/3MK Group
Table 5.30
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (6) [1.8 V ≤ VCC < 2.7 V]
(Topr = −20 to 85 °C (N version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 1.8 to 2.7 V) clock mode
Single-chip mode,
output pins are open,
other pins are VSS
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
Min.
—
Standard
Typ. Max.
2.2
—
Unit
mA
—
0.8
—
mA
XIN clock off
High-speed
High-speed on-chip oscillator on fOCO-F = 5 MHz
on-chip
oscillator mode Low-speed on-chip oscillator on = 125 kHz
—
2.5
10
mA
XIN clock off
High-speed on-chip oscillator on fOCO-F = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
—
1.7
—
mA
XIN clock off
High-speed on-chip oscillator on fOCO-F = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-16, MSTIIC = MSTTRC = 1
—
1
—
mA
XIN clock off
Low-speed
High-speed on-chip oscillator off
on-chip
oscillator mode Low-speed on-chip oscillator on = 125 kHz
—
90
300
µA
Wait mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
—
15
90
µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
—
4
80
µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
—
3.5
—
µA
XIN clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
—
2.0
5
µA
XIN clock off, Topr = 85 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
—
15
—
µA
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
No division
Divide-by-8, FMR27 = 1, VCA20 = 0
Stop mode
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 54 of 56
R8C/3MK Group
5. Electrical Characteristics
Timing requirements
Table 5.31
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V, Topr = 25 °C)
External Clock Input (XOUT)
Symbol
tc(XOUT)
tWH(XOUT)
tWL(XOUT)
Standard
Min.
Max.
200
—
90
—
90
—
Parameter
XOUT input cycle time
XOUT input “H” width
XOUT input “L” width
tC(XOUT)
Unit
ns
ns
ns
VCC = 2.2 V
tWH(XOUT)
External clock input
tWL(XOUT)
Figure 5.18
Table 5.32
External Clock Input Timing Diagram when VCC = 2.2 V
TRAIO Input
Symbol
Standard
Min.
Max.
500
—
200
—
200
—
Parameter
tc(TRAIO)
TRAIO input cycle time
tWH(TRAIO) TRAIO input “H” width
tWL(TRAIO) TRAIO input “L” width
tC(TRAIO)
Unit
ns
ns
ns
VCC = 2.2 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.19
TRAIO Input Timing Diagram when VCC = 2.2 V
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 55 of 56
R8C/3MK Group
Table 5.33
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
800
—
400
—
400
—
—
200
0
—
150
—
90
—
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 to 3
tC(CK)
VCC = 2.2 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 3
Figure 5.20
Table 5.34
Serial Interface Timing Diagram when VCC = 2.2 V
External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)
INTi input “H” width, KIi input “H” width
Standard
Min.
Max.
—
1000 (1)
INTi input “L” width, KIi input “L” width
1000 (2)
Symbol
tW(INH)
tW(INL)
Parameter
—
Unit
ns
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
INTi input
(i = 0 to 4)
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.21
tW(INH)
Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi
when VCC = 2.2 V
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 56 of 56
R8C/3MK Group
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Electronics website.
R01DS0038EJ0100 Rev.1.00
Feb 25, 2011
Page 56 of 56
REVISION HISTORY
Rev.
Date
0.01
0.02
Jun 30, 2010
Nov 08, 2010
1.00
Feb 25, 2011
R8C/3MK Group Datasheet
Description
Summary
Page
—
All
First Edition issued
Package code: “PWQN0040KB-A (previous code: 40PJS-A)”
→ “PWQN0040KB-B (previous code: 40PJS-B)”
2
Table 1.1 I/O Ports, DTC revised
LIN Module added
3
Table 1.2 A/D converter, Package revised
4
Table 1.3 “(D)”added
Table 1.3, Figure 1.1 Package revised
5
Figure 1.2 I/O Ports, A/D converter revised
LIN Module added
6
Figure 1.3 revised
7
Table 1.4 Pin Number 2, 7, 9, 22 revised
9
Table 1.6 USB “USB_OVRCURA” added
14
Table 4.1 0026h “On-Chip Reference Voltage Control Register
OCVREFCR 00h” added
15
Table 4.2 004Ah deleted
Table 4.3 00BBh “UART2 Special Mode Register 5 U2SMR5 XXh”
16
added
00BDh “UART2 Special Mode Register 3 U2SMR3
000X0X0Xb2” added
18
Table 4.5 0105h “LIN Control Register 2 LINCR2 00h” added
0106h “LIN Control Register LINCR 00h” added
0107h “LIN Status Register LINST 00h” added
Table 4.12 2E02h, 2E03h deleted
25
29
Package Dimensions added
All pages “Preliminary”, “Under development” deleted
3
Table 1.2 revised
4
Table 1.3, Figure 1.1 revised
5
Figure 1.2 revised
6
Figure 1.3 revised
7
Table 1.4 revised
9
Table 1.6 revised
13
3.1 revised, Figure 3.1 “Part Number” added
14
Table 4.1 0026h revised
15
Table 4.2 0041h revised
16
Table 4.3 00BBh revised
20
Table 4.7 0181h revised
25
Table 4.12 2E04h and 2E05h revised
26
Table 4.13 2E40h to 2E43h revised
27
Table 4.14 2ED2h to 2ED7h deleted
28
Table 4.15 2F04h, 2F11h and 2F13h deleted, 2F10h added
29 to 56 5. Electrical Characteristics added
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C-1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
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(Note 1)
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(Note 2)
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