SFC05-4 CSP TVS Flip Chip TVS Diode Array PRELIMINARY PROTECTION PRODUCTS Description Features u 300 Watts peak pulse power (tp = 8/20µs) u Transient protection for data lines to The SFC05-4 is a quad flip chip CSP TVS diode array. They are state-of-the-art devices that utilize solid-state silicon-avalanche technology for superior clamping performance and DC electrical characteristics. The SFC series TVS diodes are designed to protect sensitive semiconductor components from damage or latchup due to electrostatic discharge (ESD) and other voltage induced transient events. u u u u u u u The SFC05-4 is a 6-bump, 0.5mm pitch flip chip array with a 3x2 bump grid. It measures 1.5 x 1.0 x 0.65mm. This small outline makes the SFC05-4 especially well suited for portable applications. CSP TVS devices are compatible with current pick and place equipment and assembly methods. IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 24A (8/20µs) Small chip scale package requires less board space Low profile (< 0.65mm) No need for underfill material Protects four I/O or data lines Low clamping voltage Working voltage: 5V Solid-state silicon-avalanche technology Mechanical Characteristics u JEDEC MO-211, Variation BB, 0.50 mm Pitch Chip Scale Package (CSP) Each device will protect up to four data or I/O lines. The CSP design results in lower inductance, virtually eliminating voltage overshoot due to leads and interconnecting bond wires. They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (15kV air, 8kV contact discharge). u Marking : Marking Code u Packaging : Tape and Reel Applications u u u u u u u u Device Dimensions Cell Phone Handsets and Accessories Personal Digital Assistants (PDAs) Notebook & Hand Held Computers Portable Instrumentation Pagers Smart Cards MP3 Players GPS Schematic & PIN Configuration 1.50 B 0.50 1.00 0.50 TYP A 0.65 1 0.150 SFC05-4 Maximum Dimensions (mm) Revision 12/18/2000 2 3 3 x 2 Grid CSP TVS (Bottom View) 1 www.semtech.com SFC05-4 PRELIMINARY PROTECTION PRODUCTS Absolute Maximum Rating R ating Symbo l Value Units Peak Pulse Pow er (tp = 8/20ms) Pp k 300 Watts Peak Pulse Current (tp = 8/20ms) I PP 24 A ESD p er IEC 61000-4-2 (Air) ESD p er IEC 61000-4-2 (Contact) V ESD >25 >15 kV Soldering Temp erature TL 260 (10 seconds) o Op erating Temp erature TJ -55 to +125 o TSTG -55 to +150 o Storage Temp erature C C C Electrical Characteristics SFC05-4 fo r 5V Line s Par ame te r Symbo l Co nd itio ns Minimum Typ ical Maximum Units 5 V Reverse Stand-Off Voltage V RWM Reverse Breakdow n Voltage V BR It = 1mA Reverse Leakage Current IR VRWM = 5V, T=25°C 10 µA Clamp ing Voltage VC IPP = 5A, tp = 8/20µs 9.5 V Clamp ing Voltage VC IPP = 24A, tp = 8/20µs 11 V Junction Cap acitance Cj VR = 0V, f = 1MHz 350 pF ã 2000 Semtech Corp. 2 6 V www.semtech.com SFC05-4 PRELIMINARY PROTECTION PRODUCTS Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve 10 110 % of Rated Power or IPP Peak Pulse Power - PPP (kW) 100 1 0.1 90 80 70 60 50 40 30 20 10 0 0.01 0.1 1 10 100 0 1000 25 50 Pulse Duration - tp (µ s) Pulse Waveform 100 125 150 Clamping Voltage vs. Peak Pulse Current 110 10.00 Waveform Parameters: tr = 8µs td = 20µs 90 80 70 e 60 9.00 Clamping Voltage - Vc (V) 100 Percent of IPP 75 Ambient Temperature - TA (oC) -t 50 40 td = IPP/2 30 20 10 8.00 7.00 6.00 5.00 4.00 Waveform Parameters: tr = 8µs td = 20µs 3.00 2.00 1.00 0 0 5 10 15 20 25 0.00 30 0 Time (µs) 5 10 15 20 25 30 Peak Pulse Current - Ipp (A) ESD Clamping (8kV Contact Discharge) ã 2000 Semtech Corp. 3 www.semtech.com SFC05-4 PRELIMINARY PROTECTION PRODUCTS Applications Information Device Schematic & Pin Configuration Device Connection Options The SFC05-4 has solder bumps located in a 3 x 2 matrix layout on the active side of the device. The bumps are designated by the numbers 1 - 3 along the horizontal axis and letters A - B along the vertical axis. The lines to be protected are connected at bumps A1, B1, A3, and B3. Bumps A2 & B2 are connected to ground. All path lengths should be kept as short as possible to minimize the effects of parasitic inductance in the board traces. B A 2 1 3 Wafer Level CSP TVS CSP TVS devices are wafer level chip scale packages. They eliminate external plastic packages and leads and thus result in a significant board space savings. Manufacturing costs are minimized since they do not require an intermediate level interconnect or interposer layer for reliable operation. They are compatible with current pick and place equipment further reducing manufacturing costs. Certain precautions and design considerations have to be observed however for maximum solder joint reliability. These include solder pad definition, board finish, and assembly parameters. Layout Example To Protected IC To Protected IC Ground Printed Circuit Board Mounting Non-solder mask defined (NSMD) land patterns are recommended for mounting the SFC05-4. Solder mask defined (SMD) pads produce stress points near the solder mask on the PCB side that can result in solder joint cracking when exposed to extreme fatigue conditions. The recommended pad size is 0.200 ± 10 mm with a solder mask opening of 0.350 ± 0.025 mm. To Connector NSMD Package Footprint Grid Courtyard The recommended grid placement courtyard is 1.3 x 1.8 mm. The grid courtyard is intended to encompass the land pattern and the component body that is centered in the land pattern. When placing parts on a PCB, the highest recommended density is when one courtyard touches another. ã 2000 Semtech Corp. 4 www.semtech.com SFC05-4 PRELIMINARY PROTECTION PRODUCTS Applications Information (Continued) Printed Circuit Board Finish A uniform board finish is critical for good assembly yield. Two finishes that provide uniform surface coatings are immersion nickel gold and organic surface protectant (OSP). A non-uniform finish such as hot air solder leveling (HASL) can lead to mounting problems and should be avoided. Stencil Design Stencil Design A properly designed stencil is key to achieving adequate solder volume without compromising assembly yields. A 0.100mm thick, laser cut, electro-polished stencil with 0.275mm square apertures and rounded corners is recommended. Reflow Profile The flip chip TVS can be assembled using standard SMT reflow processes. As with any component, thermal profiles at specific board locations can vary & must be determined by the manufacturer. The flip chip TVS peak reflow temperature is 230 ± 10 °C, but the device can withstand up to 260 °C peak reflow temperature. Time above eutectic temperature (183 °C) should be 50 ± 10 seconds. During reflow, the component self-aligns itself on the pad. Reflow Profile Circuit Board Layout Recommendations for Suppression of ESD Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: l l l l l l Place the TVS near the input terminals or connectors to restrict transient coupling. Minimize the path length between the TVS and the protected line. Minimize all conductive loops including power and ground loops. The ESD transient return path to ground should be kept as short as possible. Never run critical signals near board edges. Use ground planes whenever possible. ã 2000 Semtech Corp. 5 www.semtech.com SFC05-4 PRELIMINARY PROTECTION PRODUCTS Outline Drawing - SFC05-4 Land Pattern - SFC05-4 ã 2000 Semtech Corp. 6 www.semtech.com SFC05-4 PRELIMINARY PROTECTION PRODUCTS Marking Codes Par t Numbe r Mar king Co d e SFC05-4 F45U Ordering Information P ar t Numbe r Wo r king Vo ltage Qty p e r Reel R e e l Size SFC05-4.TM 5V 6,000 7 Inch Contact Information Semtech Corporation Protection Products Division 652 Mitchell Rd., Newbury Park, CA 91320 Phone: (805)498-2111 FAX (805)498-3804 ã 2000 Semtech Corp. 7 www.semtech.com