SFC3.3-4 Low Voltage ChipClampΤΜ Flip Chip TVS Diode Array PROTECTION PRODUCTS Description Features 150 Watts peak pulse power (tp = 8/20µs) Transient protection for data lines to The SFC3.3-4 is a quad flip chip TVS diode array. They are state-of-the-art devices that utilize solid-state EPD TVS technology for superior clamping performance and DC electrical characteristics. The SFC series TVS diodes are designed to protect sensitive semiconductor components from damage or latch-up due to electrostatic discharge (ESD) and other voltage induced transient events. The SFC3.3-4 is a 6-bump, 0.5mm pitch flip chip array with a 3x2 bump grid. It measures approximately 1.5 by 1.0 mm. It has a very low profile of < 0.65 mm. This is a crucial specification for many portable applications. Each device will protect up to four data or I/O lines. The flip chip design results in lower inductance, virtually eliminating voltage overshoot due to leads and interconnecting bond wires. IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 12A (8/20µs) Small chip scale package requires less board space Low profile (< 0.65mm) No need for underfill material Protects four I/O or data lines Low clamping voltage Working voltage: 3.3V Solid-state EPD TVS technology Mechanical Characteristics The devices are constructed using Semtech’s proprietary EPD process technology. The EPD process provides low standoff voltages with significant reductions in leakage currents and capacitance over siliconavalanche diode processes. JEDEC MO-211, 0.50 mm Flip Chip Package Non-conductive top side coating Marking : Marking Code Packaging : Tape and Reel Applications They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (±15kV air, ±8kV contact discharge). Device Dimensions Cell Phone Handsets and Accessories Personal Digital Assistants (PDAs) Notebook and Hand Held Computers Portable Instrumentation Pagers Smart Cards MP3 Players Schematic & PIN Configuration B A 1 SFC3.3-4 Maximum Dimensions (mm) Revision 11/13/2008 2 3 3 x 2 Grid Flip Chip TVS (Bottom View) 1 www.semtech.com SFC3.3-4 PRELIMINARY PROTECTION PRODUCTS Absolute Maximum Rating R ating Symbol Value Units Peak Pulse Power (tp = 8/20µs) Pp k 150 Watts Peak Pulse Current (tp = 8/20µs) IP P 15 A ESD per IEC 61000-4-2 (Air) ESD per IEC 61000-4-2 (Contact) VESD >25 >15 kV TJ -55 to +125 °C TSTG -55 to +150 °C Operating Temperature Storage Temperature Electrical Characteristics (T=25oC) Parameter Reverse Stand-Off Voltage Symbol Conditions Minimum Typical VRWM Maximum Units 3.3 V Punch-Through Voltage V PT IPT = 2µA 3.5 V Snap -Back Voltage VSB ISB = 50mA 2.8 V Reverse Leakage Current IR VRWM = 3.3V, T=25°C Clamp ing Voltage VC Clamp ing Voltage 0.5 µA IPP = 1A, tp = 8/20µs Any I/O to Ground 4.5 V VC IPP = 5A, tp = 8/20µs Any I/O to Ground 6.8 V Clamp ing Voltage VC IPP = 15A, tp = 8/20µs Any I/O to Ground 9.5 V Forward Clamp ing Voltage VF IPP = 1A, tp = 8/20µs Ground to any I/O 1.7 V Junction Cap acitance Cj Each I/O p in and Ground VR = 0V, f = 1MHz 100 pF 2008 Semtech Corp. 2 0.05 75 www.semtech.com SFC3.3-4 PRELIMINARY PROTECTION PRODUCTS Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve 10 110 % of Rated Power or PI P Peak Pulse Power - Ppk (kW) 100 1 0.1 90 80 70 60 50 40 30 20 10 0 0.01 0.1 1 10 100 0 1000 25 50 Pulse Waveform 12.00 90 80 e 60 Clamping Voltage - VC (V) Waveform Parameters: tr = 8µs td = 20µs 100 70 -t 50 40 100 125 td = IPP/2 30 20 10 L to L 10.00 L to G 8.00 6.00 4.00 Waveform Parameters: tr = 8µs td = 20µs 2.00 0 0 5 10 15 150 Clamping Voltage vs. Peak Pulse Current 110 Percent of IPP 75 Ambient Temperature - TA (oC) Pulse Duration - tp (µs) 20 25 30 0.00 Time (µs) 0 5 10 15 20 Peak Pulse Current - IPP (A) Normalized Junction Capacitance vs. Reverse Voltage Forward Voltage vs. Forward Current 4.00 1.5 1.4 1.2 3.00 1.1 CJ(VR) / CJ(VR=0) Clamping Voltage - VC (V) 1.3 2.00 Waveform Parameters: tr = 8µs td = 20µs 1.00 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.00 0 5 10 15 20 0 Peak Pulse Current - IPP (A) 2008 Semtech Corp. f = 1 MHz 0 3 1 2 Reverse Voltage - VR (V) 3 4 www.semtech.com SFC3.3-4 PRELIMINARY PROTECTION PRODUCTS Applications Information Device Schematic and Pin Configuration Device Connection Options The SFC3.3-4 has solder bumps located in a 3 x 2 matrix layout on the active side of the device. The bumps are designated by the numbers 1 - 3 along the horizontal axis and letters A - B along the vertical axis. The lines to be protected are connected at bumps A1, B1, A3, and B3. Bumps A2 and B2 are connected to ground. All path lengths should be kept as short as possible to minimize the effects of parasitic inductance in the board traces. Due to the “snap-back” characteristics of the low voltage TVS, it is not recommended that any of the I/O bumps be directly connected to a DC source greater than snap-back votlage (VSB) as the device can latch on as described the EPD TVS characteristics section. 6 5 4 1 2 3 B A Layout Example To Protected IC Flip Chip TVS To Protected IC Ground Flip chip TVS devices are wafer level chip scale packages. They eliminate external plastic packages and leads and thus result in a significant board space savings. Manufacturing costs are minimized since they do not require an intermediate level interconnect or interposer layer for reliable operation. They are compatible with current pick and place equipment further reducing manufacturing costs. Certain precautions and design considerations have to be observed however for maximum solder joint reliability. These include solder pad definition, board finish, and assembly parameters. To Connector NSMD Package Footprint Printed Circuit Board Mounting Non-solder mask defined (NSMD) land patterns are recommended for mounting the SFC3.3-4. Solder mask defined (SMD) pads produce stress points near the solder mask on the PCB side that can result in solder joint cracking when exposed to extreme fatigue conditions. The recommended pad size is 0.225 ± 0.010 mm with a solder mask opening of 0.350 ± 0.025 mm. Printed Circuit Board Finish A uniform board finish is critical for good assembly yield. Two finishes that provide uniform surface coatings are immersion nickel gold and organic surface protectant (OSP). A non-uniform finish such as hot air solder leveling (HASL) can lead to mounting problems 2008 Semtech Corp. 4 www.semtech.com SFC3.3-4 PRELIMINARY PROTECTION PRODUCTS and should be avoided. Stencil Design Stencil Design A properly designed stencil is key to achieving adequate solder volume without compromising assembly yields. A 0.100mm thick, laser cut, electro-polished stencil with 0.275mm square apertures and rounded corners is recommended. Reflow Profile The flip chip TVS can be assembled using the reflow requirements for IPC/JEDEC standard J-STD-020 for assembly of small body components. During reflow, the component will self-align itself on the pad. EPD TVS Characteristics Assembly Guideline for Pb-Free Soldering The following are recommendations for the assembly of this device: The SFC3.3-4 is constructed using Semtech’s proprietary EPD technology. The structure of the EPD TVS is vastly different from the traditional pn-junction devices. At voltages below 5V, high leakage current and junction capacitance render conventional avalanche technology impractical for most applications. However, by utilizing the EPD technology, the SFC3.3-4 can effectively operate at 3.3V while maintaining excellent electrical characteristics. Assembly Parameter Solder Ball Composition Solder Stencil Design The EPD TVS employs a complex nppn structure in contrast to the pn structure normally found in traditional silicon-avalanche TVS diodes. Since the EPD TVS devices use a 4-layer structure, they exhibit a slightly different IV characteristic curve when compared to conventional devices. During normal operation, the device represents a high-impedance to the circuit up to the device working voltage (VRWM). During an ESD event, the device will begin to conduct and will enter a low impedance state when the punch through voltage (VPT) is exceeded. Unlike a conventional device, the low voltage TVS will exhibit a slight negative resistance characteristic as it conducts current. This characteristic aids in lowering the clamping voltage of the device, but must be considered in applications where DC voltages are present. 95.5Sn/3.8Ag/0.7Cu Same as the SnPb design Solder Stencil Thickness 0.100 mm (0.004") Solder Paste Composition Sn Ag (3-4) Cu (0.5-0.9) Solder Paste Type Solder Reflow Profile PCB Solder Pad Design PCB Pad Finish Type 4 size sphere or smaller per JEDEC J-STD-020 Same as the SnPb Design OSP or AuN i current through the device must fall below the ISB (approximately <50mA) and the voltage must fall below the VSB (normally 2.8 volts for a 3.3V device). If a 3.3V TVS is connected to 3.3V DC source, it will never fall below the snap-back voltage of 2.8V and will therefore stay in a conducting state. When the TVS is conducting current, it will exhibit a slight “snap-back” or negative resistance characteristics due to its structures. This point is defined on the curve by the snap-back voltage (VSB) and snap-back current (ISB). To return to a non-conducting state, the 2008 Semtech Corp. R ecommendation The SFC3.3-4 is the first device to combine the advantages of flip chip technology with those of the EPD process technology. 5 www.semtech.com SFC3.3-4 PRELIMINARY PROTECTION PRODUCTS Outline Drawing - 3x2 Grid Flip Chip B 1.47±0.03 A INDEX AREA A1 CORNER 0.97±0.03 0.10 C 0.40-0.60 0.50-0.75 C 3. 0.05 C 0.50 0.150±0.025 6X Ø0.175-0.225 0.05 C A B B 0.50 A 1 2 3 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS 2. REFERENCE JEDEC REGISTRATION MO-211. 3. Sn95.5/Ag3.8/Cu0.7 FOR Pb-FREE DEVICES. Land Pattern - 3x2 Grid Flip Chip 0.50 TYP CL CL 0.50 TYP 6X Ø0.225 NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2008 Semtech Corp. 6 www.semtech.com SFC3.3-4 PRELIMINARY PROTECTION PRODUCTS Marking Codes Part Number Marking Code SFC3.3-4 F43U Ordering Information Part Number SFC3.3-4.BCT (1) Pitch Option Qty per Reel R eel Size 2mm 3,000 7 Inch Notes (1) Lead Free Solder Balls Top Coating: The top (non-bump side) of the device is a black non-conductive coating. This material is compliant with UL 94V-0 flammability requirements. ChipClamp is a mark of Semtech Corporation Tape and Reel Specification Pin A1 Tape Specifications Device Orientation Contact Information Semtech Corporation Protection Products Division 200 Flynn Rd., Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2008 Semtech Corp. 7 www.semtech.com