FAIRCHILD SFF9250L

SFF9250L
Advanced Power MOSFET
FEATURES
BVDSS = -200 V
❑ Logic-Level Gate Drive
RDS(on) = 0.23 Ω
❑ Avalanche Rugged Technology
❑ Rugged Gate Oxide Technology
ID = -12.6 A
❑ Lower Input Capacitances
❑ Improved Gate Charge
❑ Extended Safe Operating Area
❑ Lower Leakage Current : 10uA (Max.) @ VDS=-200V
TO-3PF
❑ Lower RDS(ON) : 0.175 Ω (Typ.)
1
2
3
1.Gate 2. Drain 3. Source
Absolute Maximum Ratings
Symbol
VDSS
ID
Characteristic
Drain-to-Source Voltage
Value
Units
-200
V
Continuous Drain Current (TC=25 °C)
-12.6
Continuous Drain Current (TC=100 °C)
-7.9
①
A
IDM
Drain Current-Pulsed
VGS
Gate-to-Source Voltage
EAS
Single Pulsed Avalanche Energy
②
IAR
Avalanche Current
①
EAR
Repetitive Avalanche Energy
①
20.4
mJ
dv/dt
Peak Diode Recovery dv/dt
③
-5.0
V/ns
90
W
0.72
W/ °C
PD
Total Power Dissipation (TC=25 °C)
Linear Derating Factor
Operating Junction and
TJ , TSTG
A
±20
V
990
mJ
-12.6
A
- 55 to +150
Storage Temperature Range
°C
Maximum Lead Temp. for Soldering
TL
-50.4
300
Purposes, 1/8″ from case for 5-seconds
Thermal Resistance
Symbol
Characteristic
Typ.
Max.
RθJC
Junction-to-Case
--
0.61
RθJA
Junction-to-Ambient
--
40
Units
°C /W
Rev. A
P-CHANNEL
POWER MOSFET
SFF9250L
Electrical Characteristics (TC=25°C unless otherwise specified)
Symbol
Characteristic
BVDSS
Drain-Source Breakdown Voltage
-200
--
ΔBV/ΔTJ
Breakdown Voltage Temp. Coeff.
--
-0.17
--
VGS(th)
IGSS
IDSS
RDS(on)
Min. Typ. Max. Units
Gate Threshold Voltage
-1.0
--
-2.0
Gate-Source Leakage , Forward
--
--
100
Gate-Source Leakage , Reverse
--
--
-100
--
--
10
--
--
100
Drain-to-Source Leakage Current
V
--
--
V
nA
μA
.175 0.23
gfs
Forward Transconductance
--
Ciss
Input Capacitance
--
2500 3250
Coss
Output Capacitance
--
400 520
Crss
Reverse Transfer Capacitance
--
210 270
td(on)
Turn-On Delay Time
--
20
Rise Time
--
150 310
Turn-Off Delay Time
--
100 210
Fall Time
--
65
140
Qg
Total Gate Charge
--
90
120
Qgs
Gate-Source Charge
--
12
--
Qgd
Gate-Drain(Miller) Charge
--
54
--
tr
td(off)
tf
13
VGS=0V,ID=-250μA
V/ °C ID=-250μA
Static Drain-Source
On-State Resistance
Test Condition
--
See Fig 7
VDS=-5V,ID=-250μA
VGS=-20V
VGS=20V
VDS=-200V
VDS=-160V,TC=125 °C
Ω
VGS=-5V,ID=-6.3A
④
S
VDS=-40V,ID=-6.3A
④
pF
50
VGS=0V,VDS=-25V,f =1MHz
See Fig 5
VDD=-100V,ID=-12.6A,
ns
RG=6.2Ω
④⑤
See Fig 13
VDS=-160V,VGS=-5V,
nC
ID=-12.6A
See Fig 6 & Fig 12 ④ ⑤
Source-Drain Diode Ratings and Characteristics
Symbol
IS
Characteristic
Min. Typ. Max. Units
Continuous Source Current
--
--
-12.6
-50.4
A
Test Condition
Integral reverse pn-diode
ISM
Pulsed-Source Current
①
--
--
VSD
Diode Forward Voltage
④
--
--
-1.5
trr
Reverse Recovery Time
--
260
--
ns TJ=25 °C,IF=-19.5A,VDD=-160V
--
2.8
--
μC diF/dt=100A/μs
Qrr
Reverse Recovery Charge
V
in the MOSFET
TJ=25 °C,IS=-12.6A,VGS=0V
Notes ;
① Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
② L=3.9mH, IAS=-19.5A, VDD=-50V, RG=27Ω, Starting TJ =25℃
③ ISD≤-19.5A, di/dt≤500A/μs, VDD≤BVDSS , Starting TJ =25℃
④ Pulse Test : Pulse Width ≤ 300μs, Duty Cycle ≤ 2%
⑤ Essentially Independent of Operating Temperature
④
P-CHANNEL
POWER MOSFET
SFF9250L
Fig 2. Transfer Characteristics
1
10
-I D , Drain Current [A]
-I D, Drain Current [A]
Fig 1. Output Characteristics
VGS
Top :
-10.0 V
-8.0 V
-6.0 V
-5.0 V
-4.5 V
-4.0 V
-3.5 V
Bottom : -3.0 V
0
10
1
10
150℃
0
10
25℃
-55℃
※ Note
1. VDS = -40V
2. 250μ s Pulse Test
※ Note :
1. 250μ s Pulse Test
2. TC = 25℃
-1
10
-1
0
10
2
1
10
10
4
6
8
10
-VDS, Drain-Source Voltage [V]
-VGS , Gate-Source Voltage [V]
Fig 3. On-Resistance vs. Drain Current
Fig 4. Source-Drain Diode Forward Voltage
-I DR , Reverse Drain Current [A]
RDS(on) , [ Ω ]
Drain-Source On-Resistance
0.8
0.6
VGS = - 5V
0.4
VGS = - 10V
0.2
1
10
0
10
150℃ 25℃
※ Note :
1. VGS = 0V
2. 250μ s Pulse Test
※ Note : TJ = 25℃
-1
0.0
0
20
40
60
80
100
10
0.6
1.2
1.8
2.4
3.0
3.6
-ID , Drain Current [A]
-VSD , Source-Drain Voltage [V]
Fig 5. Capacitance vs. Drain-Source Voltage
Fig 6. Gate Charge vs. Gate-Source Voltage
12000
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
10500
6000
4500
Ciss
3000
Coss
Crss
※ Note ;
1. VGS = 0 V
2. f = 1 MHz
1500
-VGS, Gate-Source Voltage [V]
Capacitances [pF]
7500
0
-1
10
6
VDS = -40V
9000
VDS = -100V
VDS = -160V
4
2
※ Note : ID = -19.5 A
0
0
10
1
10
-VDS, Drain-Source Voltage [V]
0
20
40
60
QG, Total Gate Charge [nC]
80
100
P-CHANNEL
POWER MOSFET
SFF9250L
Fig 7. Breakdown Voltage vs. Temperature
Fig 8. On-Resistance vs. Temperature
2.5
1.1
1.0
※ Note :
1. VGS = 0 V
2. ID = -250 μ A
0.9
0.8
-100
-50
0
50
100
150
2.0
RDS(ON) , (Normalized)
Drain-Source On-Resistance
-BV DSS , (Normalized)
Drain-Source Breakdown Voltage
1.2
1.5
1.0
※ Note :
1. VGS = -5 V
2. ID = -9.8 A
0.5
0.0
-100
200
-50
0
o
50
100
150
200
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Fig 9. Max. Safe Operating Area
Fig 10. Max. Drain Current vs. Case Temperature
20
Operation in This Area
is Limited by R DS(on)
2
15
-I D, Drain Current [A]
100 µs
1 ms
10 ms
1
10
DC
0
10
※ Notes :
10
5
o
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
-1
0
1
10
0
25
2
10
10
50
75
100
TC, Case Temperature [℃]
-VDS, Drain-Source Voltage [V]
Fig 11. Thermal Response
( t) , T h e r m a l R e s p o n s e
10
0
D = 0 .5
※ N o te s :
1 . Z θ J C( t ) = 0 . 6 1 ℃ / W M a x .
2 . D u ty F a c to r, D = t1/t2
3 . T J M - T C = P D M * Z θ J C( t )
0 .2
10
-1
0 .1
0 .0 5
PDM
0 .0 2
θ JC
10
t1
0 .0 1
Z
-I D, Drain Current [A]
10
10
10
t2
s in g le p u ls e
-2
-5
10
-4
10
-3
10
-2
10
-1
t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
10
0
10
1
125
150
P-CHANNEL
POWER MOSFET
SFF9250L
Fig 12. Gate Charge Test Circuit & Waveform
50KΩ
12V
VGS
Same Type
as DUT
Qg
200nF
-5V
300nF
VDS
VGS
Qgs
Qgd
DUT
-3mA
Charge
Fig 13. Resistive Switching Test Circuit & Waveforms
RL
VDS
t on
td(on)
VDD
RG
( 0.5 rated VDS )
Vin
t off
tr
td(off)
tf
10%
DUT
-5V
VDS
90%
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- LL IAS2 -------------------2
BVDSS -- VDD
L
VDS
VDD
tp
ID
VDD
RG
VDS (t)
ID (t)
-5V
DUT
IAS
BVDSS
Time
P-CHANNEL
POWER MOSFET
SFF9250L
Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
IS
L
Driver
RG
VGS
VGS
( Driver )
Compliment of DUT
(N-Channel)
VDD
• dv/dt controlled by RG
• IS controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
5V
IFM , Body Diode Forward Current
IS
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
Vf
Body Diode
Forward Voltage Drop
VDD
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effectiveness.
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4