CADEKA SPT1175ACU

SPT1175
8-BIT, 20 MSPS CMOS A/D CONVERTER
FEATURES
APPLICATIONS
•
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•
•
•
•
•
•
•
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20 MSPS Maximum Conversion Rate
Internal Sample-and-Hold Function
90 mW Power Dissipation
Internal Voltage Reference
Single +5.0 V Power Supply
Three-State TTL-Outputs
CMOS Compatible Clock
Video Digitizing
Image Scanners
Personal Computer Video
Medical Ultrasound
Multimedia
Digital Television
GENERAL DESCRIPTION
The SPT1175 is a CMOS two-step A/D converter capable of
digitizing full scale analog input signals into 8-bit digital words
at a sample rate of 20 MSPS.
For most applications, no external sample-and-hold or
video driving amplifiers are required due to the device's
narrow aperture time, wide bandwidth, and low input capacitance.
The SPT1175 operates from a single +5.0 V power supply
and has an internal voltage reference which eliminates the
need for external reference circuitry. All digital inputs are
CMOS compatible and the tri-state outputs are TTL-compatible. The SPT1175 is ideal for most video and image processing applications that require low power dissipation and
low cost. The SPT1175 is available in 24-lead plastic SOIC,
plastic DIP, and PLCC packages over the commercial temperature range (0 to +70 °C). It is also available in die form.
BLOCK DIAGRAM
VRB
VRBS
DVDD
DGND
OE
Coarse
Sampling
Amplifier
Latch
Encoder
DØ (LSB)
D1
Error
Correction
Circuit
Reference Matrix
VIN
Data
Latches
and
3-State
Output
Buffer
D2
D3
D4
D5
D6
Fine
Sampling
Amplifier
Fine
Sampling
Amplifier
D7 (MSB)
Encoder
Analog
Mux
Latch
Timing
Generator
VRT
VRTS
AGND AVD
DVDD
CLK
AGND
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)(1) 25 °C
Supply Voltages
VDD ........................................................... -0.5 to +7.0 V
Input Voltages
Analog Input .............................................. AGND to VDD
Reference Input Voltage ........................... AGND to VDD
ESD Susceptibility(2) ................................................. ±1,500 V
Temperature
Operating Temperature ................................. 0 to +70 °C
Junction Temperature ........................................... 175 °C
Lead Temperature, (soldering 10 seconds) .......... 300 °C
Storage Temperature ................................ -55 to +125 °C
Notes: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
2. 100 pF discharged through a 1.5 kΩ resistor (human body model).
ELECTRICAL SPECIFICATIONS
TA= +25 °C, AVDD=DVDD=+5.0 V, AGND=DGND=0.0 V, VRB=+0.6 V and VRT=+2.6 V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
Resolution
UNITS
±1.2
±1.0
LSB
LSB
VRT
±5.0
V
µA
kΩ
pF
MHz
I
I
VI
V
V
VRB
I
I
IV
IV
I
I
200
5.0
0
0.55
1.9
300
6.7
0.6
2.6
0.60
2.0
400
10.0
2.8
0.65
2.1
Ω
mA
V
V
V
V
I
I
-18
0
-25
10
-68
40
mV
mV
20
30
18
(High Z)
I
IV
IV
30
100
MSPS
ns
ns
Tri-State Circuit
IV
100
ns
10
ns
VRB
VRT
VRB
VRT-VRB
Short VRT and VRTS
Short VRB and VRBS
Offset Voltage Error
Top
Bottom
Timing Characteristics
Maximum Conversion Rate
Output Data Delay (td)
Output Data Delay
(Tdish, Tdisl)
Data Valid Time
(Teneh, Tenel)
Sampling Time Offset
MAX
Bits
±0.8
±0.6
Guaranteed
I
I
I
Analog Input
Input Voltage Range
Input Bias Current
Input Resistance
Input Capacitance
Input Bandwidth
Internal Bias
SPT1175
TYP
8
DC Accuracy (+25 °C)
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
Reference Input
Reference Ladder Resistance
Reference Current
Reference Input Voltage
MIN
1 MHz Input Sine Wave
IV
100
200
15
12
5
NOTE: It is strongly recommended that all of the supply pins (AVDD, DVDD) be powered from the same source.
SPT1175
2
6/24/97
ELECTRICAL SPECIFICATIONS
TA=+25 °C, AVDD=DVDD=+5.0 V, AGND=DGND=0.0 V, VRB=+0.6 V and VRT=+2.6 V, unless otherwise specified.
PARAMETERS
Dynamic Performance
Signal-To-Noise Ratio
fIN=1.0 MHz
fIN=3.58 MHz
fIN=10 MHz
Spurious Free
Dynamic Range
fIN=1.0 MHz
fIN=3.58 MHz
fIN=10 MHz
Differential Phase
Differential Gain
Digital Inputs
Input Current, Logic High
Input Current, Logic Low
Pulse Width High (CLK)
Pulse Width Low (CLK)
Voltage, Logic High
Voltage, Logic Low
Digital Outputs
Output Current, High
Output Current, Low
Output Current, High Z
Voltage High
Voltage Low
Power Supply Requirements
Analog Supply Voltage (AVDD)
Digital Supply Voltage (DVDD)
Supply Voltage Difference
Supply Current
Power Dissipation
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT1175
TYP
MAX
UNITS
fS= 20 MSPS
I
I
V
44
43
46
45
39
dB
dB
dB
I
I
V
V
V
44
41
47
44
33
0.7
1.0
dB
dB
dB
Degrees
%
fS= 20 MSPS
NTSC 20 IRE Mod Ramp
fS = 14.3 MSPS
VDD = 5.25 V, VIH = VDD
VDD = 5.25 V, VIL = DGND
VDD = 4.75 V
VDD = 4.75 V
VDD = 5.25 V, OE= VDD
(AVDD -DVDD)
fS=20 MSPS
TEST LEVEL CODES
1.0
1.0
15
15
4.0
1.0
IV
IV
IV
I
I
-1.1
3.5
IV
IV
IV
I
I
+4.75
+4.75
-0.1
TEST LEVEL
All electrical characteristics are subject to the following
conditions:
All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific
device testing actually performed during production
and Quality Assurance inspection. Any blank section in
the data column indicates that the specification is not
tested at the specified condition.
I
I
IV
IV
I
I
0.4
mA
mA
µA
V
V
+5.25
+5.25
0.1
27
135
V
V
V
mA
mW
16
4.0
+5.0
+5.0
0.0
18
90
µA
µA
ns
ns
V
V
TEST PROCEDURE
I
100% production tested at the specified temperature.
II
100% production tested at TA = +25 °C, and sample tested
at the specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design and
characterization data.
V
Parameter is a typical value for information purposes only.
VI
100% production tested at TA = +25 °C. Parameter is
guaranteed over specified temperature range.
SPT1175
3
6/24/97
Table I - Output Coding
INDEX
ANALOG INPUT (V)
DIGITAL
OUTPUT
0
1
2
....
123
124
125
....
254
255
0.6078125
0.6078125 ~ 0.6156260
0.6156250 ~ 0.6234375
....
1.5921875 ~ 1.6000000
1.6000000 ~ 1.6078125
1.6078125 ~ 1.6156250
....
2.5843750 ~2.5921875
2.5921875 ~
00000000
00000001
00000010
....
01111111
10000000
10000001
....
11111110
11111111
Figure 1A: Timing Diagram
VRB=0.6 V
VRT=2.6 V
1 LSB=7.8125 mV
VIN (n)
VIN (n+3)
VIN (n+1)
VIN (n+2)
VIN
Clock
Data (n-3)
Data
Data (n-2)
Data (n-1)
Data (n)
td
Figure 1B: Tri-State Output Timing Diagram
50%
OE
2.5 V
OE
50%
90%
2.5 V
90%
VOL
2.5 V
10%
220 Ω
TdisL
VOL
TeneL
DUT
50 pF
OE
50%
50%
OE
90%
VOH
10%
2.5 V
TdisH
VOH
2.5 V
TeneH
SPT1175
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6/24/97
VRBS pin is to be shorted to the VRB pin. The self-bias internal
reference is not as stable over temperature and supply
variations as externally generated reference voltages but will
perform well in many commercial video applications.
TYPICAL INTERFACE CIRCUIT
The SPT1175 is an 8-bit analog-to-digital converter which
uses a two-step, ping-pong architecture to perform conversions up to 20 MSPS. Figure 2 shows the typical interface
requirements when using the SPT1175 in normal operation.
The following sections describe the function and operation of
the device.
Figure 3 - Reference Circuit Diagram
SPT1175
AVDD
POWER SUPPLIES AND GROUNDING
AGND
0V
5.0V
2.6 V
VRBS
VRB
VRT
VRTS
The SPT1175 operates from a single +5 V power supply.
AVDD and DVDD must be supplied from the same source
(analog +5 V) to prevent a latch-up condition due to power
supply sequencing. Each power supply pin should be bypassed as closely as possible to the device. For optimal
performance, both the AGND and DGND should be connected to the system's analog ground plane.
0.6 V
DIGITAL INPUTS AND OUTPUTS
The analog input is sampled and tracked on the first 'H' cycle
of the external clock and is held from the falling edge of CLK.
The output remains valid (output hold time), and the new data
becomes valid (output delay time) after the rising edge of
CLK, delayed by 2.5 clock cycles. The clock input and output
enable input must be driven at CMOS-compatible levels.
ANALOG INPUT AND VOLTAGE REFERENCE
The SPT1175 input voltage range is VRT>VIN>VRB. Two
reference voltages (VRT and VRB) are required for device
operation. These voltages may be generated externally or
the SPT1175's internal reference may be used.
EVALUATION BOARD
Inside the SPT1175, reference resistors are placed between
AVDD and VRTS and between AGND and VRBS so that VRTS
and VRBS generate the 2.6 V and 0.6 V references respectively. (See figure 3.) In order to utilize the internal self-bias
reference voltage, VRTS is to be shorted with VRT and the
The EB1175 evaluation board is available to aid designers in
demonstrating the full performance of the SPT1175. This
board includes a reference circuit, clock driver circuit, output
data latches, and an on-board reconstruction DAC. An application note describing the operation of the board is available.
Contact the factory for price and delivery.
-15
GND
-5
+5
+15
Figure 2 - Typical Interface Circuit
10
10
10 +
+
10 +
+
13
DVDD
CLK 12
14
AVDD
DVDD 11
15
AVDD
D7 10(MSB)
16
VRTS
D6 9
17
VRT
D5 8
18
AVDD
D4 7
19
VIN
D3 6
20
AGND
D2 5
21
AGND
D1 4
22
VRBS
D0
23
VRB
24
DGND
FB
GND
2k
-15
+5
R1
+15
-5
+5
+5 V
Q1
750
-15 +15
R9
C28
C29
+
VIN
3
75
R35
U1=Eleantec, EL2030
U2=OP.07
D1=D2=RCA, SK9091
Q1=Q2=2N2222A
FR=FairRite, 2743001111
All capacitors are 0.01 µF unless
otherwise specified.
2 _
4
7
U1
+5 V
D1
R37
750
750
R36
_
10 k
R6
C58
R10
7.5 k
D2
6 R15
2 U2
3 +
10
3 (LSB)
C61
C8
C59
Outputs
C60
+15
-15
-15
R8
-5
DGND
2
OE 1
R13
3-ST
Q2
2k
750
200
EN
+5
R2
+5
NOTE: AVDD and DVDD must be supplied from the same source (Analog +5 V)
to prevent a latch-up condition due to power supply sequencing.
SPT1175
5
6/24/97
PACKAGE OUTLINES
24-Lead Plastic DIP
K
24
I
1
SYMBOL
MIN
INCHES
MAX
MILLIMETERS
MIN
MAX
A
0.130
0.230
3.30
5.84
B
0.115
0.200
2.92
5.08
C
D
0.014
0.045
0.023
0.070
0.36
1.14
0.58
1.78
E
.100 typ
2.54
0.00
F
G
0.008
0.115
0.015
0.195
0.20
2.92
0.38
4.95
H
I
.30 typ
0.240
0.310
7.62
6.10
0.00
7.87
J
K
1.180
.005 typ
29.97
0.13
32.64
1.285
J
H
G
A
B
F
D
C
E
24-Lead SOIC
INCHES
SYMBOL
24
A
MIN
0.587
MILLIMETERS
MAX
0.606
MIN
14.90
MAX
15.40
B
I H
1
C
.050 typ
D
0.014
0.022
1.27 typ
0.35
0.55
E
0.006
0.012
0.15
0.30
F
0.067
0.089
1.70
2.25
G
0.012
0.028
0.30
0.70
H
0.295
0.327
7.50
8.30
I
0.205
0.220
5.20
5.60
A
F
B
C
D
G
E
SPT1175
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6/24/97
PACKAGE OUTLINES
28-Lead PLCC
INCHES
SYMBOL
MIN
MILLIMETERS
MAX
MIN
MAX
A
0.450
0.456
11.43
11.58
0.495
12.32
12.57
B
0.485
C
45°
D
0.165
45°
0.175
E
4.19
0.010
4.45
0.25
F
0.022 typ
.56 typ
0.00
G
0.18 typ
4.57 typ
0.00
H
I
0.05 typ
0.039
1.27 typ
0.99
0.00
10.92
0.430
C
Pin 1
H
Pin 1
BOTTOM
VIEW
G
TOP
VIEW
I
F
E
A
B
D
SPT1175
7
6/24/97
PIN FUNCTIONS
PIN ASSIGNMENTS
Name
DGND
OE
VIN
Analog Input
AGND
VRBS
Analog Ground
Internal Self-Biased Reference Bottom
Shorted with VRB (pin 23). Generates 0.6 V.
Reference Resistor Bottom Side
OE
VRB
DGND
DØ (LSB)
VRBS
D1
AGND
D2
AGND
D4
DGND
D0
D1-6
D7
DVDD
CLK
AVDD
VRTS
VIN
DIP and
SOIC
D3
AVDD
D5
VRT
D6
VRTS
D7 (MSB)
AVDD
DVDD
AVDD
CLK
DVDD
27
VRBS 26
VRB
1
2
DGND 28
N/C
OE
4
DGND 3
DØ
VRT
Function
Tri-State Output Enable
Tri-State When OE = DVDD,
Enable When OE = DGND
Digital Ground
Digital Output Data (LSB)
Digital Output Data
Digital Output Data (MSB)
Digital Supply
CMOS Digital Clock Input
Analog Supply
Internal Self-Biased Reference Top
Shorted with VRT (pin 17). Generates 2.6 V.
Reference Resistor Top Side
VRB
D1
5
25
AGND
D2
6
22
AGND
D3
7
23
VIN
N/C
8
22
N/C
D4
9
21
AVDD
D5 10
20
VRT
D6 11
19
VRTS
PLCC
18 AVDD
17 AVDD
16 DVDD
15 N/C
14 CLK
13 DVDD
12 D7
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
SPT1175ACN
0 to +70 °C
SPT1175ACP
0 to +70 °C
SPT1175ACS
0 to +70 °C
SPT1175ACU
+25 °C
*See the die specification for guaranteed electrical performance.
PACKAGE TYPE
24L Plastic Dip
28L PLCC
24L SOIC
Die*
SPT1175
8
6/24/97