FAIRCHILD SPT7722SIT

www.fairchildsemi.com
SPT7722
8-bit, 250 MSPS A/D Converter with Demuxed Outputs
Features
Description
•
•
•
•
•
•
•
•
•
The SPT7722 is a high-speed, 8-bit analog-to-digital converter
implemented in an advanced BiCMOS process. It is a
performance-enhanced version of the SPT7721, offering
better linearity and dynamic performance. An advanced folding
and interpolating architecture provides both a high conversion
rate and very low power dissipation of only 425mW. The
analog inputs can be operated in either single-ended or
differential input mode. A 2.5V common mode reference is
provided on chip for the single-ended input mode to minimize
external components.
TTL/CMOS/PECL input logic compatible
High conversion rate: 250 MSPS
Single +5V power supply
Very low power dissipation: 425mW
350 MHz full power bandwidth
Power-down mode: 24mW
+3.0V/+5.0V (LVCMOS) digital output logic compatibility
Single/demuxed output ports selectable
Improved replacement for AD9054
Applications
•
•
•
•
•
The SPT7722 digital outputs are demuxed (double-wide) with
both dual-channel and single-channel selectable output
modes. Demuxed mode supports either parallel aligned or
interleaved data output. The output logic is both +3.0V and
+5.0V compatible. The SPT7722 is available in a 44-lead
TQFP surface mount package over the industrial temperature
range of -40°C to +85°C.
RGB video processing
Digital communications
High-speed instrumentation
Digital Sampling Oscilloscopes (DSO)
Projection display systems
Block Diagram
DGND
AVCC
OVDD
Data Output Latches
AGND
8-Bit
250 MSPS
ADC
VIN+
VIN–
CLK
CLK
Common Mode
Voltage
Reference
Data Output
Mode Control
DA0–DA7
DB0–DB7
DCLKOUT
DCLKOUT
2
+2.5 V
VCM
PD
CLK CLK
2
Reset DMODE1,2
&
Reset
Rev. 1.0.2 December 2002
DATA SHEET
SPT7722
Absolute Maximum Ratings
(beyond which damage may occur)1 25°C
Parameter
Supply Voltages
AVCC
OVDD
Input Voltages
Analog Inputs
Digital Inputs
Temperature
Operating Temperature
Storage Temperature
Min.
Max.
Unit
+6
+6
V
V
-0.5
-0.5
VCC +0.5
VCC +0.5
V
V
-40
-65
+85
+125
°C
°C
Typ.
Max.
Unit
Note:
1. Operation at any absolute maximum rating is not implied.
See Electrical Specifications table for proper nominal applied conditions in typical applications.
Electrical Specifications
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle,
ƒIN = 70MHz, dual channel mode; unless otherwise noted)
Parameter
Resolution
DC Performance (ƒIN = 1kHz)
Differential Linearity Error (DLE)
Integral Linearity Error (ILE)
No Missing Codes @250 MSPS
Analog Input
Input Voltage Range
Input Common Mode (VCM)
Input Bias Current
Input Resistance
Input Capacitance
Input Bandwidth
Gain Error
Offset Error
Offset Power Supply Rejection Ratio
Timing Characteristics
Conversion Rate
Output Delay (Clock-to-Data) (tpd1)
Output Delay Tempco
Aperture Delay Time (tap)
Aperture Jitter Time
Conditions
Test
Level
Min.
8
+25°C
-40°C to +85°C
+25°C
-40°C to +85°C
VI
IV
VI
IV
VI
with respect to VIN-
V
IV
V
V
V
V
VI
VI
V
+25°C
+25°C
+25°C
+25°C (–3 dB of FS)
+25°C
+25°C
AVCC = 5V ±0.25V
-40°C to +85°C
IV
IV
V
V
V
-0.68
-0.95
2.0
±0.4
±0.7
±1.2
±1.4
Guaranteed
±512
2.5
13
50
5
350
-7.5
-5
bits
0.68
0.95
±1.90
±2.15
3.0
+3.5
+5
<1
25
7.0
250
8
16
0.3
2.0
9.4
LSB
LSB
LSB
LSB
mVpp
V
µA
kΩ
pF
MHz
%FS
LSB
LSB
MSPS
ns
ps/°C
ns
ps-RMS
NOTE: All electrical characteristics are subject to the following condition:
All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific devices testing actually performed
during production and quality assurance inspection. Any blank section in the data column indicates that the specification is not tested at the
specified condition.
2
Rev. 1.0.2 December 2002
SPT7722
DATA SHEET
Electrical Specifications
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle,
ƒIN = 70MHz, dual channel mode; unless otherwise noted)
Parameter
Pipeline Delay (Latency)
Single Channel Mode
Demuxed Interleaved Mode
Demuxed Parallel Mode
Channel B
Channel A
CLK to DCLKOUT Delay Time
Single Channel Mode (tpd2)
Dual Channel Mode (tpd3)
Output Delay (Clock to DClock)
Dynamic Performance
Effective Number of Bits (ENOB)
ƒIN = 70MHz
ƒIN = 70MHz
Signal-to-Noise Ratio (SNR)
ƒIN = 70MHz
ƒIN = 70MHz
Total Harmonic Distortion (THD)
ƒIN = 70MHz
ƒIN = 70MHz
Signal-to-Noise & Distortion (SINAD)
ƒIN = 70MHz
ƒIN = 70MHz
Power Supply Requirements
AVCC Voltage (Analog Supply)
OVDD Voltage (Digital Supply)
AVCC Current
AVCC Current Powerdown
OVDD Current
Single Mode
Parallel Mode
Interleave Mode
Power Dissipation
Common Mode Reference Output
Voltage
Voltage Tempco
Output Impedance
Power Supply Rejection Ratio
Conditions
Test
Level
Min.
Typ.
Max.
Unit
V
V
2.5
2.5
Cycle
Cycle
V
V
2.5
3.5
Cycle
Cycle
IV
IV
V
5.0
5.6
5.18
5.73
18.1
+25°C
-40°C to +85°C
VI
IV
6.4
6.25
7.0
6.8
Bits
Bits
+25°C
-40°C to +85°C
VI
IV
44.3
42.6
46.1
45.4
dB
dB
+25°C
-40°C to +85°C
VI
IV
+25°C
-40°C to +85°C
VI
IV
40.2
39.3
43.7
42.8
IV
IV
VI
VI
4.75
2.75
5.0
+25°C
OVDD = 3.0V, 10pF load
-47
-45.5
85
4.8
V
V
V
VI
IOUT = ±50 µA
VI
V
V
V
35
55
55
425
2.44
2.5
84
1.07
47.5
5.3
5.9
-41.5
-40.3
ns
ns
ps/°C
dB
dB
dB
dB
5.25
5.25
110
5.5
V
V
mA
mA
550
mA
mA
mA
mW
2.56
V
ppm/°C
kΩ
mV/V
NOTE: All electrical characteristics are subject to the following condition:
All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific devices testing actually performed
during production and quality assurance inspection. Any blank section in the data column indicates that the specification is not tested at the
specified condition.
Rev. 1.0.2 December 2002
3
DATA SHEET
SPT7722
Electrical Specifications
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle,
ƒIN = 70MHz, dual channel mode; unless otherwise noted)
Parameter
Conditions
Clock and Reset Inputs
Diff Signal Amplitude (VDIFF)
Diff High Input Voltage (VIHD)
Diff Low Input Voltage (VILD)
Diff Common Mode Input (VCMD)
SE High Input Voltage (VIH)
SE Low Input Voltage (VIL)
Input Current High (IIH)
Input Current Low (IIL)
Power Down & Mode Control Inputs
High Input Voltage
Low Input Voltage
Max Input Current Low
Max Input Current High <4.0V
Digital Outputs
Logic “1” Voltage
Logic “0” Voltage
TR/TF Data
(Diff & Single-Ended)
TR/TF DCLK
VID = 1.5V
VID = 1.5V
(Single-Ended)
IOH = -0.5mA
IOL = +1.6mA
10pF load
OVDD = 3V
OVDD = 5V
10pF load
OVDD = 3V
OVDD = 5V
Test
Level
Min.
IV
IV
IV
IV
IV
IV
VI
VI
400
1.4
0
1.2
1.8
0
–100
–100
IV
IV
VI
VI
2.0
0
–100
–100
VI
VI
OVDD-0.2
Typ.
Max.
Unit
43
43
1.2
+100
+100
mVpp
V
V
V
V
V
µA
µA
0.5
50
AVCC
1.0
+100
+100
V
V
µA
µA
0.2
V
V
AVCC
3.9
4.1
V
V
3.3/3.0
2.3/1.9
ns
ns
V
V
1.2/1.0
0.7/0.6
ns
ns
NOTE: All electrical characteristics are subject to the following condition:
All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific devices testing actually performed
during production and quality assurance inspection. Any blank section in the data column indicates that the specification is not tested at the
specified condition.
TEST LEVEL CODES:
Level
I
II
II
IV
V
VI
4
Test Procedure
100% production tested at the specified temperature.
100% production tested at TA = +25°C and sample tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characterization data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25°C. Parameter is guaranteed over specific temperature range.
Rev. 1.0.2 December 2002
SPT7722
DATA SHEET
Typical Operating Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle,
ƒIN = 70MHz, dual channel mode; unless otherwise noted)
DLE vs. Temperature
ƒIN = 70.1 MHz
LSB
LSB
DLE vs. Sample Rate
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
200
225
250
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
ƒIN = 70.1MHz
ƒS = 250 MSPS
-50
260
-25
50
75
100
AVCC Current vs. Temperature
ƒIN = 70.1MHz
ƒS = 250 MSPS
90
80
ƒIN = 70.1MHz
ƒS = 250 MSPS
70
60
50
40
30
20
10
Powerdown mode
0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
-50
-25
Volts
0
25
50
75
100
Temperature (°C)
SFDR, THD vs. Sample Rate
SNR, SINAD vs. Sample Rate
-30
60
ƒIN = 70.1 MHz
50
ƒIN = 70.1 MHz
-35
SFDR, THD (dB)
55
SNR, SINAD (dB)
25
100
AVCC Current (mA)
LSB
DLE vs. AVCC
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
SNR
45
SINAD
40
35
30
-40
-45
THD
-50
SFDR
-55
-60
-65
25
-70
20
200
225
250
200
260
225
250
260
Sample Rate (MSPS)
Sample Rate (MSPS)
SNR, SINAD vs. Temperature
THD vs. Temperature
60
-30
ƒIN = 70.1 MHz
ƒS = 250 MSPS
55
ƒIN = 70.1 MHz
ƒS = 250 MSPS
-35
50
-40
SNR
THD (dB)
SNR, SINAD (dB)
0
Temperature (°C)
Sample Rate (MSPS)
45
SINAD
40
35
-45
-50
-55
30
-60
25
-65
20
-70
-50
-25
0
25
50
Temperature (°C)
Rev. 1.0.2 December 2002
75
100
-50
-25
0
25
50
75
100
Temperature (°C)
5
DATA SHEET
SPT7722
Typical Operating Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle,
ƒIN = 70MHz, dual channel mode; unless otherwise noted)
SNR, SINAD vs. Duty Cycle
SFDR, THD vs. Duty Cycle
60
-30
ƒIN = 70.1 MHz
ƒS = 250 MSPS
50
SNR
45
SINAD
40
35
30
25
-40
-45
THD
-50
SFDR
-55
-60
-65
-70
20
35
40
45
50
55
60
35
% Duty Cycle
45
50
55
60
THD vs. AVCC
SNR, SINAD vs. AVCC
-30
ƒIN = 70.1 MHz
ƒS = 250 MSPS
55
50
-40
SNR
45
SINAD
40
35
-45
-50
-55
30
-60
25
-65
20
ƒIN = 70.1 MHz
ƒS = 250 MSPS
-35
THD (dB)
SNR, SINAD (dB)
40
% Duty Cycle
60
-70
4.5 4.6 4.7 4.8 4.9
5.0 5.1 5.2 5.3 5.4 5.5
Volts
6
ƒIN = 70.1 MHz
ƒS = 250 MSPS
-35
SFDR, THD (dB)
SNR, SINAD (dB)
55
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Volts
Rev. 1.0.2 December 2002
SPT7722
DATA SHEET
Theory of Operation
The SPT7722 is a three-step subranger. It consists of two
THAs in series at the input, followed by three ADC blocks.
The first block is a three-bit folder with over/under range
detection. The second block consists of two single-bit folding
interpolator stages. There are pipelining THAs between each
ADC block.
The analog decode functions are the input buffer, input
THAs, three-bit folder, folding interpolators, and pipelining
THAs. The input buffer enables the part to withstand rail-torail input signals without latchup or excessive currents and also
performs single-ended to differential conversion. All of the
THAs have the same basic architecture. Each has a differential
pair buffer followed by switched emitter followers driving the
hold capacitors. The input THA also has hold mode feedthrough cancellation devices.
The three MSBs of the ADC are generated in the first threebit folder block, the output of which drives a differential
reference ladder which also sets the full-scale input range.
Differential pairs at the ladder taps generate midscale,
quarter and three-quarter scale, overrange, and underrange.
Every other differential pair collector is cross-coupled to
generate the eighth scale zero crossings. The middle ADC
block generates two bits from the folded signals of the
previous stages after pipeline THAs. Its outputs drive more
pipeline THAs to push the decoding of the three LSBs to the
next half clock cycle. The three LSBs are generated in interpolators that are latched one full clock cycle after the MSBs.
The digital decode consists of comparators, exclusive of cells
for gray to binary decoding, and/or cells used for mostly
over/under range logic. There is a total of 2.5 clock cycles
latency before the output bank selection. In order to reduce
sparkle codes and maintain sample rate, no more than three
bits at a time are decoded in any half clock cycle.
The output data mode is controlled by the state of the demux
mode inputs. There are three output modes:
• All data on bank A with clock rate limited to
one-half maximum
• Interleaved mode with data alternately on banks
A and B on alternate clock cycles
• Parallel mode with bank A delayed one cycle to
be synchronous with bank B every other clock cycle
If necessary, the input clock is divided by two. The divided
clock selects the correct output bank. The user can synchronize with the divided clock to select the desired output bank
via the differential RESET input.
The output logic family is CMOS with output OVDD supply
adjustable from 2.7V to 5.25V. There are also differential
clock output pins that can be used to latch the output data in
single bank mode or to indicate the current output bank in
demux mode.
Finally, a power-down mode is available, which causes the
outputs to become tri-state, and overall power is reduced to
about 24mW. There is a 2V reference to supply common
mode for single-ended inputs that is not shut down in powerdown mode.
2.5 CLK Cycles
of Latency
N
VIN
N+2
N+1
tap
N+3
N+4
N+5
CLK
CLK
tpd1
D0–D7
(Bank A)
DCLKOUT
N–3
tpd2
N–2
N–1
N
N+1
N+2
tpd2
DCLKOUT
Figure 1. Single Mode Timing Diagram
Rev. 1.0.2 December 2002
7
DATA SHEET
SPT7722
2.5 CLK Cycles
of Latency
N-2
VIN
N+1
N-1
tap
N+3
N+2
N+4
Refer to AN7722
CLK
CLK
U6Reset
550ps
550ps
tpd1
tpd1
Reset
Reset
INTERLEAVED DATA OUTPUT
N-5
Bank A
Bank B
Invalid Data
N-4
N-6
6ns typ
tpd3
N+1
N-1
N-2
N
PARALLEL DATA OUTPUT
Bank A
N-7
N-5
Bank B
N-6
N-4
Invalid Data
N-1
N-2
N
tpd3
DCLKOUT
DCLKOUT
2.5 CLK Cycles
of Latency
N-2
VIN
N-1
tap
N+1
N
N+3
N+2
N+4
Refer to AN7722
CLK
CLK
U6Reset
550ps
550ps
tpd1
Reset
tpd1
Reset
INTERLEAVED DATA OUTPUT
Bank A
N-6
Bank B
N-5
tpd3
N+1
N-1
Invalid Data
N-4
N-2
N
PARALLEL DATA OUTPUT
Bank A
N-6
Bank B
N-5
N-1
Invalid Data
N-2
N
tpd3
DCLKOUT
DCLKOUT
Data Output Possibilities w/o Reset
Figure 2. Dual Mode Timing Diagram
8
Rev. 1.0.2 December 2002
SPT7722
DATA SHEET
Mode
Select
Reset
Diff In
Clock
Diff
Power
Down
+D3/5
PD
CLK
CLK
RESET
RESET
DMODE1
VCM
T1
DMODE2
30kΩ
DA0–DA7
VIN+
SPT7722
50Ω
VIN–
DCLKOUT
Interfacing
Logics
DB0–DB7
AGND
DGND
.01µF
AVCC
Mini-Circuit
T1-6T
DCLKOUT
OVDD
AIN
.01µF
.01µF
Notes:
1) FB = Ferrite bead. It must placed as close to the ADC as possible.
2) All 0.01 microfarad capacitors are surface mount caps. They must be
placed as close to the respective pin as possible.
3) For details, refer to the Application Note AN7722.
+
10µF
FB
+A5
+
10µF
+D3/5
+D3/5
Figure 3. Typical Interface Circuit
Typical Interface Circuit
AVCC
17.5kΩ
CLK
&
RES
300Ω
CLK
&
RES
300Ω
100kΩ
Very few external components are required to achieve the
stated device performance. Figure 3 shows the typical interface requirements when using the SPT7722 in normal circuit
operation. The following sections provide descriptions of the
major functions and outline performance criteria to consider
for achieving the optimal device performance.
7.5kΩ
Analog Input
The input of the SPT7722 can be configured in various ways
depending on whether a single-ended or differential input is
desired.
AGND
Figure 4. CLK and Reset Equivalent Circuit
(without ESD Diodes)
AVCC
100kΩ
100kΩ
VIN+
VIN–
300Ω
200Ω
200Ω
100kΩ
300Ω
The AC-coupled input is most conveniently implemented
using a transformer with a center-tapped secondary winding.
The center tap is connected to the VCM pin as shown in
Figure 3. To obtain low distortion, it is important that the
selected transformer does not exhibit core saturation at the
full-scale voltage. Proper termination of the input is important
for input signal purity. A small capacitor across the input
attenuates kickback noise from the internal track-and-hold.
100kΩ
AGND
Figure 6 illustrates a solution (based on operational amplifiers)
that can be used if a DC-coupled single-ended input is
desired.
Figure 5. Analog Input Equivalent Circuit
Rev. 1.0.2 December 2002
9
DATA SHEET
SPT7722
Clock Input
R3
R3
R
–
VCM
ADC
+
Input
Voltage
(±0.5 V)
(R3)/2
R
–
R2
51Ω
+
15pF
R2
51Ω
R
R
VIN+
VIN–
+
51Ω
The clock input on the SPT7722 can be driven by either a
single-ended or double-ended clock circuit and can handle
TTL, PECL, and CMOS signals. When operating at high
sample rates it is important to keep the pulse width of the
clock signal as close to 50% as possible. For TTL/CMOS single-ended clock inputs, the rise time of the signal also
becomes an important consideration.
–
R
Figure 6. DC-Coupled Single-Ended to Differential
Conversion (power supplies and
bypassing are not shown)
Input Protection
All I/O pads are protected with an on-chip protection circuit.
This circuit provides ESD robustness and prevents latchup
under severe discharge conditions without degrading analog
transmission times.
Power Supplies and Grounding
The SPT7722 is operated from a single power supply in the
range of 4.75V to 5.25V. Normal operation is suggested to be
5.0V. All power supply pins should be bypassed as close to
the package as possible. The analog and digital grounds
should be connected together with a ferrite bead as shown in
the typical interface circuit and as close to the ADC as possible.
Power-Down Mode
To save on power, the SPT7722 incorporates a power-down
function. This function is controlled by the signal on pin PD.
When pin PD is set high, the SPT7722 enters the power-down
mode. All outputs are set to high impedance. In the powerdown mode the SPT7722 dissipates 24mW typically.
Digital Outputs
The output circuitry of the SPT7722 has been designed to be
able to support three separate output modes. The demuxed
(double-wide) mode supports either parallel aligned or interleaved data output. The single-channel mode is not demuxed
and can support direct output at speeds up to 125 MSPS. The
output format is straight binary (table 1).
Table 1. Output Data Format
Analog Input
+FS
+FS - 1 LSB
+1 FS
-FS + 1 LSB
-FS
Output Code D7–D0
1111 1111
1111 111Ø
1000 000Ø
0000 000Ø
0000 0000
Ø indicates the flickering bit between logic 0 and 1
The data output mode is set using the DMODE1 and
DMODE2 inputs (pins 32 & 31 respectively). Table 2
describes the mode switching options.
Table 2. Output Data Modes
Output Mode
DMODE1 DMODE2
Parallel Dual Channel Output
0
0
Interleaved Dual Channel Output
0
1
Single Channel Data Output
1
X
(Bank A only 125 MSPS max)
Common-Mode Voltage Reference Circuit
The SPT7722 has an on-board common-mode voltage reference
circuit (VCM). It is 2.5V and is capable of driving 50µA loads
typically. The circuit is commonly used to drive the center
tap of the RF transformer in fully differential applications.
For single-ended applications, this output can be used to
provide the level shifting required for the single-to-differential
converter conversion circuit. Bypass VCM to AGND by
external 0.01µF capacitor, as shown in Figure 3.
10
Evaluation Board
The EB7721/22 evaluation board is available to aid designers
in demonstrating the full performance of the SPT7722. This
board includes a clock driver and reset circuit, adjustable
references and common mode, a single-ended to differential
input buffer and a single-ended to differential transformer
(1:1). An application note (AN7722) describing the operation
of this board, as well as information on the testing of the
SPT7722, is also available. Contact the factory for price and
availability of the EB7722.
Rev. 1.0.2 December 2002
SPT7722
DATA SHEET
Pin Assignments
AGND
AVCC
AVCC
AGND
VIN+
VIN–
AGND
VCM
AVCC
AVCC
AGND
44
43
42
41
40
39
38
37
36
35
34
AGND
1
33
AGND
PD
2
32
DMODE1
CLK
3
31
DMODE2
CLK
4
30
OVDD
RESET
5
RESET
6
SPT7722
TOP VIEW
44L TQFP
29
DGND
28
DCLKOUT
27
DCLKOUT
OVDD
7
DGND
8
26
DB7 (MSB)
DA7 (MSB)
9
25
DB6
DA6
10
24
DB5
DA5
11
23
DB4
20
21
22
DB0 (LSB)
DB1
DB2
DB3
DGND
19
DA1
18
DA2
DA0 (LSB)
15
DA3
OVDD
14
DA4
17
13
16
12
Pin Definitions
Pin Name
VIN+
Pin Number
40
VIN-
39
DA0–DA7
DB0–DB7
DCLKOUT
DCLKOUT
CLK
CLK
RESET
16–9
19–26
28
27
4
3
5
Data Output Bank A; 3V/5V LVCMOS compatible
Data Output Bank B; 3 V/5V LVCMOS compatible
Non-Inverted Data Output Clock; 3V/5V LVCMOS compatible
Inverted Data Output Clock; 3V/5V LVCMOS compatible
Non-Inverted Clock Input Pin; 100k pulldown to AGND, internally
Inverted Clock Input Pin; 17.5k pullup to VCC and 7.5k pulldown to AGND, internally
RESET synchronizes the data sampling and data output bank relationship when in
Dual Channel Mode (DMODE1 = 0); 100k pulldown to AGND, internally
RESET
DMODE1,2
6
32, 31
PD
2
Inverted RESET Input Pin; 17.5k pullup to VCC and 7.5 pulldown to AGND, internally
Internally:
100k pulldown to AGND on DMODE1
50k pullup to VCC on DMODE2
Data Output Mode Pins:
DMODE1 = 0, DMODE2 = 0: Parallel Dual Channel Output
DMODE1 = 0, DMODE2 = 1: Interleaved Dual Channel Output
DMODE1 = 1, DMODE2 = X: Single Channel Data Output on Bank A
(125 MSPS max)
Power Down Pin; PD = 1 for power-down mode. Outputs set to high impedance in
power-down mode; 100k pulldown to AGND, internally
VCM
AVCC
OVDD
AGND
37
35, 36, 42, 43
7, 17, 30
1, 33, 34,
38, 41, 44
8, 18, 29
DGND
Rev. 1.0.2 December 2002
Pin Function Description
Non-Inverted Analog Input; nominally 1 VPP;
100k pullup to VCC and 100k pulldown to AGND, internally
Inverted Analog Input; nominally 1 VPP; 100k pullup to VCC and 100k
pulldown to AGND, internally
2.5V Common Mode Voltage Reference Output
+5V Analog Supply
+3V/+5V Digital Output Supply
Analog Ground
Digital Ground
11
DATA SHEET
SPT7722
Ordering Information
Model
Part Number
Package
SPT7722
SPT7722SIT
TQFP-44
Temperature range for all parts: -40°C to +85°C.
Package Dimensions
TQFP-44
A
B
PIN1
Index
C D
E
SYMBOL
A
B
C
D
E
F
G
H
I
J
K
INCHES
MIN TYP MAX
0.472
0.394
0.394
0.472
0.031
0.012
0.018
0.053
0.057
0.002
0.006
0.018
0.030
0.039
0-7°
MILLIMETERS
MIN TYP MAX
12.00
10.00
10.00
12.00
0.80
0.300
0.45
1.35
1.45
0.05
0.15
0.45
0.75
1.00
0-7°
F
G
K
I
H
J
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN.
FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY
LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE
PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1.
Life support devices or systems are devices or systems which, (a) are intended for
surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com
2.
A critical component in any component of a life support device or system whose failure
to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
© 2002 Fairchild Semiconductor Corporation