SPT8100 16-BIT, 5 MSPS CMOS A/D CONVERTER TECHNICAL DATA JANUARY 9, 2002 FEATURES APPLICATIONS • 16-bit, 5 MSPS CMOS analog-to-digital converter • On-chip PGA: gain range from 0 to 19.5 dB in seven selectable settings: 0 dB, +2.9 dB, +5.8 dB, +11.8 dB, +14.8 dB, +17.5 dB, +19.5 dB • DLE: ±0.5 LSB, ILE: ±1.25 LSB • SFDR: 94 dB @ ƒIN = 900 kHz, –8.1 dBFS • Internal sample-and-hold and voltage reference • Power dissipation: 465 mW at 5 MSPS • +5 V analog supply and +3.3 to +5.25 V digital output supply • 44-lead LQFP plastic package • • • • • • • • Data acquisition systems IR imaging Scanners and digital copiers High-end CCD cameras Medical imaging Wireless communications Lab and test equipment Automatic test equipment DESCRIPTION The SPT8100 is a high-performance, 16-bit analog-todigital converter that operates at a sample rate of up to 5 MSPS. Excellent dynamic performance and high linearity is achieved by a digitally calibrated pipelined architecture fabricated in CMOS process technology. A low-noise programmable gain amplifier (PGA) is also incorporated on chip. The PGA is digitally programmable in seven selected settings over a 0 to +19.5 dB range. The BLOCK DIAGRAM AVDD +5V SPT8100 also features an on-chip internal sample-andhold and internal reference for minimal external circuitry. It operates from a single +5 V supply. Total power dissipation, including internal reference, is 465 mW. A separate digital output supply pin is provided for +3.3 V or 5 V logic output levels. The SPT8100 is available in a 44-lead LQFP package over the industrial temperature range of –40 °C to +85 °C. DVDD +5V OVDD +3/5 V OE (Output Enable) Low-Noise PGA OVR (Over-Range) VIN+ 16-bit, 5 MSPS ADC VIN– 16-bits D15 – D0 (Data Outputs) VCM GS2 – GS0 (Gain Set) RS (Reset) VREF AGND DGND OGND BIASC (Ext Bias Capacitor) BIASR (Ext Bias Resistor) RDY (Ready) VRT VRB CLK ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages AVDD ...................................................................... +6 V DVDD ..................................................................... +6 V OVDD ..................................................................... +6 V Input Voltages Analog Input ................................. –0.5 V to VDD +0.5 V CLK Input ............................................................... VDD AVDD – DVDD .................................................. ±100 mV Delta between AGND, DGND, and OGND ...... ±100 mV Output Digital Outputs .................................................... 10 mA Temperature Operating Temperature ........................... –40 to +85 °C Junction Temperature ...................................... +175 °C Lead Temperature (soldering 10 seconds) ...... +300 °C Storage Temperature ............................ –65 to +150 °C Note 1: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, AVDD=DVDD=+5.0 V, OVDD= 3.3 V, ƒS=5 MSPS, 2.5 VPP input span, Gain=0 dB, REXT=1.43 kΩ, unless otherwise specified. PARAMETERS TEST CONDITIONS TEST LEVEL Resolution DC Accuracy Integral Linearity Error (ILE) Differential Linearity Error (DLE) Gain Error1 Offset Error2 V V IV IV Analog Input (into PGA) Differential Input Voltage Range VIN+, VIN– Input Capacitance PGA Gain = 0 dB Input Resistance3 Input Bandwidth4 PGA Gain = 0 dB Input Common Mode Voltage Range V IV IV V V Programmable Gain Amp Composite Input-Referred Noise Floor ƒIN > 300 kHz PGA Gain = 0 dB PGA Gain = 2.9 dB PGA Gain = 5.8 dB PGA Gain = 11.8 dB PGA Gain = 14.8 dB PGA Gain = 17.5 dB PGA Gain = 19.5 dB PGA Range PGA Gain Steps3 PGA Gain Accuracy Conversion Characteristics Maximum Conversion Rate Pipeline Delay (Latency)5 Reset Pulse Time (RS) Reset Calibration Time FS = 5 MSPS References and External Bias VRT – VRB (Internal Ref) Bias Resistor Range (External) VCM Output Voltage VCM Output Current VRT VRB Total gain error of PGA and ADC using internal references. Total offset error of PGA and ADC relative to mid-scale. 3 See table I for input resistance as a function of PGA gain. 1 4 2 5 MIN SPT8100 TYP 15.9 16 MAX Bits ±1.25 ±0.5 –7.5 –5 +7.5 +5 5 15 1.15 5.5 12 2.40 UNITS 3.65 LSB LSB %FSR %FSR VPPD pF kΩ MHz V V V V V V V V V VI VI 1.4 1.5 1.6 2.0 2.3 2.6 2.8 19.5 0,2.9,5.8,11.8,14.8,17.5,19.5 ±0.3 LSBRMS LSBRMS LSBRMS LSBRMS LSBRMS LSBRMS LSBRMS dB dB dB VI IV IV V 5 MSPS Clocks Clocks ms VI V IV IV V V 2.375 800 2.275 2.5 1430 2.40 3.45 0.95 3.65 1.15 5.5 3 150 2.625 2500 2.525 47 3.85 1.35 V Ω V µA V V Input bandwidth is a frequency to which the fundamental energy drops by 3 dB The input is sampled on the falling edge of the clock and is available on the output after the rising edge of the clock, 5.5 clock cycles later. SPT8100 2 1/9/02 ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, AVDD=DVDD=+5.0 V, OVDD= 3.3 V, ƒS=5 MSPS, 2.5 VPP input span, Gain=0 dB, REXT=1.43 kΩ, unless otherwise specified. PARAMETERS Dynamic Performance1 Effective Number of Bits ƒIN = 60 kHz ƒIN = 900 kHz Signal-to-Noise Ratio (without Harmonics) ƒIN = 75 kHz ƒIN = 900 kHz Harmonic Distortion ƒIN = 60 kHz ƒIN = 900 kHz Signal-to-Noise and Distortion (SINAD) ƒIN = 60 kHz ƒIN = 900 kHz Spurious Free Dynamic Range3 ƒIN = 60 kHz ƒIN = 900 kHz ƒIN = 2 MHz ƒIN = 3 MHz Two-Tone Intermodulation 3rd Order Distortion TEST CONDITIONS TEST LEVEL 2 3 MAX UNITS IV V 12.2 13.0 12.7 Bits Bits IV V 78 81 80 dB dB ADC Input = –1 dBFS2 ADC Input = –0.5 dBFS IV V –92 –82 –84 dB dB ADC Input = –1 dBFS IV V 75 80 78 dB dB 85 REXT = 1 kΩ @ 10 MSPS REXT = 1 kΩ @ 10 MSPS IV V V V 94 94 83 78 dBc dBc dBc dBc ƒ1=400 kHz, ƒ2=410 kHz4 ƒ1=890 kHz, ƒ2=900 kHz5 V V –94 –89 dB dB ADC Input = –0.5 dB VI VI VI VI VI VI V IOH = –2 mA IOL = 2 mA CLOAD = 20 pF Power Supply Requirements Voltages OVDD AVDD DVDD Currents IDD Power Dissipation 1 SPT8100 TYP ADC Input = –1 dBFS2 Inputs GS0–GS2 Logic 1 Voltage GS0–GS2 Logic 0 Voltage CLK, RS Logic 1 Voltage CLK, RS Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Input Capacitance Digital Outputs Logic 1 Voltage Logic 0 Voltage CLK to Output Delay Time (tD) MIN Dynamic performance tested at ƒS=4.4 MSPS 0 dBFS is 5.0 V peak-to-peak differential ADC Input = –8.1 dBFS, unless otherwise noted TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. 4 5 TEST LEVEL I II III IV V VI 2.4 0.8 2.0 0.8 +10 +10 –10 –10 5 VI VI IV OVDD – 0.5 IV IV IV VI VI 3.0 4.75 4.75 3.3 5.0 5.0 93 465 V V V V µA µA pF 0.4 30 V V ns 5.25 5.25 5.25 103 515 V V V mA mW Test Conditions: PGA setting of 5.8 dB; Analog Input at ADC = –0.7 dB Test Conditions: PGA setting of 0 dB; Analog Input at ADC = –1.9 dB TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. SPT8100 3 1/9/02 DEVICE OVERVIEW ADC CLOCK The SPT8100 combines a high-resolution 5 MSPS 16-bit ADC, a built-in reference, and a programmable gain amplifier (PGA) with resistive input impedance in a 44-pin package. The chip requires a single low-jitter clock to be applied at the CLK pin, with nominal 40–60% duty cycle. All clock generation is performed internally and all converter and S/H clocks in the ADC path are directly derived from CLK. The device includes a digitally calibrated pipeline ADC, which is calibrated on assertion of a simple reset signal. The combination of low noise, high linearity, a high-input impedance buffer (with programmable gain), wideband S/H, on-board voltage references, and simple digital interface (16-bit parallel output word synchronous with the master sampling clock) makes the SPT8100 extremely easy to use in a wide variety of systems. If the sample rate is changed by more than a factor of 2, the device must be recalibrated using the RS (reset) pin. DEVICE STARTUP/INITIALIZATION SEQUENCE Note: This initialization sequence is required. Without it, the device will not work. Allow sufficient time for the analog blocks on the SPT8100 to power on and come up to their quiescent DC states. Allowance may also be needed for thermal time constants associated with the package/board. For optimum performance, the analog inputs should be driven differentially, and may be AC-coupled or DCcoupled to a source. Typical applications include high-performance data acquisition systems, automatic test equipment, and wideband digital communications receivers such as wireless basestations. On powerup, the SPT8100’s RS (reset) should be held low for at least three clock cycles. The power supply voltages applied to the device must be stable during this time. The clock signal (CLK) must be running for at least three clock cycles prior to the rising edge of RS, and must continue running. OPERATIONAL DESCRIPTION The following sections describe in greater detail individual blocks and functions of the SPT8100. When the RS signal goes from low to high, calibration is initiated. RDY is driven low two clock cycles after the rising edge of RS, and will stay low for 150 ms with a 5 MHz clock. When the initialization is complete, RDY returns high and the device is ready for normal operation. Note that the calibration of the ADC can be interrupted (before completion) by changing the RS signal from high to low, which will cause another reset to occur. When RS goes from low back to high, another calibration cycle will begin. The incoming analog differential signal (maximum level 5 V peak-to-peak differential) enters the device at the pins VIN+/VIN–. The analog signal path is partitioned into a programmable gain amplifier (PGA) and an ADC. The PGA has maximum gain of +19.5 dB; the gain is set by the digital control signals GS0 to GS2. The output of the PGA is fed directly to the ADC, which samples at a rate equal to the CLK frequency and outputs a 16-bit wide parallel word. The ADC uses a pipeline multistage architecture. Latency is 5.5 clock cycles. RDY cannot be tri-stated: it is always driven either high or low. The CLK must be constantly running throughout the Figure 1 – Device Initialization Timing PWR ON N+7 N+4 AIN N+8 N+6 N+5 CLK RS 3 clock cycles min 5 ns typ 2 clock cycles RDY Initialization period: 150 ms with 5 MHz clock 24 ns typ DOUT INVALID DATA N N+1 N+2 Requires external reset on powerup SPT8100 4 1/9/02 TYPICAL INTERFACE CIRCUIT initialization phase until RDY is deasserted. Note that, although typically the device is initialized when power is first applied, the initialization is only started when the RS is asserted; there is no “power-on-reset” circuitry on chip. RS may be held low for an indefinite period of time. While RS is low, RDY will remain high. After RS is returned to high, RDY will go low for the duration of the calibration. ANALOG INPUT DRIVER The differential analog inputs (VIN+, VIN–) have a resistive input impedance of 1 kΩ minimum. For best performance, the input source should be a differential input, as shown in figure 2, typical interface circuit. The SPT8100 provides its own common-mode voltage on the pin marked VCM. Output drive capability of VCM is a maximum of 47 µA (50 kΩ to ground). PROGRAMMABLE GAIN AMPLIFIER The programmable gain amplifier (PGA) precedes the ADC inputs. The differential inputs, which are resistive, are at pins VIN+ and VIN–.The maximum input range is 5 V peak-to-peak differential (2.5 V single-ended). To achieve maximum overall system noise performance, the source driving these inputs needs to be as low-noise and as lowjitter as possible, while maintaining the required distortion performance. In addition, the driving source must be low impedance to maintain the accuracy of the PGA gain. The SPT8100 application note (AN8100) shows an example of two modes of driving the SPT8100. One mode is through a transformer and the other is through a single-todifferential converter. In all cases, both inputs VIN+ and VIN– must be kept within the input common-mode range (1.15 V to 3.65 V). BIASC CONNECTION The internal 0 dB analog signal level and ADC full-scale output level is 5 V peak-to-peak differential (2.5 V singleended). The PGA may be used to provide gain for an input less than 5 V peak-to-peak differential. An external capacitor, CEXT on the BIASC pin, is used only for noise filtering of an internal voltage associated with the references. Its value is not critical: 1 µF in parallel with 0.01 µF is recommended. The gain of the PGA can be programmed using a three-bit control, available at pins GS0 to GS2. See table I. Note that the input resistance is a function of the gain setting. BIASR CONNECTION As shown in the typical interface circuit, REXT is needed to connect between BIASR to ground. This resistor ranges from 800 Ω to 2.5 kΩ. The proper selection of REXT is a function of the sample rate and input frequency. Nominally, at 5 MSPS, REXT=1.43 kΩ is recommended. If linearity for large signal levels at an analog bandwidth of 2 MHz is critical, the value should be decreased to REXT=1.24 kΩ; and for even higher-frequency analog inputs, REXT=1.0 kΩ can be used. At lower sample rates (for example 2 MSPS), and lower analog input frequencies, the value may be increased to REXT=2 kΩ. (Refer to the typical interface circuit table in figure 2b.) Table I – PGA Gain Control GS2 GS1 GS0 PGA Input V/V Gain Resistance Gain Ω) (dB) (kΩ 3 dB BW LSBRMS 0 0 0 0 5.57 1 12 1.4 0 0 1 2.9 4.65 1.40 10 1.5 0 1 0 5.8 3.97 1.95 8 1.6 0 1 1 11.8 2.23 3.9 7 2.0 1 0 0 14.8 1.66 5.5 6 2.3 1 0 1 17.5 1.25 7.5 5.5 2.6 1 1 0 19.5 1.00 9.5 5 2.8 1 1 1 X POWER SUPPLIES AND GROUNDING The SPT8100 requires three power supplies: analog AVDD, digital DVDD and output supply OVDD. This device works best if all three supplies are coming from the analog supply side of the system as shown in the typical interface circuit (figure 2a). Forbidden Note, in figure 2a, that the supplies to the logic interface circuit and the OVDD are separate from each other. In a case where the +A3.3/5 V supply is not available, try to implement the design as close as possible to that shown in figure 2b. Place the ferrite bead (FB1) as close to the device as possible. To avoid latch-up, the delta between all three grounds must stay with 100 mV; this includes transients. (Refer to the absolute maximum ratings specifications.) SPT8100 5 1/9/02 Figure 2a – Typical Interface Circuit 1.0 + Gain Control Reset Output Enable Clock (active Hi) Input .01 1.43K BIASC RS GS2 GS1 GS0 BIASR REXT CLK OE VCM Transformer AIN RDY VIN+ 16 RT (50) SPT8100 D0–15 VIN– Mini-Circuit T1-6T 0.1 + 4.7 VRT + OVR VRB 10 0.1 Logic Interfacing Circuit AVDD DVDD AGND DGND OGND 1nF OVDD 0.1 0.1 10 + + 10 FB1 +A5V +A3.3/5V +D3.3/5V Figure 2b – Typical Interface Circuit 1.0 + Gain Control Reset Output Enable Clock (active Hi) Input .01 1.43K BIASC RS GS2 GS1 GS0 BIASR REXT OE CLK VCM Transformer AIN RDY VIN+ 16 RT (50) SPT8100 D0–15 VIN– Mini-Circuit T1-6T 0.1 + 4.7 VRT + OVR VRB 10 0.1 1nF Logic Interfacing Circuit AVDD DVDD AGND DGND OGND OVDD 0.1 0.1 Ω) ƒS (MSPS) REXT (kΩ –5 –2 –5 –2 1.43 2.00 1.24 1.00 ƒIN <2 MHz <2 MHz •2 MHz •2 MHz 10 + FB2 10 + +A5V FB1 FB3 +D3.3/5V 800 Ω – REXT – 2.5 kΩ Notes: 1. To avoid device latch-up, closely follow either figure 2a or 2b, depending on what is available in the system. The difference between figure 2a and 2b is in the grounding. 2. FB = ferrite bead. FB1 must be placed as close to the device as possible. 3. REXT = 1.43 kΩ, optimized for ƒS = 5 MSPS. Refer to the above table for recommended value of REXT with respect to ƒS and ƒIN. 4. RT is AIN source termination resistor. 5. Power supplies and references pins must have adequate decoupling. Surface-mount capacitors are highly recommended. The smallest value of capacitors are to be placed as close to the pin as possible. SPT8100 6 1/9/02 Figure 3 – Timing Diagram 1 n+1 n n+2 n+3 n+4 n+5 Analog In n+6 n+8 n+7 CLK tD D0D15 OVR n n+1 n+2 INPUT/OUTPUT TIMING OUTPUT ENABLE The SPT8100 implements a simple interface: the 16 ADC outputs appear on the pins D15–D0 as a parallel word synchronous with the ADC sampling clock. D0 is the LSB and D15 is the MSB. The timing diagram for the ADC digital outputs is shown in figure 3. The data is sampled at the falling edge of the clock. The ADC sampling clock is at the same frequency as CLK. The ADC digital outputs are enabled by the active high output enable pin (OE). OE = 1: ADC digital outputs are enabled OE = 0: ADC digital outputs are high-impedance (tri-stated) DIGITAL CODE RANGE AND OUT-OF-RANGE DETECTION The output data is updated on the rising edge of CLK with a clock latency of 5.5 clock cycles. The output format of the ADC digital data is offset binary. Due to the calibration algorithm used, there is a slight loss in digital code range from the ADC. Instead of FFFFH and 0000H at the extremes of the range, the actual maximum and minimum codes are less than that by 1.6% at both ends of the scale, and vary from chip to chip. Effectively, this is a loss in dynamic range of a few tenths of a dB, and is negligible in many applications. The out-of-range function is defined accordingly, and sets the state of the active high digital output OVR, as follows: OUTPUT LOGIC LEVEL The voltage levels on the D15–D0 lines and OVR are CMOS levels: the HIGH level is determined by the power supply voltage on the OVDD pin, which can be set independently of the other supply pins on the device over the range from 3.0 V to 5.25 V (3.3 V typical). The RDY pin level is determined by DVDD (+5 V).The external digital output buffers should be placed as close as possible to the SPT8100 digital outputs to minimize any line reflections that would cause performance degradation. OVR is HIGH if the ADC digital code is greater than or equal to FC00H or less than or equal to 03FFH. (See figure 4.) ADC REFERENCES If the output code exceeds FC00(max) or 03FF(min), this implies that output is clipping. Therefore, once these limits are crossed, the second harmonic becomes significant and degrades performance. The ADC full-scale range is set by reference voltages generated on chip. These two reference voltages appear on pins VRT and VRB; nominally their difference is 2.5 V. The references are not designed to be overdriven. The VRT and VRB pins should be very carefully decoupled on the board using as short a trace as possible. Some optimization of the decoupling may be required, as shown in the typical interface circuit diagram. The smallest capacitor should be the closest one to the chip. (Refer to the typical interface circuit diagram.) Figure 4 – ADC Digital Code Range and Overrange Bit Function FFFFH 65535 OVR = 1 ADC Digital Code Range OVR = Ø 03FFH 1023 OVR = 1 0000H 1.6% FSR 64512 FC00H 1.6% FSR 0 SPT8100 7 1/9/02 Table II – Timing Parameters Figure 5 – Timing Diagram 2 CLK Parameter tD1 Digital Outputs tD2 Min Typ Max Units CLK high to Data Valid tD1 18 24 401 OE inactive to HiZ tD2 10 16 30 ns OE active to Data Valid tD3 10 16 30 ns 1 OE Symbol ns Conditions: load capacitance = 20 pF, VOH = 3.3 V tD3 Typical Differential Linearity Error (DLE) DLE (LSB) FFT Plot Test Conditions: ƒIN = 2 MHz ƒCLK = 4.4 MHz PGA Gain = 18 dB Test Conditions: ƒIN = 75 kHz ƒCLK = 4.4 MHz REXT = 1.08 kΩ ADC Input (Post PGA) = –5.4 dBFS TA = +25 °C Two-Tone Intermodulation FFT PGA Gain = 0 dB Near Full-Scale Input Spurious-Free Dynamic Range 100 0.9 MHz, low 95 90 0.9 MHz, med 0.9 MHz, high 85 SFDR (dBc) 80 2 MHz, high 75 2 MHz, med 70 2 MHz, low 65 3 MHz, high 60 55 3 MHz, med 50 Test Conditions: ƒ1 = 890 kHz ƒ2 = 900 kHz ƒCLK = 4.4 MHz PGA Gain = 6 dB 3 MHz, low REXT = 1.43 kΩ ADC Input (Post PGA) = –8.0 dBFS TA = +25 °C 45 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 Composite Level at ADC Input (dBFS) 0 5 VP-P Test Conditions: Med: REXT=1.24 kΩ @109 mA 10 MSPS, 5 V, 25 °C Low: REXT=1.43 kΩ @96 mA High: REXT=1 kΩ @129 mA SPT8100 8 1/9/02 PACKAGE OUTLINE 44-Lead LQFP A B SYMBOL Pin 1 Index 0.465 0.480 11.80 12.20 B 0.390 0.398 9.90 10.10 C 0.390 0.398 9.90 10.10 D 0.465 0.480 11.80 12.20 F E D MILLIMETERS MIN MAX A E C INCHES MIN MAX 0.0315 BSC 0.012 0.018 0.80 BSC 0.30 0.45 G 0.053 0.057 1.35 1.45 H 0.002 0.006 0.05 0.15 I 0.018 0.030 0.45 0.75 J 0.039 typ 1.0 typ K 0–7° 0–7° F G H K I J SPT8100 9 1/9/02 PIN ASSIGNMENTS PIN FUNCTIONS BIASC BIASR VRB VRT AGND VCM GS1 VIN+ GS0 VIN AVDD Pin Name Description 34 35 36 37 39 38 40 41 43 42 44 AGND Analog ground DGND Digital ground D0–D15 Data output bits; D0 is LSB; D15 is MSB CLK 7 27 GS2 OVR Overrange indicator bit (active high) OE 8 26 N/C N/C No connect D0 (LSB) 9 25 OVR GS[2:0] 3-bit PGA gain setting control inputs 10 24 D15 (MSB) AVDD Analog +5.0 V supply 11 23 D14 RS Resets internal state of chip (active low) RDY Initialization in progress indicator; RDY goes low during reset initialization. Chip is ready for normal operation when RDY is high. BIASC External bias capacitor connection BIASR External bias resistor connection VRT, VRB ADC reference voltage outputs VCM Common mode reference voltage output D1 D2 D13 AVDD D12 28 22 Output enable (active high) 6 D11 OE OVDD 21 AGND D10 29 20 5 19 OGND D9 Master reference clock D8 CLK 18 RS 17 Digital outputs supply (+3.3/5 V) 30 D7 OVDD 4 D6 N/C DVDD 16 3 31 15 Ground for digital I/O DVDD D5 Digital +5.0 V supply OGND D4 DVDD N/C 14 RDY 32 13 33 2 D3 1 12 AGND DGND VIN+, VIN– Analog inputs to the PGA ORDERING INFORMATION PART NUMBER SPT8100SIT TEMPERATURE RANGE PACKAGE –40 to +85 °C 44L LQFP DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com © Copyright 2002 Fairchild Semiconductor Corporation SPT8100 10 1/9/02