SSC SS6526

SS6526
Dual USB High-Side Power Switch
FEATURES
DESCRIPTION
• 110mΩ (5V Input) High-Side MOSFET Switch.
The SS6526 is a dual high-side power switch
500mA Continuous Load Current per Channel.
for self-powered and bus-powered Universal
110µA Typical On-State Supply Current.
Serial Bus (USB) applications. Both high-side
1µA Typical Off-State Supply Current.
switches are MOSFET with 110m Ω RDS(ON),
Current-Limit / Short Circuit Protection.
which meets USB voltage drop requirements for
Thermal Shutdown Protection under Overcurrent
maximum transmission wire length.
Condition.
Multi-purpose
Undervoltage Lockout Ensures that Switch is off
indicates
at Start Up.
shutdown, or undervoltage lockout for each
Output
can
be
Forced
Higher
(Off-State).
Open-Drain Fault Flag.
than
Input
open-drain
over-current
fault
flag
limiting,
output
thermal
channel. Output current is typically limited to 1A,
and the thermal shutdown functions of the
power switches independently control their
channel under overcurrent condition.
Slow Turn ON and Fast Turn OFF.
Enable Active-High or Active-Low.
Guaranteed minimum output rise time limits
inrush current during hot plug-in as well as
minimizing EMI and prevents the voltage at
APPLICATIONS
upstream port from dropping excessively.
USB Power Management.
Hot Plug-In Power Supplies.
Battery-Charger Circuit.
Pb-free; RoHS-compliant
10/23/2007 Rev.1.00
www.SiliconStandard.com
1
SS6526
TYPICAL APPLICATION CIRCUIT
VCC
5.0V
+
10K
33µF
4.50V to 5.25V
Upstream VBUS
100mA max
10K
SS6722
VBUS
IN
D+
+
DGND
1µF
CIN
USB Controller
OUT
10µF
COUT
GND
ON/OFF
CTLA
OUTA
OVERCURRENT
FLGA
IN
OVERCURRENT
FLGB
GND
VIN
+
Ferrite
Bead
AIC1526
ON/
VBUS
+
0.1µF
33µF
*
D+
0.01µF
DGND
CTLB OUTB
GND
DATA
DATA
*
33µF, 16V Tantalum, or
100µF, 10V Electrolytic
Bold line indicate high- current traces
+
33µF
*
VBUS
D+
0.01µF
DGND
DATA
Two-Port Self-Powered Hub
ORDERING INFORMATION
SS6526 - XXXXX
PIN CONFIGURATION
PACKING TYPE
TR: TAPE & REEL
TB: TUBE
DIP-8
SOP-8
TOP VIEW
CTLA 1
PACKAGING TYPE
N: DIP-8
S: SOP-8
O: MSOP-8
C: Commercial
G: Lead Free Commercial
FLGA 2
8 OUTA
7 IN
FLGB 3
6 GND
CTLB 4
5 OUTB
MSOP-8
TOP VIEW
CTLA 1
CONTROL POLARITY
0: Active Low
1: Active High
FLGA 2
8 OUTA
7 IN
FLGB 3
6 OUTB
CTLB 4
5 GND
Example: SS6526-0CSTR
Active Low Version, in SOP-8 Package & Taping
& Reel Packing Type
(CN is not available in TR packing)
SS6526-1PSTR
Active High Version, in Lead Free SOP-8 Package
& Taping & Reel Packing Type
10/23/2007 Rev.1.00
www.SiliconStandard.com
2
SS6526
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VIN)
7.0V
Fault Flag Voltage (VFLG)
7.0V
Fault Flag Current (IFLG)
50mA
Control Input (VCTL)
-0.3V ~7V
Operating Temperature Range
-40°C~85°C
Junction Temperature
125°C
Storage Temperature Range
-65°C ~ 150°C
Lead Temperature (Soldering, 10sec)
260°C
Thermal Resistance, θJA (Junction to Ambient) DIP-8
100°C/W
(Assume no Ambient Airflow, no Heatsink)
SOP-8
160°C/W
MSOP-8
180°C/W
Thermal Resistance, θJC (Junction to Case)
DIP-8……………………………………..60°C /W
SOP-8……………………………………40°C /W
MSOP-8………………………………….75°C /W
Absolute Maximum Ratings are those values beyond which the life of a device may be
impaired.
TEST CIRCUIT
VCC
+5V
10K R1
10K R2
ON
10Ω
CTLA
OUTA
FLGA
IN
OFF
R4
0.1µF
C1
FLGB
GND
CTLB
OUTB
10Ω
ON
OFF
10/23/2007 Rev.1.00
R4
SS6526
www.SiliconStandard.com
3
SS6526
ELECTRICAL CHARACTERISTICS
(VIN= 5V, TA=25°C, unless otherwise specified.) (Note 1)
PARAMETERS
Supply Current
Control Input Voltage
Control Input Current
CONDITIONS
MIN.
TYP.
MAX.
VCTL =Logic “0”, OUT=Open
0.75
5
VCTL =Logic “1”, OUT=Open
110
160
VCTL =Logic “0”
VCTL =Logic “1”
0.8
2.4
VCTL =Logic “0”
0.01
1
VCTL =Logic “1”
0.01
1
Control Input Capacitance
1
Output MOSFET Resistance
110
UNIT
µA
V
µA
pF
150
mΩ
µS
Output Turn-On Rise Delay
RL = 10Ω each Output
100
Output Turn-On Rise Time
RL = 10Ω each Output
1000
2500
µS
Output Turn-Off Delay
RL = 10Ω each Output
0.8
20
µS
Output Turn-Off Fall Time
RL = 10Ω each Output
0.7
20
µS
10
µA
1.25
A
Output Leakage Current
Current Limit Threshold
0.6
1.0
Over Temperature Shutdown
TJ Increasing
135
Threshold
TJ Decreasing
125
Error Flag Output Resistance
VIN = 5V, IL =10 mA
10
25
VIN = 3.3V, IL =10mA
15
40
1
Error Flag Off Current
VFLG = 5V
0.01
UVLO Threshold
VIN Increasing
2.6
VIN Decreasing
2.4
°C
Ω
µA
V
Note 1: Specifications are production tested at TA=25°C. Specifications over the -40°C to 85°C operating
temperature range are assured by design, characterization and correlation with Statistical Quality
Controls (SQC).
10/23/2007 Rev.1.00
www.SiliconStandard.com
4
SS6526
118
150
116
140
ON Resistance (m Ω)
ON Resistance (m Ω)
TYPICAL PERFORMANCE CHARACTERISTICS
114
130
RL=47Ω
TA=25°C
112
120
110
RL=47Ω
TA=25°C
110
108
100
106
90
104
3.0
3.5
4.0
4.5
80
5.5
5.0
-40
Supply Voltage (V)
Fig. 1 ON Resistance vs. Supply Voltage
-20
0
20
40
60
100
80
Temperature (°C)
Fig. 2 Output On Resistance vs. Temperature
3.0
2.8
140
Supply Current (µA)
Threshold Voltage (V)
160
Rising
2.6
Falling
2.4
2.2
2.0
-40
-20
0
20
40
60
80
120
100
Both Switches ON
80
60
100
3
130
0.10
120
0.08
110
Both Switches ON
100
5
6
7
8
0.06
Both Switches OFF
0.04
0.02
90
80
-40
4
Supply Voltage (V)
Fig. 4 ON-State Supply Current vs. Supply Voltage
Supply Current (µA)
Supply Current (µA)
Temperature (°C)
Fig. 3 UVLO Threshold Voltage vs. Temperature
-20
0
20
40
60
80
Temperature (°C)
Fig. 5 ON State Current vs. Temperature
10/23/2007 Rev.1.00
100
0
-40
-20
0
20
40
60
80
100
Temperature (°C)
Fig. 6 OFF-State Current vs. Temperature
www.SiliconStandard.com
5
SS6526
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
(Continued)
1.7
1.6
Enable voltage
Supply Current (µA)
0.08
0.06
Both Switches OFF
0.04
1.5
VEN Rising
1.4
1.3
VEN Falling
1.2
0.02
1.1
0
1.0
3
4
5
6
7
8
Supply Voltage (V)
Fig. 7 OFF-State Current vs. Supply Voltage
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage (V)
Fig. 8 Control Threshold vs. Supply Voltage
Control (V)
6
FLG
4
2
VOUT
0
1A
Output (V)
5
3
RL=47Ω
1
IOUT
-1
0.0
0.5
1.0
1.5
2.0
2.5
Time (mS)
Fig. 9 Turn-On, Turn-Off Characteristics
10/23/2007 Rev.1.00
www.SiliconStandard.com
Fig. 10 Current Limit Response
6
SS6526
BLOCK DIAGRAM
OUTA
Driver
CTLA
Thermal
Shutdown
Charge
Pump
Current
Limit
UVLO
Current
Limit
CTLB
FLGB
CS
Driver
IN
CS
Power N-MOSFET
Charge
Pump
Power N-MOSFET
FLGA
OUTB
PIN DESCRIPTIONS
PIN 1: CTLA - Controls the turn-on/turn-off of
channel A MOSFET with TTL as
a control input. Active high for
SS6526-1 and active low for
SS6526-0.
PIN 4: CTLB - Controls the turn-on/turn-off of
channel B MOSFET with TTL
as a control input. Active High
for SS6526-1 and active low
for SS6526-0.
PIN 2: FLGA - An active-low and open-drained
fault flag output for channel A.
FLGA is an indicator for current
limit when CTLA is active. In
normal mode operation (CTLA
or/and CLTB is active), it also
can indicate thermal shutdown
or undervoltage.
PIN 5: OUTB - Channel B MOSFET switch
output.
PIN 6: GND
- Chip power ground.
PIN 7: IN
- Power supply input.
PIN 8: OUTA - Channel A MOSFET switch
output.
PIN 3: FLGB - An active-low and open-drained
fault flag output for channel B.
FLGB is an indicator for current
limit when CTLB is active. In
normal mode operation (CTLB
or/and CLTA is active), it also
can indicate thermal shutdown
or undervoltage.
10/23/2007 Rev.1.00
www.SiliconStandard.com
7
SS6526
APPLICATION INFORMATION
Error Flag
Supply Filtering
An error Flag is an open-drained output of an
N-channel MOSFET. FLG output is pulled low to
signal the following fault conditions: input
undervoltage, output current limit, and thermal
shutdown.
A 0.1µF to 1µF bypass capacitor from IN to GND,
located
near
the
device,
is
strongly
recommended to control supply transients.
Without a bypass capacitor, an output short may
cause sufficient ringing on the input (from supply
lead inductance) to damage internal control
circuitry.
Current Limit
The current limit threshold is preset internally. It
protects the output MOSFET switches from
damage resulting from undesirable short circuit
conditions or excess inrush current, which is
often encountered during hot plug-in. The low
limit of the current limit threshold of the SS6526
allows a minimum current of 0.6A through the
MOSFET switches. The error flag signals when
any current limit conditions occur.
Thermal Shutdown
When temperature of SS6526 exceeds 135°C
for any reasons, the thermal shutdown function
turns both MOSFET switches off and signals the
error flag. A hysteresis of 10°C prevents the
MOSFETs from turning back on until the chip
temperature drops below 125°C. However, if
thermal shutdown is triggered by chip
temperature rise resulting from overcurrent fault
condition of either one of the MOSFET switches,
the thermal shutdown function will only turn off
the switch that is in overcurrent condition and
the other switch can still remain its normal
operation. In other words, the thermal shutdown
function of the two switches is independent of
each other in the case of overcurrent fault.
10/23/2007 Rev.1.00
Transient Requirements
USB supports dynamic attachment (hot plug-in)
of peripherals. A current surge is caused by the
input capacitance of downstream device. Ferrite
beads are recommended in series with all power
and ground connector pins. Ferrite beads
reduce EMI and limit the inrush current during
hot-attachment by filtering high-frequency
signals.
Short Circuit Transient
Bulk capacitance provides the short-term
transient
current
needed
during
a
hot-attachment event. A 33µF/16V tantalum or a
100µF/10V electrolytic capacitor mounted close
to downstream connector each port should
provide transient drop protection.
Printed Circuit Layout
The power circuitry of USB printed circuit boards
requires a customized layout to maximize
thermal dissipation and to minimize voltage drop
and EMI.
www.SiliconStandard.com
8
SS6526
APPLICATION CIRCUIT
USB
Controller
AIC1526
1
Vbus
2
3
USB Host
4.7uF
4
CTLA
OUTA
FLGA
IN
FLGB
GND
CTLB
OUTB
8
Vbus
7
6
0.1uF
33uF
Downstream
USB Device
5
GND
GND
Bus Powered Hub
Cable
Cable
Fig. 11 Soft Start (Single Channel)
USB
Controller
SS6526
1
Vbus
2
3
USB Host
4.7uF
4
CTLA
OUTA
FLGA
IN
FLGB
GND
CTLB
OUTB
8
USB
Device
7
6
0.1uF
5
33uF
USB
Device
33uF
GND
Cable
USB Peripheral
Fig. 12 Inrush Current-Limit Application
10/23/2007 Rev.1.00
www.SiliconStandard.com
9
SS6526
PHYSICAL DIMENSIONS (unit: mm)
SOP-8
D
h X 45°
E
A
H
S
Y
M
B
O
L
A
e
SEE VIEW B
SOP-8
MILLIMETERS
MIN.
MAX.
A
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
A
e
A1
B
4.00
1.27 BSC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
0°
8°
θ
C
WITH PLATING
0.25
BASE METAL
GAUGE PLANE
SEATING PLANE
VIEW B
θ
L
Note:
1.Refer to JEDEC MS-012AA.
2.Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 6
mil per side.
3.Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash or protrusion shall not exceed 10 mil per side.
4.Controlling dimension is millimeter, converted inch dimensions
are not necessarily exact.
10/23/2007 Rev.1.00
www.SiliconStandard.com
10
SS6526
DIP-8
E
D
0.38
E1
GAUGE PLANE
eA
A
A2
eB
b
A
A
D1
b2
e
c
L
A1
WITH PLATING
BASE METAL
SECTION A-A
S
Y
M
B
O
L
DIP-8
MILLIMETERS
MAX.
MIN.
5.33
A
A1
0.38
A2
2.92
4.95
b
0.36
0.56
b2
1.14
1.78
c
0.20
0.35
D
9.01
10.16
D1
0.13
E
7.62
8.26
E1
6.10
7.11
e
2.54 BSC
eA
7.62 BSC
eB
L
10.92
2.92
3.81
Note:
1.Refer to JEDEC MS-001BA.
2.Dimension D, D1 and E1 do not include mold flash or
protrusions. Mold flash or protrusion shall not exceed 10 mil.
3.Controlling dimension is millimeter, converted inch dimensions
are not necessarily exact.
10/23/2007 Rev.1.00
www.SiliconStandard.com
11
SS6526
MSOP-8
D
S
Y
M
B
O
L
MSOP-8
MILLIMETERS
MAX.
MIN.
E
E1
A
A A
A1
0.05
0.15
A2
0.75
0.95
b
0.25
0.40
c
0.13
0.23
D
2.90
E
SEE VIEW B
E1
A2
e
1.10
A
0.65 BSC
0.40
0.70
0°
6°
A1
θ
3.10
2.90
e
L
3.10
4.90 BSC
b
0.25
c
WITH PLATING
BASE METAL
SECTION A-A
θ
L
VIEW B
Note:
1. Refer to JEDEC MO-187AA.
2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 6
mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per
side.
4. Controlling dimension is millimeter, converted inch dimensions
are not necessarily exact.
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
10/23/2007 Rev.1.00
www.SiliconStandard.com
12