SS6802 TWO-CELL LITHIUM-ION BATTERY PROTECTION IC FEATURES DESCRIPTION Ultra-Low Quiescent Current at 10µA (VCC=7V, VC=3.5V). Ultra-Low Power-Down Current at 0.2µA (VCC =3.8V, VC=1.9V). Wide Supply Range: 2 to 18V. Precision Overcharge Protection Voltage 4.35V ± 30mV for the SS6802A 4.30V ± 30mV for the SS6802B 4.25V ± 30mV for the SS6802C Built-in Delay Circuits for Overcharge, Over-discharge and Overcurrent Protection. Overcharge and Overdischarge Delay Time can be Extended by External Capacitors. Built-in Cell-balancing Bleeding Network under Overcharge Condition. The SS6802 battery protection IC is designed to protect lithium-ion batteries from damage due to overcharging, overdischarging, and overcurrent for two series cells in portable phones and laptop computers. It can be a part of the low-cost charge control system within a two-cell lithium-ion battery pack. Safe and full utilization charging is ensured by the accurate ±30mV overcharge detection. Three different specification values for overcharge protection voltage are provided for various protection requirements. The very low standby current drains little current from the cells while in storage. APPLICATIONS Pb-free; RoHS-compliant Protection IC for Two-Cell Lithium-Ion Battery Pack. TYPICAL APPLICATION CIRCUIT VBAT+ **R1 8 BATTERY 1 C1 1µF BATTERY 2 C2 1µF VCC TC 5 *CTC 6 VC TD 3 *CTD 4 GND OC 1 **R2 M1 CEM9926 2 OD CS SS6802 R3 1M 7 Q1 R6 1K M2 R4 1M R5 C3 0.01µF 1M CEM9926 VBAT - *CTC & CTD are optional for delay time adjustment. **R1 & R2: Refer application informations. Protection Circuit for Two-Cell Lithium-Ion Battery Pack 02/26/2008 Rev.1.00 www.SiliconStandard.com 1 SS6802 ORDERING INFORMATION SS6802XXXXX PIN CONFIGURATION PACKING TYPE TR: TAPE & REEL TB: TUBE TOP VIEW PACKAGE TYPE S: SOP-8 OC 1 8 VCC OD 2 7 CS TD 3 6 VC GND 4 5 TC G: LEAD FREE COMMERCIAL OVERCHARGE PROTECTION Example: SS6802AGSTR VOLTAGE 4.35V version, in A: 4.35V B: 4.30V SO-8 Lead Free C: 4.25V Package & Tape & Reel Packing Type ABSOLUTE MAXIMUM RATINGS Supply Voltage ....................................……………..................................................... 18V DC Voltage Applied on VC, CS, OC, OD Pins ...............…………….............................. 18V DC Voltage Applied on TC, TD Pins ...............…………………..…….............................. Operating Temperature Range 5V .......................................….………….............. -40°C~85°C Storage Temperature Range .........................…………………..................... - 65°C~150°C Junction Temperature .........................…………………...................………………… 125°C Lead Temperature (Soldering 10s) .........................…………………...................…. 260°C Thermal Resistance Junction to Case SOP-8 .........................……………… 40°C/W Thermal Resistance Junction to Ambient SOP-8 .........................…………… 160°C/W (Assume no ambient airflow, no heatsink) Absolute Maximum Rating are those value beyond which the life of a device may be impaired. TEST CIRCUIT ICO 1 OC VCC ICC 8 VCC VCS VOD + 2 OD CS 7 3 TD VC 6 4 GND TC 5 CTD SS6802 02/26/2008 Rev.1.00 IC VC + CTC www.SiliconStandard.com 2 SS6802 ELECTRICAL CHARACTERISTICS (TA=25°C, unless otherwise specified.) PARAMETER TEST CONDITIONS SYMBOL MIN. TYP. MAX. UNIT Supply Current in Normal Mode VCC=7V, VC=3.5V ICC 10 15 µA Supply Current in Power-Down Mode VCC=4.8V, VC=2.4V IPD 0.8 1.2 µA VC Pin Input Current VCC=7V, VC=3.5V IC 400 600 nA 4.32 4.35 4.38 4.27 4.30 4.33 4.22 4.25 4.28 AIC1802A Overcharge Protection Voltage AIC1802B VOCP AIC1802C V Overcharge Release Voltage VOCR 3.85 4.0 4.15 V Overdischarge Protection Voltage VODP 2.25 2.4 2.55 V Overdischarge Release Voltage VODR 2.85 3.0 3.15 V Overcurrent Protection Voltage VCC=7V VOIP 135 150 165 mV Overcharge Delay Time (1) VCC=8.6V, VC=4.3V, CTC=0µF TOC1 12 25 38 mS Overcharge Delay Time (2) VCC=8.6V, VC=4.3V, CTC=0.47µF TOC2 0.7 1.1 1.5 S Overdischarge Delay Time (1) VCC=4.8V, VC=2.4V, CTD=0µF TOD1 12 25 38 mS Overdischarge Delay Time (2) VCC=4.8V, VC=2.4V, CTD=0.47µF TOD2 0.7 1.1 1.5 S Overcurrent Delay Time (1) VCC=7V, VC=3.5V, VCS=0.15V TOI1 4 9 14 mS Overcurrent Delay Time (2) VCC=7V, VC=3.5V, VCS=0.36V TOI2 1.0 2.0 3.0 mS OC Pin Source Current VCC=8.6V, VC=4.3V, OC Pin Short to GND ICO 270 400 530 µA OD Pin Output “H” Voltage 02/26/2008 Rev.1.00 VDL www.SiliconStandard.com VCC-0.1 VCC-0.02 V 3 SS6802 ELECTRICAL CHARACTERISTICS (Continued) TEST CONDITIONS SYMBOL PARAMETER OD Pin Output “L” Voltage MIN. TYP. MAX. UNIT 0.01 0.1 V VDH Charge Detection Threshold Voltage VCC=4.8V VCH -0.55 -0.4 Unbalance Discharge Current VCC=8.3V, VC=4V IUD 5.4 7.7 V 10 mA Note1: Specifications are production tested at TA = 25°C. Specifications over the -40°C to 85°C operating Temperature range are assured by design, characterization and correlation with Statistical Quality Controls (SQC). TYPICAL PERFORMANCE CHARACTERISTICS 10.7 Power-Down Current (µA) VC=1/2VCC TA=25°C Supply Current (µA) 10.5 10.3 10.1 9.9 0.8 0.65 VC=1/2VCC TA=25°C 0.5 0.35 0.2 9.7 5.5 6.5 7.5 3.8 8.5 4.3 Supply Voltage (V) Fig. 1 Fig. 2 Supply Current vs. Supply Voltage Overcurrent Protection Voltage (mV) Overcharge Protection Voltage (V) 4.32 4.315 AIC1802B 4.31 4.305 4.3 -20 -10 0 10 20 30 40 50 60 70 5.8 VCC=7V VC=3.5V 147.5 145 142.5 140 -20 -10 0 10 20 30 40 50 60 70 Temperature (°C) Overcharge Protection Voltage vs. Temperature 02/26/2008 Rev.1.00 5.3 150 Temperature (°C) Fig. 3 4.8 Supply Voltage (V) Power-down Current vs. Supply Voltage Fig. 4 www.SiliconStandard.com Overcurrent Protection Voltage vs. Temperature 4 SS6802 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) VCC=7V VC=3.5V Power-Down Current (µA) Supply Current (µA) 12.5 11.5 10.5 9.5 1.1 VCC=4.8V VC=2.4V 0.9 0.7 0.5 8.5 -20 -10 0 10 20 30 40 50 60 -20 70 -10 0 10 Temperature (°C) Supply Current vs. Temperature Fig. 6 30 40 50 60 70 Power-Down Current vs. Temperature 2.420 4.025 Overcharge Release Voltage (V) Overdischarge Protection Voltage Fig. 5 20 Temperature (°C) 2.415 2.410 2.405 2.400 2.395 -20 -10 0 10 20 30 40 50 60 70 4.020 4.015 4.010 4.005 -20 -10 Temperature (°C) 10 20 30 40 50 60 70 Temperature (°C) Fig. 7 Overdischarge Protection Voltage vs. Temperature Overdischarge Release Voltage (V) 0 Fig. 8 Overcharge Release Voltage vs. Temperature 3.025 3.020 3.015 3.010 3.005 -20 -10 0 10 20 30 40 50 60 70 Temperature (°C) Fig. 9 Overdischarge Release Voltage vs. Temperature 02/26/2008 Rev.1.00 www.SiliconStandard.com 5 SS6802 BLOCK DIAGRAM VCC 8 OVERCHARGE DETECTOR 1 5 OVERCHARGE DELAY CIRCUIT TC 450 OVERDISCHARGE DETECTOR 1 VC 6 OVERDISCHARGE DELAY CIRCUIT 3 UNBALANCE DISCHARGE OVERCHARGE DETECTOR 2 LOGIC CONTROL 4 OVERDISCHARGE DETECTOR 2 OVERCURRENT DELAY CIRCUIT OD OVERCURRENT DETECTOR TD VCC WAKEUP 450 GND POWERDOWN TIMING GENERATION 1 OC CHARGE DETECTION 7 2 CS PIN DESCRIPTIONS PIN 1: OC - PMOS open drain output for control of the charge control MOSFET M2. When overcharge occurs, this pin sources current to switch the external NPN Q1 on, and charging is inhibited by turning off the charge control MOSFET M2. PIN 2: OD - Output pin for control of discharge control MOSFET When overdischarge occurs, pin goes low to turn off discharge control MOSFET and discharging is inhibited. PIN 3: TD - Overdischarge delay time setting pin. - Overcharge delay time setting pin. PIN 6: VC - To be connected to the positive terminal of the lower cell and the negative terminal of the upper cell. PIN 7: CS - Input pin for current sensing. Using the drain-source voltage of the discharge control MOSFET M1 (voltage between CS and GND), it senses discharge current during normal mode and detects whether charging current is present during power down mode. the M1. this the M1 PIN 4: GND - Ground pin. This pin is to be connected to the negative terminal of the lower battery cell. 02/26/2008 Rev.1.00 PIN 5: TC PIN 8: VCC - Power supply pin. It is to be connected to the positive terminal of the upper cell. www.SiliconStandard.com 6 SS6802 APPLICATION INFORMATION THE OPERATION circuit for the cell under overcharge condition. Overcharge Protection When the voltage of either of the battery cells Charge Detection after Overdischarge exceeds VOCP (overcharge protection voltage) When overcharge occurs, the discharge control beyond the overcharge delay time period, MOSFET M1 turns off and discharging is charging is inhibited by the turning-off of the inhibited. However, charging is still permitted charge control MOSFET M2. The overcharge through the parasitic diode of M1. Once the delay time (TOC) defaults to 25mS and can be extended by adding a capacitor CT C . Inhibition of charger is connected to the battery pack, the charging is immediately released when the generation and detection circuitry and goes into voltage of the overcharged cell becomes lower normal mode. Charging is determined to be in than VOCR (overcharge release voltage) through progress if the voltage between CS and GND is discharge. below –0.4V (charge detection threshold voltage SS6802 immediately turns on all the timing VCH) Overdischarge Protection When the voltage of either of the battery cells Overcurrent Protection goes below VODP (overdischarge protection In normal mode, the SS6802 continuously voltage) beyond the overdischarge delay time monitors the discharge current by sensing the period, discharging is inhibited by the turning-off voltage of CS pin. If the voltage of CS pin of the discharge control MOSFET M1. The exceeds VOIP (overcurrent protection voltage) overdischarge delay time (TOD) defaults to 25mS beyond overcurrent delay time TOI period, the and can be extended by adding a capacitor CTD. Inhibition of discharging is immediately released overcurrent when the voltage of the overdischarged cell discharge control MOSFET M1. Discharging (overdischarge must be inhibited for at least 256mS after becomes higher than VODR Power-Down after Overdischarge When overdischarge occurs, the SS6802 will go into power-down mode, turning off all the timing generation and detection circuitry to reduce the quiescent current to 0.8µA (VCC=4.8V). In the where one battery cell is overdischarged while the other under overcharge condition, the SS6802 will turn off all the detection circuits except the overcharge detection 02/26/2008 Rev.1.00 operates and discharging is inhibited by turning-off of the external case circuit overcurrent takes place to avoid damage to release voltage) through charging. unusual protection control MOSFETs due to rapidly switching transient between VBAT+ and VBATterminals. The overcurrent condition returns to the normal mode when the load is released and the impedance between the VBAT+ and VBATterminals is 10MΩ or higher. For the sake of protection of the external MOSFETs, the larger the CS pin voltage (which means the larger discharge current) the shorter the overcurrent delay time. The relationship between voltage of www.SiliconStandard.com 7 SS6802 CS pin and overcurrent delay time TOI is tabulated as below. VCS (V) TOI (S) 150m 9.0m 200m 5.6m 300m 2.8m 360m 2.0m 1V 540µ 3V 290µ 5V 270µ CTC (F) TOC (S) 0µ 25m 0.1µ 320m 0.3µ 890m 0.47µ 1.12 0.57µ 1.43 CTD (F) TOD (S) 0µ 25m 0.1µ 320m 0.3µ 820m 0.47µ 1.08 0.57µ 1.39 Unbalanced Discharge after Overcharge When either of the battery cells is overcharged, the SS6802 will automatically discharge the overcharged cell at about 7.7mA until the voltage of the overcharged cell is equal to the voltage of the other cell. If the voltage of the other cell is below VOCR, the internal cell-balance “bleeding” will proceed until the voltage of the overcharged cell decreases to VOCR. Selection of External Control MOSFETs Because the overcurrent protection voltage is preset, the threshold current for overcurrent detection is determined by the turn-on resistance of the discharge control MOSFET M1. The turn-on resistance of the external control MOSFETs can be determined by the equation: RON=VOIP/IT (IT is the overcurrent threshold DESIGN GUIDE current). Adjustment of Overcharge and Overdischarge Delay Time times default to 25mS and can be extended by adding the external capacitors CTC and CTD, respectively. Increasing the capacitance value will the delay time. The relationship between capacitance of the external capacitors and delay time is tabulated as below: example, if the overcurrent threshold current IT is designed to be 5A, the Both the overcharge and overdischarge delay increase For turn-on resistance of the external control MOSFETs must be 30mΩ. Users should be aware that turn-on resistance of the MOSFET changes with temperature variation due to heat dissipation. It changes with the voltage between gate and source as well. (Turn-on resistance of a MOSFET increases as the voltage between gate and source decreases). Once the turn-on resistance of the external MOSFET changes, the 02/26/2008 Rev.1.00 www.SiliconStandard.com 8 SS6802 overcurrent threshold current will change accordingly. release voltage and bleeding function. The relationship among Vrelease1,Vrelease2, R1, and R2 is shown as following equations: Vrelease1=VOCR+IUD*R1 Suppressing the Ripple and Disturbance from Charger Vrelease2=VOCR+IUD*R2 To suppress the ripple and disturbance from where Vrelease1 is Battery 1, real overcharge release voltage Vrelease2 is Battery 2, real overcharge release voltage charger, connecting C1 to cell 1 and C2 to cell 2 is necessary. Controlling the Charge Control MOSFET R3, R4, R5 and NPN transistor Q1 are used to Therefore, resistance of R1 and R2 should not switch the charge control MOSFET M2. If higher than 30Ω. Otherwise, overcharge release overcharge does not occur, no current flows out voltage from OC pin and Q1 are turned off, then M2 is protection voltage and the charging current may turned on. When overcharge occurs, current oscillate. In addition, if overcharge protection flows out from OC pin and Q1 is turned on, which function occurs, SS6802 will discharge the turns off M2 in turn. High resistance for R3, R4, overcharged cell and will stop bleeding function and R5 is recommended for reducing loading of even if the voltage is not equal to the other. The the batteries. recommended resistance of R1 and R2 is from would be higher than overcharge 20 to 30Ω. Latch-Up Protection at CS Pin R6 is used for latch-up protection when charger is connected under overdischarge condition, and also for overstress protection when charger is connected in reverse. The charge detection function after overdischarge is possibly disabled by larger value of R6. Resistance of 1KΩ is recommended. Effect of C3 C3 has to be applied to the circuit. Because C3 will keep SS6802 to be charged after overdischarge occurred. In addition, when the differential voltage between charger and battery pack is higher than 2.1V and overcharge protection function work, C3 will avoid battery pack from being charged even if the battery Selection of R1 and R 2 voltage lower than 4V (To avoid battery pack from R1 and R2 are used to avoid large current flow being through the battery pack under the situation of IC situation). The battery pack can be charged again damage or pin short. On the other hand, till remove it from charger. charged under charger malfunction resistance of R1 and R2 will affect overcharge 02/26/2008 Rev.1.00 www.SiliconStandard.com 9 SS6802 PHYSICAL DIMENSIONS SOP-8 (unit: mm) D h X 45° E A H S Y M B O L A e SEE VIEW B SOP-8 MILLIMETERS MIN. MAX. A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 A e A1 B 4.00 1.27 BSC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0° 8° θ C WITH PLATING 0.25 BASE METAL GAUGE PLANE SEATING PLANE VIEW B θ L Note: 1.Refer to JEDEC MS-012AA. 2.Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3.Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash or protrusion shall not exceed 10 mil per side. 4.Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 02/26/2008 Rev.1.00 www.SiliconStandard.com 10