SSCNE555 Elektronische Bauelemente Single Timer RoHS Compliant Product Description The SPNE555 is a highly stable timer IC that can be operated in astable mode and monostable mode. For monostable mode: time delay is controlled by one external and one capacitor. For stable mode: frequency and duty cycle are accurately controlled with two external resistors and one capacitor. Features Package Dimensions High current driver capability (=200mA) Adjustable duty cycle timing form sec to hours turn off time less than 2 sec Applications Precision timing Pulse generation Time delay generation REF. A B C D E F Millimeter Min. Max. 5.80 4.80 3.80 0 0.40 0.19 6.20 5.00 4.00 8 0.90 0.25 REF. Millimeter Min. Max. M H L J K G 0.10 0.25 0.35 0.49 1.35 1.75 0.375 REF. 45 1.27 TYP. Block Diagram and Simplified Application & Pin Configuration http://www.SeCoSGmbH.com/ 01-Jun-2006 Rev. A Any changing of specification will not be informed individual Page 1 of 5 SSCNE555 Elektronische Bauelemente Single Timer Absolute Maximum Ratings (Ta = 25 °C) Parameter Supply Voltage Differential Input Voltage Input Voltage Power Dissipation Opearting, Storage Temperature Symbol Value Units VCC IO Tlead PD 16 200 300 440 0~70, -65~150 V mA °C mW TOPR, TSTG °C Electrical Characteristics (Ta = 25 °C, VCC = 5 ~ 15V) Parameter Symbol Supply Voltage VCC Supply Current (Note 1) ICC Test Conditions VCC = 5V, RL = ∞ VCC = 15V, RL = ∞ Min Typ Max Units 4.5 - 16 V - 3 10 6 15 mA mA Timing Error (monostable) Initial Accurary (Note 1) ACCUR RA = 1k ~ 100kΩ - 1.0 - % Drift with Temperature Δt/ΔT C = 0.1 μF - 50 - ppm/°C - 0.1 - %/V % Drift with Supply Voltage Δt/ΔVCC Timing Error (astable) Initial Accurary (Note 1) ACCUR RA = 1k ~ 100kΩ - 2.25 - Drift with Temperature Δt/ΔT C = 0.1 μF - 150 - ppm/°C - 0.3 - %/V VC VCC = 15V 10.0 3.33 10.0 3.33 11.0 4.0 10.8 3.55 V VTH VCC = 15V 9.0 2.6 9.2 3.1 - 0.1 0.25 μA VCC = 15V 1.1 4.5 1.67 5 2.2 5.6 V Vtr = 0 - - 2.0 μA 0.7 1.0 V 0.1 0.4 mA 12.75 2.75 0.06 0.3 0.05 12.5 13.3 3.3 0.25 0.75 0.35 15 5 Drift with Supply Voltage Control Voltage Δt/ΔVCC VCC = 5V Threshold Voltage VCC = 5V Threshold Current (Note 3) ITH Trigger Voltage Vtr Trigger Current Itr Reset Voltage Vrst 0.4 Reset Current Irst - VCC = 5V VCC = 15V, Isink = 10mA Low Output Voltage VOL VCC = 15V, Isink = 50mA VCC = 5V, Isink = 5mA VCC = 15V, Isink = 200mA High Output Voltage VOH VCC = 15V, Isink = 100mA VCC = 5V, Isink = 100mA V V Reset Time of Output tR - 100 - nSec Fall Time of Output tF - 100 - nSec ILKG - 20 100 nA Discharge leakage Current Note 1: Supply current when output is high typically 1 mA less at VCC = 5V Note 2: Tested at VCC = 5V and VCC = 15V. Note 3: This will determine the maximum value or RA+RB for 15V operation, the maximum total is R=20MΩ, and for 5V operation the maximum total is R=6.7MΩ. http://www.SeCoSGmbH.com/ 01-Jun-2006 Rev. A Any changing of specification will not be informed individual Page 2 of 5 SSCNE555 Elektronische Bauelemente Single Timer Characteristics Curve VCC = 15 V http://www.SeCoSGmbH.com/ 01-Jun-2006 Rev. A Any changing of specification will not be informed individual Page 3of 5 SSCNE555 Elektronische Bauelemente http://www.SeCoSGmbH.com/ 01-Jun-2006 Rev. A Single Timer Any changing of specification will not be informed individual Page 4 of 5 SSCNE555 Elektronische Bauelemente Single Timer Application Circuit FLIP-FLOP SPNE555 Application Notes The application circuit shows astable mode configuration. Pin 6 (Threshold) is tied to Pin 2 (Trigger) and Pin 4 (Reset) is tied to VCC (Pin 8). The external capacitor C1 of Pin 6 and Pin 2 charges through RA, RB and discharge through RB only. In the internal circuit of GSCNE555, one input of the upper comparator is at voltage of 2/3VCC (R1=R2=R3), another input is connected to Pin 6. As soon as C1 is charging to higher than 2/3VCC, transistor Q1 is turned ON and discharge C1 to collector voltage of transistor Q1. Therefore, the flip-flop circuit is reset and output is low. One input of lower comparator is at voltage of 1/3VCC, discharge transistor Q1 turn off and C1 charges through RA and RB. Therefore, flip-flop circuit is set output high. That is, when C1 charges through RA and RB, output is high and when C1 discharge through RB, output is low. The charge time (output is high) t1 is 0.693 (RA+RB) C1 and the discharge time (output is low) T2 is 0.693RB*C1. In Vcc 1 Vcc Vcc 3 Vcc Vcc Vcc - 2 Vcc 3 =0.693 T1=0.693*(RA+RB)*C1 Thus the total period time T is given by T2=0.693*RB*C1 T=T1+T2=0.693(RA+2RB)*C1 Then the frequency of astable mode is given by f= 1 T = 1.44 1.44 (RA+2RB)*C1 C1 The duty cycle is given by D.C. = T2 T = http://www.SeCoSGmbH.com/ 01-Jun-2006 Rev. A RB RB RA+2RB RA+2RB Any changing of specification will not be informed individual Page 5of 5