ETC SSD1858Z

TABLE OF CONTENTS
1
GENERAL DESCRIPTION................................................................................................................. 1
2
FEATURES ........................................................................................................................................ 2
3
ORDERING INFORMATION .............................................................................................................. 2
4
BLOCK DIAGRAM ............................................................................................................................. 3
5
DIE ARRANGEMENT ........................................................................................................................ 4
6
PIN DESCRIPTION ............................................................................................................................ 9
6.1
RES#............................................................................................................................................ 9
6.2
PS0 .............................................................................................................................................. 9
6.3
PS1 .............................................................................................................................................. 9
6.4
CS# .............................................................................................................................................. 9
6.5
D/C#............................................................................................................................................. 9
6.6
R/W(WR#).................................................................................................................................... 9
6.7
E(RD#) ......................................................................................................................................... 9
6.8
D0 -D7 ........................................................................................................................................... 9
6.9
VDD ............................................................................................................................................... 9
6.10
RVSS ........................................................................................................................................... 10
6.11
CVSS ........................................................................................................................................... 10
6.12
VSS ............................................................................................................................................. 10
6.13
VCI .............................................................................................................................................. 10
6.14
Vout ............................................................................................................................................. 10
6.15
VL5, VL4, VL3 and VL2 ................................................................................................................... 10
6.16
COM0 – COM63 ........................................................................................................................ 10
6.17
ICONS........................................................................................................................................ 10
6.18
COL0 – COL103........................................................................................................................ 10
i
6.19
CL .............................................................................................................................................. 10
6.20
M ................................................................................................................................................ 11
6.21
MID0~MID2................................................................................................................................ 11
6.22
SYNC ......................................................................................................................................... 11
6.23
MODE ........................................................................................................................................ 11
6.24
TEST_IN0~1 .............................................................................................................................. 11
6.25
TEST0~14.................................................................................................................................. 11
6.26
N/C............................................................................................................................................. 11
6.27
Dummy...................................................................................................................................... 11
7
FUNCTIONAL BLOCK DESCRIPTIONS ........................................................................................ 12
7.1
Command Decoder and Command Interface........................................................................ 12
7.2
MPU Parallel 6800-series Interface ........................................................................................ 12
7.3
MPU Parallel 8080-series Interface ........................................................................................ 12
7.4
MPU Serial 4-wire Interface..................................................................................................... 13
7.5
MPU Serial 3-wire interface..................................................................................................... 13
7.6
Graphic Display Data RAM (GDDRAM).................................................................................. 13
7.7
Oscillator Circuit ...................................................................................................................... 13
7.8
LCD Driving Voltage Generator and Regulator .................................................................... 14
7.9
169 Bit Latch ............................................................................................................................ 14
7.10
Level selector ........................................................................................................................... 14
7.11
HV Buffer Cell (Level Shifter).................................................................................................. 14
7.12
Default Setting after Reset...................................................................................................... 15
7.13
LCD Panel Driving Waveform ................................................................................................. 16
COMMAND TABLE .................................................................................................................................... 20
8
7.14
Read Status Byte ..................................................................................................................... 25
7.15
Data Read / Write ..................................................................................................................... 25
COMMAND DESCRIPTIONS .......................................................................................................... 26
ii
8.1
Set Display On/Off ................................................................................................................... 26
8.2
Set Display Start Line.............................................................................................................. 26
8.3
Set Page Address .................................................................................................................... 26
8.4
Set Higher Column Address ................................................................................................... 26
8.5
Set Lower Column Address.................................................................................................... 26
8.6
Set Temperature Coefficient (TC) Value................................................................................ 26
8.7
Set Segment Re-map............................................................................................................... 26
8.8
Set Normal/Reverse Display ................................................................................................... 26
8.9
Set Entire Display On/Off ........................................................................................................ 26
8.10
Set LCD Bias ............................................................................................................................ 26
8.11
Software Reset ......................................................................................................................... 27
8.12
Set COM Output Scan Direction............................................................................................. 27
8.13
Set Power Control Register .................................................................................................... 27
8.14
Set Internal Regulator Resistors Ratio.................................................................................. 27
8.15
Set Contrast Control Register ................................................................................................ 28
8.16
Set frame frequency ................................................................................................................ 29
8.17
Set Multiplex Ratio................................................................................................................... 29
8.18
Set Power Save Mode.............................................................................................................. 29
8.19
Exit Power Save Mode............................................................................................................. 29
8.20
Set N-line Inversion ................................................................................................................. 29
8.21
Exit N-line Inversion ................................................................................................................ 29
8.22
Set DC-DC Converter Factor................................................................................................... 29
8.23
Set Icon Enable ........................................................................................................................ 29
8.24
Start Internal Oscillator ........................................................................................................... 29
8.25
Set Display Data Length.......................................................................................................... 29
8.26
Set Test Mode .......................................................................................................................... 29
8.27
Status register Read................................................................................................................ 30
8.28
Set Gray Scale Mode (White/Light Gray/Dark Gray/Black).................................................. 30
iii
8.29
Set PWM and FRC.................................................................................................................... 30
EXTENDED COMMANDS..................................................................................................................... 30
8.30
OTP setting and programming ............................................................................................... 31
8.31
Enable External Oscillator Input ............................................................................................ 33
9
MAXIMUM RATINGS ....................................................................................................................... 34
10
DC CHARACTERISTICS ................................................................................................................. 35
11
AC CHARACTERISTICS ................................................................................................................. 37
12
APPLICATION EXAMPLES ............................................................................................................ 44
iv
TABLE OF FIGURES
Figure 1 - Block Diagram .............................................................................................................................. 3
Figure 2 – SSD1858 Pin Assignment ........................................................................................................... 4
Figure 3 – Display Data Read with the insertion of Dummy Read.............................................................. 12
Figure 4 - Oscillator Circuitry....................................................................................................................... 13
Figure 5 - SSD1858 Graphic Display Data RAM (GDDRAM) Address Map (with vertical scroll value 30H &
MODE=L) ............................................................................................................................................. 17
Figure 6 - SSD1858 Graphic Display Data RAM (GDDRAM) Address Map (with vertical scroll value 30H &
MODE=H) ............................................................................................................................................ 18
Figure 7 - LCD Display Example “0” ........................................................................................................... 19
Figure 8 - LCD Driving Signal from SSD1858............................................................................................. 19
o
Figure 9 - Contrast Control Voltage Range Curve (TC=-0.14%/ C; VDD=2.775V; VCI=3.5V) ..................... 28
Figure 10 - Contrast Control Flow ............................................................................................................... 28
Figure 11 - OTP programming circuitry....................................................................................................... 31
Figure 12 - Flow chart of OTP program ...................................................................................................... 32
o
Figure 13 - Frame Frequency at different VDD( Temp = 25 C).................................................................. 37
Figure 14 – Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H)............................. 38
Figure 15 - Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H) ............................. 39
Figure 16 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L) .............................. 40
Figure 17 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L) .............................. 41
Figure 18- Serial Timing Characteristics (PS0 = L) .................................................................................... 42
Figure 19 - Serial Timing Characteristics (PS0 = L) ................................................................................... 43
LIST OF TABLE
Table 1 - Ordering Information ...................................................................................................................... 2
Table 2 - SSD1858 Series Die Pad Coordinates .......................................................................................... 5
Table 3 - PS0 & PS1 Interface ...................................................................................................................... 9
Table 4 - Vout > VL5 > VL4 > VL3 > VL2 > VSS Relationship ............................................................................ 10
Table 5 – Mode setting................................................................................................................................ 11
Table 6 -Modes of Operation ...................................................................................................................... 13
Table 7 - COMMAND TABLE...................................................................................................................... 20
Table 8 – Extended Command Table ......................................................................................................... 24
Table 9 - Read Status Byte ......................................................................................................................... 25
Table 10 - Address Increment Table........................................................................................................... 25
Table 11 - Commands Required for R/W (WR#) Actions on RAM ............................................................. 25
Table 12 - Maximum Ratings (Voltage Referenced to VSS) ........................................................................ 34
Table 13 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 1.8 to 3.3V,
TA = -40 to 85°°C).................................................................................................................................. 35
Table 14 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD, VCI = 2.7V, TA
= -40 to 85°°C) ...................................................................................................................................... 37
Table 15 – Parallel Timing Characteristics (TA = -40 to 85°°C, VDD = 1.8V, VSS =0V) ................................. 38
Table 16 – Parallel Timing Characteristics (TA = -40 to 85°°C, VDD = 2.7, VSS =0V).................................... 39
Table 17 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V) .................................. 40
Table 18 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.7V, VSS =0V) .................................. 41
Table 19 – Serial Timing Characteristics (TA = -40 to 85°°C, VDD = 2.7V, VSS =0V) .................................... 42
Table 20 – Serial Timing Characteristics (TA = -40 to 85°°C, VDD = 1.8V, VSS =0V) .................................... 43
v
SOLOMON SYSTECH LIMITED
SEMICONDUCTOR TECHNICAL DATA
SSD1858
Advanced Information
LCD Segment / Common Driver with Controller
CMOS
1
General Description
SSD1858 is a single-chip CMOS 4 gray scale LCD driver with controller for liquid crystal dot-matrix
graphic display system. SSD1858 consists of 169 high voltage driving output pins for driving maximum
104 Segments, 64 Commons and 1 icon driving Commons. SSD1858 supports two display modes 96x65
or 104x65 by pin select.
SSD1858 displays data directly from its internal 104x65x2 bits Graphic Display Data RAM
(GDDRAM). Data/Commands are sent from general MCU through a hardware selectable 6800-/8080series compatible Parallel Interface or 3/4 wires Serial Peripheral Interface.
SSD1858 embeds a DC-DC Converter, a LCD Voltage Regulator, an On-Chip Bias Divider,
integrated bias capacitors, integrated booster capacitors and an On-Chip oscillator which reduce the
number of external components. With the special design on minimizing power consumption and
die/package layout, SSD1858 is suitable for any portable battery-driven applications requiring a long
operation period and a compact size.
This document contains information on a new product. Specifications and information herein are subject to change without
notice.
Copyright  2002 SOLOMON Systech Limited
Rev 1.1
09/2002
2
FEATURES
104x64 4 gray scale levels Graphic Display with an Icon Line
Programmable Multiplex ratio (partial display) [16Mux - 65Mux]
Single Supply Operation, 1.8 V - 3.3V
Low Current Sleep Mode (<1.0uA)
On-Chip Voltage Generator / External Power Supply
Software selectable 2X / 3X / 4X / 5X On-Chip DC-DC Converter, with Integrated Capacitors
On-Chip Oscillator
Software Selectable On-Chip Bias Dividers, with Integrated Capacitors
Programmable 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 bias ratio
Maximum +12.0V LCD Driving Output Voltage
Hardware pin selectable for 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel
Interface, 3-wire Serial Peripheral Interface or 4-wire Serial Peripheral Interface
On-Chip 104 x 65 x 2 Graphic Display Data RAM
Re-mapping of Row and Column Drivers
Vertical Scrolling
Display Offset Control
64 Levels Internal Contrast Control
External Contrast Control
Maximum 17MHz SPI or 15MHz PPI operation
Selectable LCD Driving Voltage Temperature Coefficients (5 settings) [-0.14%/oC (POR)]
Programmable Frame Frequency
One time programmable (OTP) capability for Vout adjusts.
3
ORDERING INFORMATION
Table 1 - Ordering Information
Ordering Part Number
SSD1858Z
SSD1858
Rev 1.1
09/2002
Seg
104 /96
Com
64 + 1
Package Form
Gold Bump Die
2
SOLOMON
4
BLOCK DIAGRAM
COM0 to
COM63
ICONS
COL0~COL103
HV Buffer Cell Level Shifter
Level Selector
Vout
VL5
VL4
VL3
VL2
Vss
169 Bit Latch
M
Display Timing
Generator
SYNC
LCD Driving
Voltage Generator
2X / 3X / 4X / 5X
DC/DC Converter,
Voltage Regulator,
Bias Divider,
Contrast Control,
Temperature
Compensation
Oscillator
CL
TEST_IN0~1
104 X 65 X 2 Bits
VCI
TEST0~14
Command Decoder
VSS
VDD
Command Interface
RES# PS0 PS1
CS# D/C#
R/W E
MODE
(WR#) (RD#)
Parallel / Serial Interface
D7
(SDA)
D6 D5 D4 D3 D2 D1 D0
(SCK)
Figure 1 - Block Diagram
3
SSD1858
Rev 1.1
09/2002
SOLOMON
DIE ARRANGEMENT
DUMMY
DUMMY
COM17
COM18
COM19
:
:
:
:
:
COM29
COM30
COM31
DUMMY
DUMMY
5
Pad168 Note:
KEY1
Centre: -5360.40,-449.7
KEY5
Centre: -5372.48, 143.78
y
x
KEY3
Centre: 5344.35, 237.9
KEY4
Centre: -5349.9, 237.9
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
TEST14
CL
M
CL
SYNC
VOUT
VOUT
:
VOUT
VOUT
VSS
VSS
:
VSS
VSS
CVSS
CVSS
:
CVSS
CVSS
RVSS
RVSS
VCI
VCI
:
VCI
VCI
VDD
VDD
:
VDD
VDD
VL5
VL4
VL3
VL2
TEST13
TEST12
TEST11
TEST10
TEST9
TEST8
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1
TEST_IN1
VSS
MODE
VDD
TEST_IN0
VSS
MID2
VDD
MID1
VSS
MID0
VDD
D/C#
D/C#
D/C#
RES#
VSS
CS#
CS#
VDD
D0
D7
D7
D7
D6
D6
D6
D5
D4
D3
D2
D1
D0
D7
D7
VDD
E(RD#)
E(RD#)
R/W(WR#)
R/W(WR#)
VSS
D/C#
D/C#
D/C#
RES#
VDD
CS#
CS#
VSS
PS1
VSS
PS0
VDD
SYNC
M
CL
TEST0
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
30 x VOUT
9 x VSS
1. Diagram showing the die face up.
2. Coordinates are reference to center of the
chip.
3. Unit of coordinates and Size of all
alignment marks are in um.
4. All alignment keys do not contain gold
bump.
25
25
25
15 x CVSS
25
20 x VCI
25
11 x VDD
25
100
100
25
25
25
25
100
50
100
75
18
100
100
Pad1
Die size: 11.66 x 1.41 mm2
Die Thickness: 533±25µm
Bump Height: Normally 18µm
Bump co-planarity < 3 µm (within die)
DUMMY
DUMMY
COM50
COM51
COM52
:
:
:
:
:
COM62
COM63
ICONL
DUMMY
DUMMY
Pad355
DUMMY
DUMMY
DUMMY
COM16
COM15
:
:
:
:
COM1
COM0
ICONR
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COL0
COL1
:
:
:
:
:
:
:
:
:
:
COL102
COL103
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM32
COM33
:
:
:
:
COM48
COM49
DUMMY
DUMMY
DUMMY
KEY2Centre: 3819.2, -419.2
Size:
99.75µ449.7
x 99.75µ
Centre:
5360.-4,
188
Figure 2 – SSD1858 Pin Assignment
SSD1858
Rev 1.1
09/2002
4
SOLOMON
Table 2 - SSD1858 Series Die Pad Coordinates
5
Pad #
Pad
Name
X-pos
Y-pos
Pad #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
TEST0
CL
M
SYNC
VDD
PS0
VSS
PS1
VSS
CS#
CS#
VDD
RES#
D/C#
D/C#
D/C#
VSS
R/W(WR#)
R/W(WR#)
E(RD#)
E(RD#)
VDD
D7
D7
D0
D1
D2
D3
D4
D5
D6
D6
D6
D7
D7
D7
D0
VDD
CS#
CS#
VSS
RES#
D/C#
D/C#
-5601.45
-5534.55
-5467.65
-5400.75
-5333.85
-5266.95
-5200.05
-5133.15
-5066.25
-4999.35
-4932.45
-4865.55
-4798.65
-4731.75
-4664.85
-4597.95
-4531.05
-4464.15
-4397.25
-4330.35
-4263.45
-4196.55
-4129.65
-4062.75
-3995.85
-3928.95
-3862.05
-3795.15
-3728.25
-3661.35
-3594.45
-3527.55
-3460.65
-3393.75
-3326.85
-3259.95
-3193.05
-3126.15
-3059.25
-2992.35
-2925.45
-2858.55
-2791.65
-2724.75
-2657.85
-2590.95
-2524.05
-2457.15
-2390.25
-2323.35
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SSD1858
Rev 1.1
09/2002
Pad
Name
D/C#
VDD
MID0
VSS
MID1
VDD
MID2
VSS
TEST_IN0
VDD
MODE
VSS
TEST_IN1
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
TEST8
TEST9
TEST10
TEST11
TEST12
TEST13
VL2
VL3
VL4
VL5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
X-pos
Y-pos
Pad #
Pad
Name
X-pos
Y-pos
-2256.45
-2189.55
-2122.65
-2055.75
-1988.85
-1921.95
-1855.05
-1788.15
-1721.25
-1654.35
-1587.45
-1520.55
-1453.65
-1386.75
-1319.85
-1252.95
-1186.05
-1119.15
-1052.25
-985.35
-918.45
-851.55
-784.65
-717.75
-650.85
-576.30
-509.40
-442.50
-375.60
-308.70
-234.15
-167.25
-100.35
-33.45
33.45
100.35
167.25
234.15
301.05
367.95
434.85
501.75
568.65
635.55
702.45
769.35
836.25
903.15
970.05
1036.95
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
RVSS
RVSS
CVSS
CVSS
CVSS
CVSS
CVSS
CVSS
CVSS
CVSS
CVSS
CVSS
CVSS
CVSS
CVSS
CVSS
CVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
1103.85
1170.75
1237.65
1304.55
1371.45
1438.35
1505.25
1572.15
1639.05
1705.95
1772.85
1839.75
1906.65
1973.55
2040.45
2107.35
2174.25
2241.15
2308.05
2374.95
2441.85
2508.75
2575.65
2642.55
2709.45
2776.35
2843.25
2910.15
2977.05
3043.95
3110.85
3177.75
3244.65
3311.55
3378.45
3445.35
3512.25
3586.80
3653.70
3720.60
3787.50
3854.40
3921.30
3988.20
4055.10
4122.00
4188.90
4255.80
4322.70
4389.60
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
SOLOMON
Pad
#
Pad
Name
X-pos
Y-pos
Pad
#
Pad
Name
SIGNAL
MODE=1
SIGNAL
MODE=0
X-pos
Y-pos
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
SYNC
CL
M
CL
TEST14
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
4456.50
4523.40
4590.30
4657.20
4724.10
4791.00
4857.90
4932.45
4999.35
5066.25
5133.15
5200.05
5266.95
5333.85
5400.75
5467.65
5534.55
5601.45
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5741.55
5586.15
5519.25
5452.35
5385.45
5318.55
5251.65
5184.75
5117.85
5050.95
4984.05
4917.15
4850.25
4783.35
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-619.05
-615.90
-549.00
-482.10
-415.20
-348.30
-281.40
-214.50
-147.60
-80.70
-13.80
53.10
120.00
186.90
253.80
320.70
387.60
454.50
521.40
588.30
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
COM6
COM5
COM4
COM3
COM2
COM1
COM0
ICONR
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
COL8
COL9
COL10
COL11
COL12
COL13
COL14
COL15
COL16
COL17
COL18
COL19
COL20
COL21
COL22
COL23
COL24
COL25
COL26
COL27
COL28
COL29
COL30
COM6
COM5
COM4
COM3
COM2
COM1
COM0
ICONR
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
N/C
N/C
N/C
N/C
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
COM6
COM5
COM4
COM3
COM2
COM1
COM0
ICONR
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
4716.45
4649.55
4582.65
4515.75
4448.85
4381.95
4315.05
4248.15
4181.25
4114.35
4047.45
3980.55
3913.65
3846.75
3779.85
3712.95
3646.05
3579.15
3512.25
3445.35
3378.45
3311.55
3244.65
3177.75
3110.85
3043.95
2977.05
2910.15
2843.25
2776.35
2709.45
2642.55
2575.65
2508.75
2441.85
2374.95
2308.05
2241.15
2174.25
2107.35
2040.45
1973.55
1906.65
1839.75
1772.85
1705.95
1639.05
1572.15
1505.25
1438.35
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
SSD1858
Rev 1.1
09/2002
6
SOLOMON
Pad
#
Pad
Name
SIGNAL
MODE=1
SIGNAL
MODE=0
X-pos
Y-pos
Pad #
Pad
Name
SIGNAL
MODE=1
SIGNAL
MODE=0
X-pos
Y-pos
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
COL31
COL32
COL33
COL34
COL35
COL36
COL37
COL38
COL39
COL40
COL41
COL42
COL43
COL44
COL45
COL46
COL47
COL48
COL49
COL50
COL51
COL52
COL53
COL54
COL55
COL56
COL57
COL58
COL59
COL60
COL61
COL62
COL63
COL64
COL65
COL66
COL67
COL68
COL69
COL70
COL71
COL72
COL73
COL74
COL75
COL76
COL77
COL78
COL79
COL80
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
1371.45
1304.55
1237.65
1170.75
1103.85
1036.95
970.05
903.15
836.25
769.35
702.45
635.55
568.65
501.75
434.85
367.95
301.05
234.15
167.25
100.35
33.45
-33.45
-100.35
-167.25
-234.15
-301.05
-367.95
-434.85
-501.75
-568.65
-635.55
-702.45
-769.35
-836.25
-903.15
-970.05
-1036.95
-1103.85
-1170.75
-1237.65
-1304.55
-1371.45
-1438.35
-1505.25
-1572.15
-1639.05
-1705.95
-1772.85
-1839.75
-1906.65
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
COL81
COL82
COL83
COL84
COL85
COL86
COL87
COL88
COL89
COL90
COL91
COL92
COL93
COL94
COL95
COL96
COL97
COL98
COL99
COL100
COL101
COL102
COL103
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
N/C
N/C
N/C
N/C
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
-1973.55
-2040.45
-2107.35
-2174.25
-2241.15
-2308.05
-2374.95
-2441.85
-2508.75
-2575.65
-2642.55
-2709.45
-2776.35
-2843.25
-2910.15
-2977.05
-3043.95
-3110.85
-3177.75
-3244.65
-3311.55
-3378.45
-3445.35
-3512.25
-3579.15
-3646.05
-3712.95
-3779.85
-3846.75
-3913.65
-3980.55
-4047.45
-4114.35
-4181.25
-4248.15
-4315.05
-4381.95
-4448.85
-4515.75
-4582.65
-4649.55
-4716.45
-4783.35
-4850.25
-4917.15
-4984.05
-5050.95
-5117.85
-5184.75
-5251.65
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
619.05
7
SSD1858
Rev 1.1
09/2002
SOLOMON
Pad #
Signal
X-pos
Y-pos
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
COM48
COM49
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
ICONL
DUMMY
DUMMY
-5318.55
-5385.45
-5452.35
-5519.25
-5586.15
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
-5741.55
619.05
619.05
619.05
619.05
619.05
588.30
521.40
454.50
387.60
320.70
253.80
186.90
120.00
53.10
-13.80
-80.70
-147.60
-214.50
-281.40
-348.30
-415.20
-482.10
-549.00
-615.90
Pad Pitch
Pad
Space
Y
Pad355
Pad188
Pad Size
X
SSD1858 IC
Pad1
SSD1858
Pad168
Rev 1.1
09/2002
X
66.9
Y
66.9
Unit
um
Remark
Min.
24.9
24.9
um
Min.
Pad #
1 - 168
169 - 187
188 - 355
356 - 374
X
42
60
42
60
Y
60
42
60
42
Unit
um
um
um
um
8
SOLOMON
6
PIN DESCRIPTION
6.1
RES#
This pin is reset signal input. When the pin is low, initialization of the chip is executed.
6.2
PS0
This pin uses together with PS1 to determine the interface protocol between the driver and MCU.
Refer to PS1 pin descriptions for more details.
6.3
PS1
This pin uses together with PS0 to determine the interface protocol between the driver and MCU
according to the following table.
Table 3 - PS0 & PS1 Interface
PS0
PS1
Interface
L
L
3-wire SPI (write only)
L
H
4-wire SPI (write only)
H
L
8080 parallel interface (read and write allowed)
H
H
6800 parallel interface (read and write allowed)
6.4
CS#
This pin is chip select input. The chip is enabled for display data/command transfer only when CS# is
low.
6.5
D/C#
This input pin is to identify display data/command cycle. When the pin is high, the data written to the
driver will be written into display RAM. When the pin is low, the data will be interpreted as command.
6.6
R/W(WR#)
This pin is microprocessor interface signal. When interfacing to an 6800-series microprocessor, the
signal indicates read mode when high and write mode when low. When interfacing to an 8080microprocessor, a data write operation is initiated when R/W(WR#) is low and the chip is selected.
6.7
E(RD#)
This pin is microprocessor interface signal. When interfacing to an 6800-series microprocessor, a data
operation is initiated when E(RD#) is high and the chip is selected. When interfacing to an 8080microprocessor, a data read operation is initiated when E(RD#) is low and the chip is selected.
6.8
D0 -D7
These pins are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus. When
serial mode is selected, D7 is the serial data input SDA and D6 is the serial clock input SCK.
6.9
VDD
Power supply pin.
9
SSD1858
Rev 1.1
09/2002
SOLOMON
6.10 RVSS
Ground reference of Vref.
6.11 CVSS
Ground reference of analog circuitry.
6.12 VSS
Ground reference of logic circuitry.
6.13 VCI
Reference voltage input for internal DC-DC converter. The voltage of generated VCC equals to the
multiple factor (2X, 3X, 4X or 5X) times VCI with respect to VSS.
Note: Voltage at this input pin must be larger than or equal to VDD.
6.14 Vout
This is the most positive voltage supply pin of the chip. It can be supplied externally or generated by
the internal regulator.
6.15 VL5, VL4, VL3 and VL2
LCD driving voltages. They can be supplied externally or generated by the internal bias divider. They
have the following relationship:
Vout > VL5 > VL4 > VL3 > VL2 > VSS
Table 4 - Vout > VL5 > VL4 > VL3 > VL2 > VSS Relationship
1 : a bias
VL5
VL4
(a-1)/a * Vout
(a-2)/a * Vout
VL3
2/a * Vout
VL2
1/a * Vout
a is equals to 9 at POR.
6.16 COM0 – COM63
These pins provide the row driving signal COM0 - COM63 to the LCD panel. See figure 5 and figure 6
about the COM signal mapping in different multiplex ratio N.
6.17 ICONS
This pin is the special icons line COM signal output.
6.18 COL0 – COL103
These pins provide the LCD column driving signal. Their voltage level is VSS during sleep mode.
6.19 CL
This pin is the external clock input for the device which is enabled by using an extended command.
Under normal operation, this pin should be left opened and internal oscillator will be used after power
on reset.
SSD1858
Rev 1.1
09/2002
10
SOLOMON
6.20 M
This pin is used for cascade purpose only. Under normal operation, it should be left open.
6.21 MID0~MID2
These pins are used for setting the ID code of LCD panel manufacturer. These pins should be
connected to VSS or VDD when NOT IN USE.
6.22 SYNC
This pin is used for cascade purpose only. Under normal operation, it should be left open.
6.23 MODE
This pin is used for setting the display size.
Table 5 – Mode setting
MODE
Remarks:
H
SSD1858 96x65 display mode
L
SSD1858 104x65 display mode
6.24 TEST_IN0~1
These pins is used for internal only and should be connected to Vss.
6.25 TEST0~14
These pins is used for internal only and should be left open, any connection is not allowed.
6.26 N/C
These No Connection pins should NOT be connected to any signal pins nor shorted together. They
should be left open.
6.27 Dummy
There are the floating dummy pads without any internal circuitry connection.
11
SSD1858
Rev 1.1
09/2002
SOLOMON
7
FUNCTIONAL BLOCK DESCRIPTIONS
7.1
Command Decoder and Command Interface
This module determines whether the input data is interpreted as data or command. Data is
directed to this module based upon the input of the D/C# pin. If D/C# is high, data is written to
Graphic Display Data RAM (GDDRAM). If D/C# is low, the input at D0 -D7 is interpreted as a
command and it will be decoded and written to the corresponding command register.
Reset is of the same function as Power ON Reset (POR). Once RES# receives a negative reset
pulse of about 1us, all internal circuitry will be back to its initial status. Refer to Command
Description section for more information.
7.2
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D0 - D7), R/W(WR#), D/C#, E(RD#)
and CS#. R/W(WR#) input High indicates a read operation from the Graphic Display Data RAM
(GDDRAM) or the status register. R/W(WR#) input Low indicates a write operation to Display
Data RAM or Internal Command Registers depending on the status of RS input. The E(RD#)
and CS# input serves as data latch signal (clock) when they are high and low respectively.
Refer to Figure 14 of parallel timing characteristics for Parallel Interface Timing Diagram of
6800-series microprocessors.
In order to match the operating frequency of display RAM with that of the microprocessor, some
pipeline processing is internally performed which requires the insertion of a dummy read before
the first actual display data read. This is shown in Figure 3 below.
R/W(WR)
E(RD)
data bus
N
writ e column address
n
dummy read
data read1
n+1
n+2
data read 2
data read 3
Figure 3 – Display Data Read with the insertion of Dummy Read
7.3
MPU Parallel 8080-series Interface
The parallel interface consists of 8 bi-directional data pins (D0 - D7), R/W(WR#), E(RD#), D/C#
and CS#. The CS# input serves as data latch signal (clock) when it is low. Whether it is display
data or status register read is controlled by D/C#. R/W(WR#) and E(RD#) input indicates a write
or read cycle when CS# is low. Refer to Figure 16 of parallel timing characteristics for Parallel
Interface Timing Diagram of 8080-series microprocessor.
Similar to 6800-series interface, a dummy read is also required before the first actual display
data read.
SSD1858
Rev 1.1
09/2002
12
SOLOMON
7.4
MPU Serial 4-wire Interface
The serial interface consists of serial clock SCK, serial data SDA, D/C# and CS#. SDA is shifted
into an 8-bit shift register on every rising edge of SCL in the order of D7, D6, ... D0. D/C# is
sampled on every eighth clock and the data byte in the shift register is written to the Display
Data RAM or command register in the same clock. No extra clock or command is required to
end the transmission.
7.5
MPU Serial 3-wire interface
Operation is similar to 4-wire serial interface while D/C# is not been used. The Display Data
Length instruction is used to indicate that a specified number display data byte(s) (1-256) are to
be transmitted. Next byte after the display data string is handled as a command.
It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in
the serial communication, a hardware reset pulse at RES# pin is required to initialize the chip
for re-synchronization.
Table 6 -Modes of Operation
6800 Parallel
8080 Parallel
Serial
Data Read
Yes
Yes
No
Data Write
Yes
Yes
Yes
Command Read Status only
Status only
No
Command Write Yes
Yes
Yes
7.6
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of
the RAM is 104 x 65 x 2 = 13,520bits. Figure 5 is a description of the GDDRAM address map.
For mechanical flexibility, re-mapping on both Segment and Common outputs are provided.
For vertical scrolling of display, an internal register storing the display start line can be set to
control the portion of the RAM data mapped to the display. Figure 5 shows the case in which
the display start line register is set at 30H.
For those GDDRAM out of the display common range, they could still be accessed, for either
preparation of vertical scrolling data or even for the system usage.
7.7
Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates
the clock for the DC-DC voltage converter. This clock is also used in the Display Timing
Generator.
Oscillator
enable
enable
enable
Oscillation Circuit
Buffer
(CL)
Internal Resistor
OSC1
OSC2
Figure 4 - Oscillator Circuitry
13
SSD1858
Rev 1.1
09/2002
SOLOMON
7.8
LCD Driving Voltage Generator and Regulator
This module generates the LCD voltage needed for display output. It takes a single supply input
and generates necessary bias voltages.
It consists of:
1. 2X, 3X, 4X and 5X DC-DC voltage converter
2. Bias Divider
If the output op-amp buffer option in Set Power Control Register command is enabled, this circuit
block will divide the regulator output (Vout) to give the LCD driving levels (VL2 - VL5).
The divider does not require external capacitors to reduce the external hardware and pin counts.
3. Contrast Control
Software control of 64 voltage levels of LCD voltage.
4. Bias Ratio Selection circuitry
Software control of 1/4 to 1/9 bias ratio to match the characteristic of LCD panel.
5. Self adjust temperature compensation circuitry
Provide 5 different compensation grade selections to satisfy the various liquid crystal temperature
grades. The grading can be selected by software control. Defaulted temperature coefficient (TC)
value is -0.14%/°C.
7.9
169 Bit Latch
A register carries the display signal information. In 104 X 65 display-mode, data will be fed to
the HV-buffer Cell and level-shifted to the required level.
7.10 Level selector
Level Selector is a control of the display synchronization. Display voltage can be separated into
two sets and used with different cycles. Synchronization is important since it selects the
required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD
waveform.
7.11 HV Buffer Cell (Level Shifter)
HV Buffer Cell works as a level shifter, which translated the low voltage output signal to the
required driving voltage. The output is shifted out with an internal FRM clock, which comes
from the Display Timing Generator. The voltage levels are given by the level selector, which is
synchronized with the internal M signal.
SSD1858
Rev 1.1
09/2002
14
SOLOMON
7.12 Default Setting after Reset
When RES input is low, the chip is initialized to the following:
Register
Default Value
Descriptions
Page address
0
Column address
0
Display ON/OFF
0
Display OFF
Display Start Line
0
GDDRAM page 0,D0
Display Offset
0
COM0 is mapped to ROW0
Mux Ratio
40H
64 Mux
Normal/Reverse Display
0
Normal Display
N-line Inversion
0
No N-line Inversion
Entire Display
0
Entire Display is OFF
DC-DC booster
0
3X booster is selected
Internal Resistor Ratio
0
Gain = 2.84 (IR0)
Contrast
20H
LCD Bias Ratio
5
1/9 Bias Ratio
Scan direction of COM
0
Normal Scan direction
Segment Re-map
0
Segment re-map is disabled
Internal oscillator
0
Internal oscillator is OFF
Power save mode
0
Power save mode is OFF
Data display length
0
FRC, PWM Mode
0
4FRC, 9PWM
White Palette
(0, 0, 0, 0)
Light Gray Palette
(9, 0, 0, 0)
Dark Gray Palette
(9, 9, 9, 0)
Black Palette
(9, 9, 9, 9)
Test mode
0
Test mode is OFF
o
Temperature coefficient
4
PTC4 (-0.14%/ C)
Icon display
0
Icon display line is OFF
8
Frame frequency = 157.5Hz (typical)
Power control
0,0,0
Booster, regulator & divider are both disabled
When RESET command is issued, the following parameters are initialized only:
Register
Default Value
Descriptions
Page address
0
Column address
0
Display Start Line
0
GDDRAM page 0,D0
Internal Resistor Ratio
0
Gain = 2.84 (IR0)
Contrast
20H
Data display length
0
FRC, PWM Mode
0
4FRC, 9PWM
White Palette
(0, 0, 0, 0)
Light Gray Palette
(9, 0, 0, 0)
Dark Gray Palette
(9, 9, 9, 0)
Black Palette
(9, 9, 9, 9)
15
SSD1858
Rev 1.1
09/2002
SOLOMON
7.13 LCD Panel Driving Waveform
The following is an example of how the Common and Segment drivers may be connected to a
LCD panel. The waveforms shown in Figure 7 and Figure 8 illustrate the desired multiplex
scheme with N-line inversion feature is disabled (default).
SSD1858
Rev 1.1
09/2002
16
SOLOMON
(LSB) Second Byte
Internal Column Address
SEG Re-map = 0
SEG Re-map = 1
SEG Outputs
Remapped
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
……………
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
Normal
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
ICONS
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
COM49
COM48
ICONS
CF
0
CE
0
00
67
01
66
02
65
03
64
64
03
65
02
66
01
67
00
SEG103
0
CD
0
SEG102
Page 8
CB
1
CC
1
SEG101
1
C9
1
CA
Page 7
C8
0
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
SEG100
……………
1
……………
……………
1
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
07
……………
1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
06
……………
Page 6
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
SEG3
1
05
0
04
0
SEG2
0
03
Page 1
02
0
Line Address
0 0
0 1
0 2
0 3
0 4
0 5
0 6
0 7
0 8
0 9
0 A
0 B
0 C
0 D
0 E
0 F
SEG1
0
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
01
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
00
0
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
SEG0
Page 0
……………
Page Address
D3 D2 D2 D0
……………
(MSB) First Byte
Figure 5 - SSD1858 Graphic Display Data RAM (GDDRAM) Address Map (with vertical scroll value
30H & MODE=L)
17
SSD1858
Rev 1.1
09/2002
SOLOMON
(LSB) Second Byte
Internal Column Address
SEG Re-map = 0
SEG Re-map = 1
SEG Outputs
Remapped
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
……………
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
Normal
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
ICONS
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
COM49
COM48
ICONS
BF
0
BE
0
00
5F
01
5E
02
5D
03
5C
5C
03
5D
02
5E
01
5F
00
SEG95
0
BD
0
SEG94
Page 8
BB
1
BC
1
SEG93
1
B9
1
BA
Page 7
B8
0
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
SEG92
……………
1
……………
……………
1
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
07
……………
1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
06
……………
Page 6
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
SEG3
1
05
0
04
0
SEG2
0
03
Page 1
02
0
Line Address
0 0
0 1
0 2
0 3
0 4
0 5
0 6
0 7
0 8
0 9
0 A
0 B
0 C
0 D
0 E
0 F
SEG1
0
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
………..
01
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
00
0
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
SEG0
Page 0
……………
Page Address
D3 D2 D2 D0
……………
(MSB) First Byte
Figure 6 - SSD1858 Graphic Display Data RAM (GDDRAM) Address Map (with vertical scroll value
30H & MODE=H)
SSD1858
Rev 1.1
09/2002
18
SOLOMON
SEG 0
SEG 1
SEG 2
SEG 3
SEG 4
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
Figure 7 - LCD Display Example “0”
TIME SLOT
1 2 3 4 5 6 7 8 9
.. .
*
N 1 2 3 4 5 6 7 8 9
. ..
*
N 1 2 3 4 5 6 7 8 9
.. .
*
N 1 2 3 4 5 6 7 8 9
.. .
*
N
V o ut
V L5
V L4
COM0
V L3
V L2
VS S
V o ut
V L5
V L4
COM1
V L3
V L2
VS S
V o ut
V L5
V L4
SEG0
V L3
V L2
VS S
V o ut
V L5
V L4
SEG1
V L3
V L2
VS S
M
* Note : N is the number of multiplex ratio including Icon line if it is enabled, N is equal to 64 on POR .
Figure 8 - LCD Driving Signal from SSD1858
19
SSD1858
Rev 1.1
09/2002
SOLOMON
COMMAND TABLE
Table 7 - COMMAND TABLE
Bit Pattern
0000 C3C2C1C0
Command
Set Column LSB
0001 0C6C5C4
Set Column MSB
0010 0R2R1R0
Set Internal Resistor
Ratio
0010 1VC VR VF
Set Voltage Control
0011 1T2T1T0
Set TC value
0100 00XX
XL6L5L4 L3L2L1L0
Set Initial Display Line
0100 01XX
XXC5C4 C3C2C1C0
Set Initial COM0
SSD1858
Rev 1.1
09/2002
Description
Set the lower nibble of the column address pointer for
RAM access. The pointer is reset to 0 after reset.
Set the upper nibble of the column address pointer for
RAM access. The pointer is reset to 0 after reset.
The internal regulator gain (1+R2/R1) Vout increases as
R2R1R0 is increased from 000b to 111b. The factor,
1+R2/R1, is given by:
R2R1R0 = 000: 2.84 (POR)
R2R1R0 = 001: 3.71
R2R1R0 = 010: 4.57
R2R1R0 = 011: 5.44
R2R1R0 = 100: 6.30
R2R1R0 = 101: 7.16
R2R1R0 = 110: 8.03
R2R1R0 = 111: 8.89
(Refer to 8.14)
VC=0: turn OFF the internal voltage booster (POR)
VC=1: turn ON the internal voltage booster & regulator
VR=0: turn OFF the internal regulator (POR)
VR=1: turn ON the internal regulator & voltage booster
VF=0: turn OFF the output op-amp buffer (POR)
VF=1: turn ON the output op-amp buffer
This command set the Temperature Coefficient
T2T1T0:
o
000: -0.01%/ C
o
001: -0.035%/ C
o
010: -0.05%/ C
o
011: -0.083%/ C
o
100: -0.14%/ C(POR)
The second command specifies the row address pointer
(0-63) of the RAM data to be displayed in COM0. This
command has no effect on ICONS. The pointer is set to
0 after reset.
The second command specifies the mapping of first
display line (COM0) to one of ROW0~63. This
command has no effect on ICONS. COM0 is mapped to
ROW0 after reset.
20
SOLOMON
Bit Pattern
0100 10XX
XD6D5D4 D3D2D1D0
Command
Set Multiplex Ratio
0100 11XX
XXXN4 N3N2N1N0
Set N-line Inversion
0101 0B2B1B0
Set LCD Bias
0110 01B1B0
Set Boost Level
1000 0001
XXC5C4 C3C2C1C0
Set Contrast Level
21
SSD1858
Rev 1.1
09/2002
Description
The second command specifies the number of lines,
excluding ICONS, to be displayed. With Icon is disabled
(POR), 16~64 Mux could be selected. With Icon
enabled, the available Mux are 17~ 65.
Mux(icon disable) Mux(icon enable)
D6 – D0
000000
invalid
invalid
…
0001111
invalid
invalid
0010000
16
17
0010001
17
18
…
1000000
64
65
1000001
invalid
invalid
1000010
invalid
invalid
…
1111111
invalid
invalid
The second command sets the n-line inversion register
from 3 to 33 lines to reduce display crosstalk. Register
values from 00001b to 11111b are mapped to 3 lines to
33 lines respectively. Value 00000b disables the N-line
inversion, which is the POR value.
To avoid a fix polarity at some lines, it should be noted
that the total number of Mux (including the icon line)
should NOT be a multiple of the lines of inversion (n).
n-line inversion
N4 – N0
00000
Exit n-line inversion
00001
3 lines
00010
4 lines
…
11101
31 lines
11110
32 lines
11111
33 lines
Sets the LCD bias from 1/4 ~ 1/9 according to B2B1B0:
000: 1/4 bias
001: 1/5 bias
010: 1/6 bias
011: 1/7 bias
100: 1/8 bias
101: 1/9 bias (POR)
110: 1/9 bias
111: 1/9 bias
Set the DC-DC multiplying factor from 2X to 5X
B1B0:
00: 3X (POR)
01: 4X
10: 5X
11: 2X
The second command sets one of the 64 contrast
levels. The darkness increase as the contrast level
increase.
SOLOMON
1000 1000
WB3WB2WB1WB0 WA3WA2WA1WA0
1000 1001
WD3WD2WD1WD0 WC3WC2WC1WC0
1000 1010
LB3LB2LB1LB0 LA3LA2LA1LA0
1000 1011
LD3LD2LD1LD0 LC3LC2LC1LC0
1000 1100
DB3DB2DB1DB0 DA3DA2DA1DA0
1000 1101
DD3DD2DD1DD0 DC3DC2DC1DC0
1000 1110
BB3BB2BB1BB0 BA3BA2BA1BA0
1000 1111
BD3BD2BD1BD0 BC3BC2BC1BC0
SSD1858
Rev 1.1
09/2002
Set White Mode,
nd
st
Frame 2 & 1
Set White Mode,
th
rd
Frame 4 & 3
Set Light Gray Mode,
nd
st
Frame 2 & 1
Set Light Gray Mode,
th
rd
Frame 4 & 3
Set Dark Gray Mode,
nd
st
Frame 2 & 1
Set Dark Gray Mode,
th
rd
Frame 4 & 3
Set Black Mode,
nd
st
Frame 2 & 1
Set Black Mode,
th
rd
Frame 4 & 3
Set gray scale mode and register. These are two-byte
commands used to specify the contrast levels for the
gray scale, 4 levels available.
After power on reset:
WA0~3 = WB0~3 = WC0~3 = WD0~3 = 0000
LA0~3 = 1001
LB0~3 = LC0~3 = LD0~3 = 0000
DA0~3 = DB0~3 = DC0~3 = 1001
DD0~3 = 0000
BA0~3 = BB0~3 = BC0~3 = BD0~3 = 1001
Memory Content
st
1 Byte
0
0
1
1
2
nd
Byte
0
1
0
1
Gray Mode
White
Light Gray
Dark Gray
Black
22
SOLOMON
Bit Pattern
1001 0 FRC PWM1 PWM0
Command
Set PWM and FRC
1010 000S0
Set Segment Re-map
1010 001C0
1010 010E0
Icon Control Register
ON/OFF
Entire Display Select
1010 011R0
Invert Display Select
1010 1001
Power Save Mode
1010 1011
Start Internal Oscillator
1010 111D0
Display On/Off
1011 P3P2P1P0
Set Page Address
1100 S0XXX
Set COM Scan Direction
1110 0001
1110 0010
Exit Power-save Mode
Reset
1110 0100
Release N-line Inversion
Mode
Display Data Length
1110 1000
D7D6D5D4 D3D2D1D0
23
SSD1858
Rev 1.1
09/2002
Description
Set PWM and FRC for gray-scale operation.
FRC = 0 : 4-frame (POR)
FRC = 1 : 3-frame
PWM = 00 & 01 : 9-levels (POR)
PWM = 10 : 12-levels
PWM = 11 : 15-levels
MODE=0
S0=0: column address 00H is mapped to SEG0 (POR)
S0=1: column address 67H is mapped to SEG0
MODE=1
S0=0: column address 00H is mapped to SEG0 (POR)
S0=1: column address 5FH is mapped to SEG0
C0=0: Disable icon row (Mux = 16 to 64, POR)
C0=1: Enable icon row (Mux = 17 to 65)
E0=0: Normal display (display according to RAM
contents, POR)
E0=1: All pixels are ON regardless of the RAM contents
*Note: This command will override the effect of “Set
Normal/Invert Display”
R0=0: Normal display (display according to RAM
contents, POR)
R0=1: Invert display (ON and OFF pixels are inverted)
*Note: This command will not affect the display of the
icon lines
Sleep Mode:
Oscillator: OFF
LCD Power Supply: OFF
COM/SEG Outputs: VSS
This command starts the internal oscillator. Note that
the oscillator is OFF after reset, so this instruction must
be executed for initialization
Turn the display on and off without modifying the
content of the RAM. (0: off, 1: on)
This command has priority over Entire Display On/Off
and Invert Display On/Off. Commands are accepted
while the display is off, but the visual state of the
display does not change.
Select the page of display RAM to be addressed.
Pages 0-8 are valid.
Set the COM (row) scanning direction.
(0: COM0 →COM63, 1: COM63 →COM0)
Return the driver/controller from the sleep mode.
Reset some functions of the driver/controller. See Reset
Section below for more details.
Release the driver/controller from N-line inversion
mode.
This command is used in 3-line SPI mode (without RS
line) to specify that the controller is about to send
display data to the display RAM. Eight bits are used to
specify the number of bytes to be sent (1 to 256 bytes).
The second command received after the display data is
transmitted is assumed to be command data.
SOLOMON
Bit Pattern
1101 1F2F1F0
Command
Set Frame Frequency
Description
This command is used to set the frame frequency.
F2F1F0
Frame Frequency (typical)
000
70
001
78.5
010
88.5
011
100
100
115
101
130
110
140
111
157.5(POR)
Table 8 – Extended Command Table
Bit Pattern
1000 0010
0001X3X2X1X0
1000 0011
1111 0010
000X0 0000
Other than above
SSD1858
Command
OTP setting
Comment
Set the desired Vout voltage value:
0000: original contrast
0001: original contrast +1 step
0010: original contrast +2 steps
0011: original contrast +3 steps
0100: original contrast +4 steps
0101: original contrast +5 steps
0110: original contrast +6 steps
0111: original contrast +7 steps
1000: original contrast -8 steps
1001: original contrast -7 steps
1010: original contrast -6 steps
1011: original contrast -5 steps
1100: original contrast -4 steps
1101: original contrast -3 steps
1110: original contrast -2 steps
1111: original contrast -1 step
OTP programming
This command start program LCD driver with OTP offset
value. This command only execute once. No effect on the
second run. Detail of OTP programming procedure on
P.31
Enable external oscillator input Select external oscillator input form CL pin.
X0 = 0 : (POR) internal RC oscillator
X0 = 1 : external square wave
Reserved
Rev 1.1
09/2002
24
SOLOMON
7.14 Read Status Byte
An 8 bits status byte will be placed to the data bus if a read operation is performed if D/C# is low. The
status byte is defined as follow.
Table 9 - Read Status Byte
Bit Pattern
Command
BUSY ON RES# MF2 Read Status
MF1 MF0 DS1 DS0
Comment
BUSY=0: Chip is idle
BUSY=1: Chip is executing instruction
ON=0: Display is OFF
ON=1: Display is ON
RES#=0: Chip is idle
RES#=1: Chip is executing reset
MF2-MF0: Manufacturer device ID
DS1,DS0 :
0 0 : 64-row driver
0 1 : 80-row driver
1 0 : 128-row,4 G/S driver
7.15 Data Read / Write
To read data from the GDDRAM, input High to R/W(WR#) pin and D/C# pin for 6800-series parallel
mode. Low to E(RD#) pin and High to RS pin for 8080-series parallel mode. No data read is provided
for serial mode. In normal mode, GDDRAM column address pointer will be increased by one
automatically after each data read. Also, a dummy read is required before the first data is read. See
Figure 3 in Functional Description.
To write data to the GDDRAM, input Low to R/W(WR#) pin and High to D/C# pin for 6800-series
parallel mode. For serial interface, it will always be in write mode. GDDRAM column address pointer
will be increased by one automatically after each data write. The address will be reset to 0 in next data
read/write operation is executed when it is 95.
Remarks: Only read data on Page 0 to Page 7 of the GDDRAM. The data on Icon page (page 8)
cannot be read.
Table 10 - Address Increment Table
RS
0
0
1
1
R/W (WR)
0
1
0
1
Comment
Write Command
Read Status
Write Data
Read Data
Address Increment
No
No
Yes
Yes
Address Increment is done automatically after data read/write. The column address pointer of
GDDRAM is also affected. It will be reset to 0 in next data read/write operation is executed when it is
95.
Table 11 - Commands Required for R/W (WR#) Actions on RAM
R/W (WR) Actions on RAMs
Read/write Data from/to GDDRAM
Commands Required
Set GDDRAM Page Address
Set GDDRAM Column Address
Read/Write Data
(1011X3X2X1X0)*
(0001X3X2X1X0)*
(0000X3X2X1X0)*
(X7X6X5X4X3X2X1X0)
* No need to resend the command again if it is set previously.
The read / write action to the Display Data RAM does not depend on the display mode. This means the
user can change the RAM content whether the target RAM content is being displayed or not.
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8
COMMAND DESCRIPTIONS
8.1
Set Display On/Off
This command turns the display on/off, by the value of the LSB.
8.2
Set Display Start Line
This command is to set Display Start Line register to deter-mine starting address of display
RAM to be displayed by selecting a value from 0 to 63. With value equals to 0, D0 of Page 0 is
mapped to COM0. With value equals to 1, D1 of Page0 is mapped to COM0. The display start
line values of 0 to 63 are assigned to Page 0 to 7.
8.3
Set Page Address
This command positions the page address to 0 to 8 possible positions in GDDRAM. Refer to
Figure 5.
8.4
Set Higher Column Address
This command specifies the higher nibble of the 7-bit column address of the display data RAM.
The column address will be incremented by each data access after it is pre-set by the MCU and
returning to 0 once overflow (>95 when MODE=1 OR >103 when MODE=0).
8.5
Set Lower Column Address
This command specifies the lower nibble of the 7-bit column address of the display data RAM.
The column address will be incremented by each data access after it is pre-set by the MCU and
returning to 0 once overflow (>95 when MODE=1 OR >103 when MODE=0).
8.6
Set Temperature Coefficient (TC) Value
This command is to set 1 out of 5 different temperature coefficients in order to match various
liquid crystal temperature grades (-0.14% / °C – POR).
8.7
Set Segment Re-map
This commands changes the mapping between the display data column address and segment
driver. It allows flexibility in layout during LCD module assembly. Refer to Figure 5.
8.8
Set Normal/Reverse Display
This command sets the display to be either normal/reverse. In normal display, a RAM data of 1
indicates an “ON” pixel while in reverse display; a RAM data of 0 indicates an “ON” pixel. The
icon line is not affected by this command.
8.9
Set Entire Display On/Off
This command forces the entire display, including the icon row, to be “ON” regardless of the
contents of the display data RAM. This command has priority over normal/reverse display.
To execute this command, Set Display On command must be sent in advance.
8.10 Set LCD Bias
This command selects a suitable bias ratio (1/4 to 1/9) required for driving the particular LCD
panel in use. The POR is set to 1/9 bias.
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8.11 Software Reset
This command causes some of the internal status of the chip to be initialized:
Register
Default Value
Descriptions
Page address
0
Column address
0
Display Start Line
0
GDDRAM page 0,D0
Internal Resistor Ratio
0
Gain = 2.84(IR0)
Contrast
20H
Data display length
0
FRC, PWM Mode
0
4FRC, 9PWM
White Palette
(0, 0, 0, 0)
Light Gray Palette
(9, 0, 0, 0)
Dark Gray Palette
(9, 9, 9, 0)
Black Palette
(9, 9, 9, 9)
8.12 Set COM Output Scan Direction
This command sets the scan direction of the COM output allowing layout flexibility in LCD
module assembly.
8.13 Set Power Control Register
This command turns on/off the various power circuits associated with the chip. There are three
power relating sub-circuits could be turned on/off by this command.
Internal voltage booster is used to generate the highest positive voltage supply internally from
the voltage input (VCI -VSS).
Internal regulator is used to generate the LCD driving volt-age. Vout, from the booster output
(internal use only).
Output op-amp buffer is the internal divider for dividing the different voltage levels (VL2, VL3, VL4,
VL5) from the internal regulator output, Vout. External voltage sources should be fed into this
driver if this circuit is turned off.
8.14 Set Internal Regulator Resistors Ratio
This command is to enable any one of the eight internal resistor (IRS) settings for different
regulator gains when using internal regulator resistor network. The Contrast Control Voltage
Range curves is referred to the following formula:
 R 
Vout = 1 + 2  *Vcon
 R1 
 63 − α 
Vcon = 1 −
 * Vref
210 

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, where Vref = 1.7V
SOLOMON
Contrast Cruve
Vout[V]
16
14
IR0
12
IR1
IR2
10
IR3
IR4
8
IR5
IR6
6
IR7
4
2
Contrast[0~63]
0
10
20
30
40
50
60
70
o
Figure 9 - Contrast Control Voltage Range Curve (TC=-0.14%/ C; VDD=2.775V; VCI=3.5V)
8.15 Set Contrast Control Register
This command adjusts the contrast of the LCD panel by changing Vout of the LCD drive voltage
provided by the On-Chip power circuits. Vout is set with 64 steps (6-bit) contrast control register.
It is a compound commands:
Set Contrast Control Register
Contrast Level Data
No
Changes
Complete?
Yes
Figure 10 - Contrast Control Flow
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8.16 Set frame frequency
This command specifies the frame frequency so as to minimize the flickering due to the ac main
frequency. The frequency is set to 157.5Hz (typical) at 64 Mux after POR.
8.17 Set Multiplex Ratio
This command switches default 64 multiplex modes to any multiplex from 16 to 64, if Icon is
disabled (POR). When Icon is set enable, the corresponding multiplex ratio setting will be
mapped to 17 to 65. The chip pads ROW0-ROW63 will be switched to corresponding COM
signal output as specified in Table 2.
8.18 Set Power Save Mode
This command can force the chip to enter Standby or Sleep Mode. LSB of the command will
define which mode will be entered.
8.19 Exit Power Save Mode
This command releases the chip from Sleep Mode and return to normal operation.
8.20 Set N-line Inversion
Number of line inversion is set by this command for reducing crosstalk noise. 3 to 33-line
inversion operations could be selected. At POR, this operation is disabled.
It should be noted that the total number of mux (including the icon line) should NOT be a
multiple of the inversion number (n). Or else, some lines will not change their polarity during
frame change.
8.21 Exit N-line Inversion
This command releases the chip from N-line inversion mode. The driving waveform will be
inverted once per frame after issuing this command.
8.22 Set DC-DC Converter Factor
Internal DC-DC converter factor is set by this command. For SSD1858, 2X to 5X multiplying
factors could be selected. 2X to 5X factors are selected using this command.
8.23 Set Icon Enable
This command enable/disable the Icon display.
8.24 Start Internal Oscillator
After POR, the internal oscillator is OFF. It should be turned ON by sending this command to
the chip.
8.25 Set Display Data Length
This two-bytes command only valid when 3-wire SPI configuration is set by H/W input
(PS0=PS1=L). The second 8-bit is used to indicate that a specified number display data byte(s)
(1-256) are to be transmitted. Next byte after the display data string is handled as a command.
8.26 Set Test Mode
This command forces the driver chip into its test mode for internal testing of the chip. Under
normal operation, user should NOT use this command.
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8.27 Status register Read
This command is issued by setting D/C# Low during a data read (refer to Figure 14 and Figure
16 parallel interface waveform). It allows the MCU to monitor the internal status of the chip. No
status read is provided for serial mode.
8.28 Set Gray Scale Mode (White/Light Gray/Dark Gray/Black)
Command 84(hex) to 8F(hex) are used to specify the four gray levels’ pulse width at the four
possible frames. The four gray levels are called white, light gray, dark gray and black. Each
level is defined by 4 registers for 4 consecutive frames. For example, WA is a 4-bit register to
st
nd
define the pulse width of the 1 frame in White mode. WB is a register for 2 frame in White
mode etc. Each command specifies two registers.
For 4 FRC,
Memory Content
st
nd
1 Byte
2 Byte
0
0
0
1
1
0
1
1
Gray Mode
White
Light Gray
Dark Gray
Black
FRAME
st
2
WB
LB
DB
BB
st
2
WB
LB
DB
BB
1
WA
LA
DA
BA
nd
rd
4
WD
LD
DD
BD
th
rd
4 (No use)
WD (XX)
LD (XX)
DC (XX)
BC (XX)
3
WC
LC
DC
BC
For 3 FRC,
Memory Content
st
nd
1 Byte
2 Byte
0
0
0
1
1
0
1
1
Gray Mode
White
Light Gray
Dark Gray
Black
FRAME
1
WA
LA
DA
BA
nd
3
WC
LC
DC
BC
th
8.29 Set PWM and FRC
This command selects the number of frames in frame rate control, or the number of levels in the
pulse width modulation.
EXTENDED COMMANDS
These commands are used, in addition to basic commands, to trigger the enhanced features, on top of
general ones, designed for the chip.
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8.30 OTP setting and programming
OTP (One Time Programming) is a method to adjust Vout. In order to eliminate the variations of
LCD module in term of contrast level, OTP can be used to achieve the best contrast of every
LCD modules.
OTP setting and programming should include two major steps of (1) Find the OTP offset and
(2) OTP programming as following,
Step 1. Find OTP offset
(1)
(2)
(3)
(4)
(5)
Hardware Reset (sending an active low reset pulse to RES# pin)
Send original initialization routines
Set and display any test patterns
Adjust the contrast value (0x81, 0x00~0x3F) until there is the best visual contrast
OTP setting steps = Contrast value of the best visual contrast - Contrast value of original
initialization
Example 1:
Contrast value of original initialization = 0x20
Contrast value of the best visual contrast = 0x24
OTP setting steps = 0x24 - 0x20 = +4
OTP setting commands should be (0x82, 0x14)
Example 2:
Contrast value of original initialization = 0x20
Contrast value of the best visual contrast = 0x1B
OTP setting steps = 0x1B - 0x20 = -5
OTP setting commands should be (0x82, 0x1B)
Step 2. OTP programming
(6) Hardware Reset (sending an active low reset pulse to RES# pin)
(7) Enable Oscillator (0xAB)
(8) Connect an external Vout (see diagram below)
(9) Send OTP setting commands that we find in step 1 (0x82, 0x10~0x1F)
(10)Send OTP programming command (0x83)
(11)Wait at least 2 seconds
(12)Hardware Reset
Verify the result by repeating step 1. (2) – (3)
(8)
SSD1858
R
Vout
+ C
GND
RES#
16.5-17.5V
(1) & (6) & (12)
GND
Note: R = 1K ~ 10k ohm
C = 1u ~ 4.7u F
Figure 11 - OTP programming circuitry
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SOLOMON
Start
Step 2
Step 1
i) Hardware reset
ii) Send original initialization
routines
iii) Set and display any test
patterns
i) Hardware reset
ii) Enable oscillator
Connect an external
voltage (16.5-17.5V)
on Vout pins
Adjust the
contrast level
to the best
visual level
Accept the
contrast level
on panel?
Yes
OTP setting steps =
Adjusted contrast value
– Original contrast value
No
i) Send OTP setting
commands
ii) Send OTP programming
command
iii) Wait > 2 sec
iv) Hardware reset
i) Send original initialization
routines
ii) Set and display any test
patterns
iii) Inspect the contrast
END
Figure 12 - Flow chart of OTP program
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32
SOLOMON
OTP Example program
Find the OTP offset:
1.
Hardware reset by sending an active low reset pulse to RES# pin
2.
COMMAND(0XAB)
\\Enable oscillator
COMMAND(0X2F)
\\ Turn on the internal voltage booster, internal regulator and
output op-amp buffer; Select booster level
3.
4.
5.
6.
COMMAND(0X48)
\\ Set Duty ratio
COMMAND(0X40)
\\ 64Mux
COMMAND(0X55)
\\ Set Biasing ratio (1/9 BIAS)
COMMAND(0X81)
\\ Set target gain and contrast.
COMMAND(0X2D)
\\ Contrast = 45
COMMAND(0X24)
\\ Gain = 6.3
\\ Set target display contents
COMMAND(0XB0)
\\ Set page address
COMMAND(0x00)
\\ Set lower nibble column address
COMMAND(0X10)
\\ Set higher nibble column address
DATA(…)
\\ Write test patterns to GDDRAM
COMMAND(0XAF)
\\ Set Display On
OTP offset calculation… target OTP offset value is +3
OTP programming:
7.
Hardware reset by sending an active low reset pulse to RES# pin
8.
COMMAND(0XAB)
9.
Connect an external Vout (16.5V-17.5V)
10. COMMAND(0X82)
COMMAND(0X13)
11. COMMAND(0X83)
\\ Enable Oscillator
\\ Set OTP offset value to +3 (0011)
\\ 0001 X3X2X1X0 , where X3X2X1X0 is the OTP offset value
\\ Send the OTP programming command.
12. Wait at least 2 seconds for programming wait time.
13. Hardware reset by sending an active low reset pulse to RES# pin
14. Verify the result:
15. After OTP programming, procedure 2 to 5 are repeated for inspection of the contrast on
the panel
8.31 Enable External Oscillator Input
This command enables the external clock input from CL pin and expected external square wave
is 726kHz.
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9
MAXIMUM RATINGS
Table 12 - Maximum Ratings (Voltage Referenced to VSS)
Symbol
VDD
VCC
VCI
Vin
I
TA
Tstg
Parameter
Supply Voltage
Booster Supply Voltage
Input Voltage
Current Drain Per Pin Excluding VDD and VSS
Operating Temperature
Storage Temperature Range
Value
-0.3 to 5.5
VSS -0.3 to VSS +12.0
VDD to +5.5
VSS -0.3 to VDD +0.3
25
-40 to +85
-65 to +150
Unit
V
V
V
V
mA
°C
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description
section.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric
fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher
than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that
Vin and Vout be constrained to range VSS < or = (Vin or Vout) < or = VDD. Reliability of operation is enhanced
if unused inputs are connected to an appropriate logic voltage level (e.g. either VSS or VDD). Unused
outputs must be open. This device may be light sensitive. Caution should be taken to avoid exposure of
this device any light source during normal operation. This device is not radiation protected.
SSD1858
Rev 1.1
09/2002
34
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10 DC CHARACTERISTICS
Table 13 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 1.8 to
3.3V, TA = -40 to 85°C)
Symbol
VDD
VCI
VREF
Internal Reference Voltage
o
o
(25 C, -0.14%/ C)
IAC
Access Mode Supply Current
Drain (VDD Pins)
IDP1
Display Mode Supply Current
Drain (VDD & VCI Pins)
IDP2
Display Mode Supply Current
Drain (VDD &VCI Pins)
IVCI
Operating Current (VCI Pin)
o
o
(25 C, -0.14%/ C)
ISLEEP
Sleep Mode Supply Current
Drain (VDD Pins)
Vout
LCD Driving Voltage
Generator Output (Vout Pin)
VLCD
VOH1
VOL1
Vout
35
Parameter
Logic Circuit Supply Voltage
Range
Booster Voltage Supply Pin
SSD1858
Test Condition
(Absolute value referenced to
VSS)
(Absolute value referenced to
VSS)
Internal Reference Voltage
Source Enabled (REF pin
pulled High), VEXT pin NC.
VDD = 2.7V, Voltage
Generator On, 5X DC-DC
Converter Enabled, Write
accessing,
Tcyc =3.3MHz,
Frame Freq.=157.5Hz,
Display On.
VDD =VCI = 2.7V, Voltage
Generator ON, internal
Divider Enabled. Read/Write
Halt, Frame Freq. = 157.5Hz,
Display On, Vout = 10.0V.
VDD = VCI = 1.8V, Voltage
Generator OFF, DC-DC
Converter Disabled, Internal
Divider Disable. Read/Write
Halt, Frame Freq. = 157.5Hz,
Display On, Vout = 8.0V, no
panel loading.
VDD=VCI=2.75V, Voltage
Generator On, 4X DC-DC
Converter Enabled, Internal
Divider Enabled. Read/Write
Halt, Frame Freq. = 157.5Hz,
Display On, Vout = 7.5V, no
panel loading, checker board
pattern.
VDD = 2.7V, LCD Driving
Waveform Off, Oscillator Off,
Read/Write halt.
Display On, Voltage
Generator Enabled, DC/DC
Converter Enabled, Regulator
Enabled, Frame
Freq.=157.5Hz,
Min
1.8
Typ
2.7
Max
3.3
Unit
V
VDD
-
3.6
V
-
1.7
-
V
-
0.9
2
mA
-
220
300
µA
-
75
150
µA
220
300
µA
-
1.2
2.5
µA
4.0
-
12.0
V
-
85
-
%
DC-DC Converter Efficiency
80uA panel loading
LCD Driving Voltage Input
(Vout Pin)
Output High Voltage (D0-D7)
Out Low Voltage (D0-D7)
LCD Driving Voltage Source
(Vout Pin)
Voltage Generator Disabled
4.0
-
12.0
V
Iout = +500µA
Iout = -500µA
Regulator Enabled (Vout
voltage depends on Internal
contrast Control)
0.8*VDD
0
VDD
-
VDD
0.2*VDD
12.0
VLCD
V
V
Rev 1.1
09/2002
SOLOMON
Symbol
Vout
VIH1
VIL1
Vout
Parameter
LCD Driving Voltage Source
(Vout Pin)
Input high voltage
(RES#, PS0, PS1, CS#,
D/C#, R/W(WR#), D0-D7)
Input low voltage
(RES#, PS0, PS1, CS#,
D/C#, R/W(WR#), D0-D7)
LCD Display Voltage Output
VL5
VL4
VL3
VL2
(Vout, VL5, VL4, VL3, VL2 Pins)
Vout
LCD Display Voltage Input
(Vout, VL5, VL4, VL3, VL2 Pins)
VL5
VL4
VL3
VL2
IOH
IOL
IOZ
IIL /IIH
CIN
∆Vout
Vref
PTC0
PTC1
PTC2
PTC3
PTC4
Test Condition
Regulator Disable
Bias Divider Enabled, 1:a bias
ratio
Voltage reference to VSS,
External Voltage Generator,
Bias Diver Disabled
Min
-
Typ
Floating
Max
-
Unit
V
0.8*VDD
-
VDD
V
0
-
0.2*VDD
V
-
Vout
-
V
-
(a-1)/a*Vout
(a-2)/a*Vout
2/a* Vout
1/a* Vout
-
V
V
V
V
VL5
-
VL4
VL3
VL2
VSS
50
-
V
-
Vout
VL5
VL4
VL3
-
V
V
V
V
µA
-
-
-50
µA
-1
-
1
µA
-1
-
1
µA
-
5
7.5
PF
-
±2
-
%
Reference Voltage (T= 25ºC)
1.68
1.7
1.72
V
Reference Voltage (T= -20ºC)
Reference Voltage (T= 70ºC)
Temperature Coefficient
Compensation
Flat Temperature Coefficient
Temperature Coefficient 1*
Temperature Coefficient 2*
Temperature Coefficient 3*
Temperature Coefficient 4*
(POR)
1.76
1.54
1.81
1.59
1.86
1.64
V
V
0
-0.025
-0.04
-0.07
-0.126
-0.01
-0.035
-0.05
-0.083
-0.14
-0.02
-0.045
-0.06
-0.096
-0.154
%
%
%
%
%
Output High Current Source
(D0-D7)
Output Low Current Drain
(D0-D7)
Output Tri-state Current
Source
(D0-D7)
Input Current
(RES#, PS0, PS1, CS# ,
E(RD#), D/C#, R/W(WR#),
D0-D7)
Input Capacitance
(all logic pins)
Variation of Vout Output
(1.8V < VDD < 3.3V)
Output Voltage=V DD -0.4V
Output Voltage = 0.4V
Regulator Enabled, Internal
Contrast Control Enabled, Set
Contrast Control Register = 0
Voltage Regulator Enabled
Voltage Regulator Enabled
Voltage Regulator Enabled
Voltage Regulator Enabled
Voltage Regulator Enabled
* The formula for the temperature coefficient is:
TC(%)= Vout 50ºC – Vout at 0ºC
50ºC – 0ºC
SSD1858
Rev 1.1
09/2002
X
1
X100%
Vout at 25ºC
36
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11 AC CHARACTERISTICS
Table 14 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD, VCI = 2.7V,
TA = -40 to 85°C)
Symbol
FFRM
Fosc
Parameter
Frame Frequency
Oscillator frequency
Test Condition
Display ON, Set 104 x 64
Graphic Display Mode, Icon
Line Disabled (POR)
Display ON, Set 104 x 64
Graphic Display Mode, Icon
Line Disabled
Min
Typ
Max
Unit
-
157.5
-
Hz
-
726
-
kHz
Frame Frequency at diff Vdd
180.0
160.0
Frame Frequency[Hz]
140.0
D8
D9
DA
120.0
DB
100.0
DC
DD
80.0
DE
DF
60.0
40.0
1.5
2
2.5
3
3.5
VDD [V]
o
Figure 13 - Frame Frequency at different VDD( Temp = 25 C).
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Table 15 – Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V)
Symbol
tcycle
tAS
tAH
tDSW
tDHW
tDHR
tOH
tACC
PW CSL
PW CSH
tR
tF
Parameter
Clock Cycle Time (write cycle)
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time (RAM)
Access Time (command)
Chip Select Low Pulse Width (read RAM)
Chip Select Low Pulse Width (read Command)
Chip Select Low Pulse Width (write)
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
Rise Time
Fall Time
Min
200
0
0
40
10
10
15
15
500
500
100
200
100
-
Typ
1000
-
Max
25
50
40
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R/ W
D/ C
tAH
tAS
E
t cycle
PW CSL
PW CSH
CS
tR
tF
tDSW
D0 -D7
(Write data to driv er)
tDHW
Valid Data
tACC
D 0-D 7
(Read data f rom driv er)
t DHR
Valid Data
tOH
Figure 14 – Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H)
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38
SOLOMON
Table 16 – Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.7, VSS =0V)
Symbol
tcycle
tAS
tAH
tDSW
tDHW
tDHR
tOH
tACC
PW CSL
PW CSH
tR
tF
Parameter
Clock Cycle Time (write cycle)
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time (RAM)
Access Time (command)
Chip Select Low Pulse Width (read RAM)
Chip Select Low Pulse Width (read Command)
Chip Select Low Pulse Width (write)
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
Rise Time
Fall Time
Min
100
0
0
30
5
10
15
15
250
250
50
100
50
-
Typ
500
-
Max
25
50
40
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R/ W
D/ C
tAH
tAS
E
t cycle
PW CSL
PW CSH
CS
tR
tF
tDSW
D0 -D7
(Write data to driv er)
tDHW
Valid Data
tACC
D 0-D 7
(Read data f rom driv er)
t DHR
Valid Data
tOH
Figure 15 - Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H)
39
SSD1858
Rev 1.1
09/2002
SOLOMON
Table 17 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V)
Symbol
tcycle
tAS
tAH
tDSW
tDHW
tDHR
tOH
tACC
PW CSL
PW CSH
tR
tF
Parameter
Clock Cycle Time (write cycle)
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time (RAM)
Access Time (command)
Chip Select Low Pulse Width (read RAM)
Chip Select Low Pulse Width (read Command)
Chip Select Low Pulse Width (write)
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
Rise Time
Fall Time
Min
200
0
0
40
10
10
15
15
500
500
100
200
100
-
Typ
1000
-
Max
25
50
40
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D/C
tAH
tAS
WR (R/W)
RD (E)
tcycl e
PWCSL
PW CSH
CS
tF
tR
tD SW
D0-D7
(Write dat a to driver)
t DH W
Valid Data
tAC C
D0 -D7
(Read data from driver)
t D HR
Valid Data
tOH
Figure 16 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L)
SSD1858
Rev 1.1
09/2002
40
SOLOMON
Table 18 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.7V, VSS =0V)
Symbol
tcycle
tAS
tAH
tDSW
tDHW
tDHR
tOH
tACC
PW CSL
PW CSH
tR
tF
Parameter
Clock Cycle Time (write cycle)
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time (RAM)
Access Time (command)
Chip Select Low Pulse Width (read RAM)
Chip Select Low Pulse Width (read Command)
Chip Select Low Pulse Width (write)
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
Rise Time
Fall Time
Min
100
0
0
30
5
10
15
15
250
250
50
100
50
-
Typ
500
-
Max
25
50
40
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D/C
tAH
tAS
WR (R/W)
RD (E)
tcycl e
PWCSL
PW CSH
CS
tF
tR
tD SW
D0-D7
(Write dat a to driver)
t DH W
Valid Data
tAC C
D0 -D7
(Read data from driver)
t D HR
Valid Data
tOH
Figure 17 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L)
41
SSD1858
Rev 1.1
09/2002
SOLOMON
Table 19 – Serial Timing Characteristics (TA = -40 to 85°C, VDD = 2.7V, VSS =0V)
Symbol
tcycle
tAS
tAH
tCSS
tCSH
tDSW
tOHW
tCLKL
tCLKH
tR
tF
Parameter
Min
58.8
10
5
30
29.4
30
30
29.4
29.4
-
Clock Cycle Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise Time
Fall Time
Typ
-
Max
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D/C
(Required if PS1 = H)
tAH
tAS
CS
tCSS
tCS H
t c ycle
tC LK L
tC L KH
SCK
tF
tR
tDSW
SDA
tDHW
Valid Data
CS
SCK
D7
SDA
D6
D5
D4
D3
D2
D1
D0
Figure 18- Serial Timing Characteristics (PS0 = L)
SSD1858
Rev 1.1
09/2002
42
SOLOMON
Table 20 – Serial Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V)
Symbol
tcycle
tAS
tAH
tCSS
tCSH
tDSW
tOHW
tCLKL
tCLKH
tR
tF
Parameter
Min
111
15
10
60
55.5
60
60
55.5
55.5
-
Clock Cycle Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise Time
Fall Time
Typ
--
Max
--
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D/C
(Required if PS1 = H)
tAH
tAS
CS
tCSS
tCS H
t c ycle
tC LK L
tC L KH
SCK
tF
tR
tDSW
SDA
tDHW
Valid Data
CS
SCK
D7
SDA
D6
D5
D4
D3
D2
D1
D0
Figure 19 - Serial Timing Characteristics (PS0 = L)
43
SSD1858
Rev 1.1
09/2002
SOLOMON
12 APPLICATION EXAMPLES
ICONS
COM0
:
:
COM10
COM11
:
:
COM30
COM31
Remapped COM
SCAN Direction
[Command: C8
COL99………………………………………………………………………COL4
:
:
:
:
COM62
COM63
ICONS
Remapped COM
SCAN Direction
[Command: C8]
:
:
:
:
:
COM30
COM31
SSD1858 IC
64 MUX
(DIE FACE IP)
Remapped COM
SCAN Direction
[Command: C8
:
:
:
:
COM33
COM32
SEG95…………………………………………….………….SEG0
COM32
COM33
:
:
:
:
:
COM63
:
:
:
:
:
COM0
Remapped COM
SCAN Direction
[Command: C8
DISPLAY PANEL SIZE
96 X 64 + 1 ICON LINE
C1 C2
VOUT
VSS
VCI
VDD
SDA
SCL
RES#
CS#
where VDD&VCI=2.775V;
C1~C2 = 0.47uF~4.7uF,
Logic pin connections not specified above:
Pins connected to VDD: E(RD#);R/W(WR#);MODE; D/C; D0~D5
Pins connected to VSS: TEST_IN0;TEST_IN1;PS0;PS1;RVSS;CVSS
Figure 20 - Typical Application (3-wires SPI mode)
SSD1858
Rev 1.1
09/2002
44
SOLOMON
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for
each customer application by customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of
others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the
body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could
create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or
manufacture of the part.
45
SSD1858
Rev 1.1
09/2002
SOLOMON