ETC SSD1906

SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1906
Advanced Information
256K Embedded Display SRAM
LCD Graphic Controller
CMOS
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
http://www.solomon-systech.com
SSD1906
Rev 1.1
P 1/159
Aug 2005
Copyright  2005 Solomon Systech Limited
TABLE OF CONTENTS
1
GENERAL DESCRIPTION...............................................................................................................................2
2
FEATURES..........................................................................................................................................................3
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
INTEGRATED DISPLAY BUFFER .......................................................................................................................3
CPU INTERFACE .............................................................................................................................................3
DISPLAY SUPPORT ..........................................................................................................................................3
DISPLAY MODES.............................................................................................................................................3
DISPLAY FEATURES ........................................................................................................................................3
CLOCK SOURCE ..............................................................................................................................................4
MISCELLANEOUS ............................................................................................................................................4
PACKAGE ........................................................................................................................................................4
3
ORDERING INFORMATION...........................................................................................................................4
4
BLOCK DIAGRAM............................................................................................................................................5
4.1
PIN ARRANGEMENT .................................................................................................................................6
4.1.1
100 pin TQFP ........................................................................................................................................6
4.1.2
100 pin TFBGA......................................................................................................................................8
5
PIN DESCRIPTION..........................................................................................................................................10
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6
FUNCTIONAL BLOCK DESCRIPTIONS ....................................................................................................19
6.1
6.2
6.3
6.4
6.5
6.6
7
HOST INTERFACE ..........................................................................................................................................11
LCD INTERFACE ..........................................................................................................................................12
CLOCK INPUT ...............................................................................................................................................14
MISCELLANEOUS ..........................................................................................................................................14
POWER AND GROUND ...................................................................................................................................14
SUMMARY OF CONFIGURATION OPTIONS .....................................................................................................14
HOST BUS INTERFACE PIN MAPPING ............................................................................................................16
LCD INTERFACE PIN MAPPING ....................................................................................................................17
DATA BUS ORGANIZATION ...........................................................................................................................18
MCU INTERFACE .........................................................................................................................................19
CONTROL REGISTER .....................................................................................................................................19
DISPLAY OUTPUT .........................................................................................................................................19
DISPLAY BUFFER ..........................................................................................................................................19
PWM CLOCK AND CV PULSE CONTROL ......................................................................................................19
CLOCK GENERATOR .....................................................................................................................................19
REGISTERS ......................................................................................................................................................20
7.1
REGISTER MAPPING......................................................................................................................................20
7.2
REGISTER DESCRIPTIONS ..............................................................................................................................20
7.2.1
Read-Only Configuration Registers.....................................................................................................20
7.2.2
Clock Configuration Registers.............................................................................................................21
7.2.3
Look-Up Table Registers .....................................................................................................................22
7.2.4
Panel Configuration Registers.............................................................................................................26
7.2.5
Display Mode Registers .......................................................................................................................37
7.2.6
Main Window Registers .......................................................................................................................40
7.2.7
Floating Window Registers..................................................................................................................42
7.2.8
Miscellaneous Registers ......................................................................................................................47
7.2.9
General IO Pins Registers ...................................................................................................................49
7.2.10 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers ..52
7.2.11 Cursor Mode Registers ........................................................................................................................55
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Aug 2005 P 2/159
Rev 1.1
SSD1906
8
MAXIMUM RATINGS.....................................................................................................................................69
9
DC CHARACTERISTICS................................................................................................................................70
10
AC CHARACTERISTICS............................................................................................................................70
10.1 CLOCK TIMING .............................................................................................................................................71
10.1.1 Input Clocks .........................................................................................................................................71
10.1.2 Internal Clocks.....................................................................................................................................72
10.2 CPU INTERFACE TIMING ..............................................................................................................................73
10.2.1 Generic #1 Interface Timing................................................................................................................73
10.2.2 Generic #2 Interface Timing (e.g. ISA)................................................................................................75
10.2.3 Motorola MC68K #1 Interface Timing (e.g. MC68000)......................................................................77
10.2.4 Motorola DragonBall Interface Timing with DTACK# (e.g. MC68EZ328/MC68VZ328)...................79
10.2.5 Motorola DragonBall Interface Timing without DTACK# (e.g. MC68EZ328/MC68VZ328)..............81
10.2.6 Hitachi SH-3 Interface Timing (e.g. SH7709A) ...................................................................................83
10.2.7 Hitachi SH-4 Interface Timing (e.g. SH7751) .....................................................................................85
10.3 LCD POWER SEQUENCING ...........................................................................................................................87
10.3.1 Passive/TFT Power-On Sequence........................................................................................................87
10.3.2 Passive/TFT Power-Off Sequence .......................................................................................................88
10.3.3 Power Saving Status ............................................................................................................................89
10.4 DISPLAY INTERFACE.....................................................................................................................................90
10.4.1 Generic STN Panel Timing ..................................................................................................................91
10.4.2 Monochrome 4-Bit Panel Timing.........................................................................................................93
10.4.3 Monochrome 8-Bit Panel Timing.........................................................................................................96
10.4.4 Color 4-Bit Panel Timing ....................................................................................................................99
10.4.5 Color 8-Bit Panel Timing (Format stripe) .........................................................................................102
10.4.6 Generic TFT Panel Timing ................................................................................................................105
10.4.7 9/12/18-Bit TFT Panel Timing...........................................................................................................106
10.4.8 160x160 Sharp HR-TFT Panel Timing (e.g. LQ031B1DDxx) ...........................................................110
10.4.9 Generic HR-TFT Panel Timing .........................................................................................................114
11
CLOCKS ......................................................................................................................................................116
11.1 CLOCK DESCRIPTIONS ................................................................................................................................116
11.1.1 BCLK .................................................................................................................................................116
11.1.2 MCLK ................................................................................................................................................117
11.1.3 PCLK .................................................................................................................................................117
11.1.4 PWMCLK...........................................................................................................................................118
11.2 CLOCKS VERSUS FUNCTIONS ......................................................................................................................119
12
POWER SAVING MODE ..........................................................................................................................120
13
FRAME RATE CALCULATION..............................................................................................................120
14
DISPLAY DATA FORMATS.....................................................................................................................121
15
LOOK-UP TABLE ARCHITECTURE.....................................................................................................122
15.1 MONOCHROME MODES ..............................................................................................................................122
15.1.1 1 Bit-per-pixel Monochrome Mode....................................................................................................122
15.1.2 2 Bit-per-pixel Monochrome Mode....................................................................................................122
15.1.3 4 Bit-per-pixel Monochrome Mode....................................................................................................123
15.1.4 8 Bit-per-pixel Monochrome Mode....................................................................................................123
15.1.5 16 Bit-Per-Pixel Monochrome Mode.................................................................................................123
15.2 COLOR MODES ...........................................................................................................................................124
15.2.1 1 Bit-Per-Pixel Color.........................................................................................................................124
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Rev 1.1
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Aug 2005
Solomon Systech
15.2.2
15.2.3
15.2.4
15.2.5
16
2 Bit-Per-Pixel Color.........................................................................................................................125
4 Bit-Per-Pixel Color.........................................................................................................................126
8 Bit-per-pixel Color Mode................................................................................................................127
16 Bit-Per-Pixel Color Mode.............................................................................................................128
BIG-ENDIAN BUS INTERFACE..............................................................................................................128
16.1 BYTE SWAPPING BUS DATA .......................................................................................................................128
16.1.1 16 Bpp Color Depth...........................................................................................................................129
16.1.2 1/2/4/8 Bpp Color Depth....................................................................................................................129
17
VIRTUAL DISPLAY MODE .....................................................................................................................130
18
DISPLAY ROTATE MODE.......................................................................................................................131
18.1 90° DISPLAY ROTATE MODE ......................................................................................................................131
18.1.1 Register Programming.......................................................................................................................131
18.2 180° DISPLAY ROTATE MODE ....................................................................................................................132
18.2.1 Register Programming.......................................................................................................................132
18.3 270° DISPLAY ROTATE MODE ....................................................................................................................133
18.3.1 Register Programming.......................................................................................................................133
19
FLOATING WINDOW MODE .................................................................................................................134
19.1 WITH DISPLAY ROTATE MODE ENABLED...................................................................................................135
19.1.1 Display Rotate Mode 90°...................................................................................................................135
19.1.2 Display Rotate Mode 180°.................................................................................................................135
19.1.3 Display Rotate Mode 270°.................................................................................................................136
20
HARDWARE CURSOR MODE ................................................................................................................137
20.1 WITH DISPLAY ROTATE MODE ENABLED...................................................................................................138
20.1.1 Display Rotate Mode 90° ...................................................................................................................138
20.1.2 Display Rotate Mode 180° .................................................................................................................139
20.1.3 Display Rotate Mode 270° .................................................................................................................139
20.2 PIXEL FORMAT (NORMAL ORIENTATION MODE) .........................................................................................139
20.2.1 4/8/16 Bit-per-pixel............................................................................................................................140
20.3 PIXEL FORMAT (90˚ DISPLAY ROTATE MODE) ...........................................................................................140
20.3.1 4 Bit-per-pixel....................................................................................................................................140
20.3.2 8 Bit-per-pixel....................................................................................................................................142
20.3.3 16 Bit-per-pixel..................................................................................................................................142
20.4 PIXEL FORMAT (180˚ DISPLAY ROTATE MODE) .........................................................................................143
20.4.1 4 Bit-per-pixel....................................................................................................................................143
20.4.2 8 Bit-per-pixel....................................................................................................................................143
20.4.3 16 Bit-per-pixel..................................................................................................................................144
20.5 PIXEL FORMAT (270˚ DISPLAY ROTATE MODE) .........................................................................................144
20.5.1 4 Bit-per-pixel....................................................................................................................................144
20.5.2 8 Bit-per-pixel....................................................................................................................................145
20.5.3 16 Bit-per-pixel..................................................................................................................................145
21
APPLICATION EXAMPLES ....................................................................................................................147
22
APPENDIX...................................................................................................................................................153
22.1
22.2
22.3
PACKAGE MECHANICAL DRAWING FOR 100 PINS TQFP ............................................................................153
PACKAGE MECHANICAL DRAWING FOR 100 PINS TFBGA.........................................................................154
REGISTER TABLE ........................................................................................................................................156
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Aug 2005 P 4/159
Rev 1.1
SSD1906
Figures
Figure 4-1 : Block Diagram ........................................................................................................................... 5
Figure 4-2 : Pinout Diagram – 100 pin TQFP ............................................................................................... 6
Figure 4-3 : Pinout Diagram – 100 pin TFBGA ............................................................................................. 8
Figure 7-1 : GPIO Offset for 320x240 HR-TFT ........................................................................................... 36
Figure 7-2 : Display Data Byte/Word Swap ................................................................................................ 39
Figure 7-3 : PWM Clock/CV Pulse Block Diagram ..................................................................................... 52
Figure 10-1 : Clock Input Requirements ..................................................................................................... 71
Figure 10-2 : Generic #1 Interface Timing .................................................................................................. 73
Figure 10-3 : Generic #2 Interface Timing .................................................................................................. 75
Figure 10-4 : Motorola MC68K #1 Interface Timing.................................................................................... 77
Figure 10-5 : Motorola DragonBall Interface with DTACK# Timing ............................................................ 79
Figure 10-6 : Motorola DragonBall Interface without DTACK# Timing ....................................................... 81
Figure 10-7 : Hitachi SH-3 Interface Timing................................................................................................ 83
Figure 10-8 : Hitachi SH-4 Interface Timing................................................................................................ 85
Figure 10-9 : Passive/TFT Power-On Sequence Timing ............................................................................ 87
Figure 10-10 : Passive/TFT Power-Off Sequence Timing .......................................................................... 88
Figure 10-11 : Power Saving Status Timing ............................................................................................... 89
Figure 10-12 : Panel Timing Parameters ................................................................................................ 90
Figure 10-13 : Generic STN Panel Timing ............................................................................................. 91
Figure 10-14 : Monochrome 4-Bit Panel Timing .................................................................................... 93
Figure 10-15 : Monochrome 4-Bit Panel A.C. Timing ........................................................................... 94
Figure 10-16 : Monochrome 8-Bit Panel Timing .................................................................................... 96
Figure 10-17 : Monochrome 8-Bit Panel A.C. Timing ........................................................................... 97
Figure 10-18 : Color 4-Bit Panel Timing .................................................................................................. 99
Figure 10-19 : Color 4-Bit Panel A.C. Timing ....................................................................................... 100
Figure 10-20 : Color 8-Bit Panel Timing (Format stripe) .................................................................... 102
Figure 10-21 : Color 8-Bit Panel A.C. Timing (Format stripe)............................................................ 103
Figure 10-22 : Generic TFT Panel Timing ............................................................................................ 105
Figure 10-23 : 12-Bit TFT Panel Timing ................................................................................................ 106
Figure 10-24 : TFT A.C. Timing.............................................................................................................. 108
Figure 10-25 : 160x160 Sharp HR-TFT Panel Horizontal Timing ..................................................... 110
Figure 10-26 : 160x160 Sharp HR-TFT Panel Vertical Timing.......................................................... 112
Figure 10-27 : HR-TFT Panel Horizontal Timing ................................................................................. 114
Figure 10-28 : HR-TFT Panel Vertical Timing ...................................................................................... 115
Figure 11-1 : Clock Generator Block Diagram ..................................................................................... 116
Figure 14-1 : 1/2/4/8/16 Bit-Per-Pixel Display Data Memory Organization .............................................. 121
Figure 15-1 : 1 Bit-per-pixel Monochrome Mode Data Output Path ................................................. 122
Figure 15-2 : 2 Bit-per-pixel Monochrome Mode Data Output Path ................................................. 122
Figure 15-3 : 4 Bit-per-pixel Monochrome Mode Data Output Path ................................................. 123
Figure 15-4 : 8 Bit-per-pixel Monochrome Mode Data Output Path ................................................. 123
Figure 15-5 : 1 Bit-Per-Pixel Color Mode Data Output Path .............................................................. 124
Figure 15-6 : 2 Bit-Per-Pixel Color Mode Data Output Path .............................................................. 125
Figure 15-7 : 4 Bit-Per-Pixel Color Mode Data Output Path .............................................................. 126
Figure 15-8 : 8 Bit-per-pixel Color Mode Data Output Path............................................................... 127
Figure 16-1 : Byte-swapping for 16 Bpp ............................................................................................... 128
Figure 16-2 : Byte-swapping for 1/2/4/8 Bpp ....................................................................................... 129
Figure 17-1 : Main Window inside Virtual Image Area.............................................................................. 130
Figure 18-1 : Relationship Between The Screen Image and the Image Refreshed in 90° Display Rotate
Mode. ................................................................................................................................................. 131
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Rev 1.1
P 5/159
Aug 2005
Solomon Systech
Figure 18-2 : Relationship Between The Screen Image and the Image Refreshed in 180° Display Rotate
Mode. ................................................................................................................................................. 132
Figure 18-3 : Relationship Between The Screen Image and the Image Refreshed in 270° Display Rotate
Mode. ................................................................................................................................................. 133
Figure 19-1 : Floating Window with Display Rotate Mode disabled ................................................. 134
Figure 19-2 : Floating Window with Display Rotate Mode 90° enabled ........................................... 135
Figure 19-3 : Floating Window with Display Rotate Mode 180° enabled ........................................ 135
Figure 19-4 : Floating Window with Display Rotate Mode 270° enabled ........................................ 136
Figure 20-1 : Display Precedence in Hardware Cursor ............................................................................ 137
Figure 20-2 : Cursors on the main window ............................................................................................... 138
Figure 20-3 : Cursors with Display Rotate Mode 90° enabled.................................................................. 138
Figure 20-4 : Cursors with Display Rotate Mode 180° enabled................................................................ 139
Figure 20-5 : Cursors with Display Rotate Mode 270° enabled................................................................ 139
Figure 21-1: Typical System Diagram (Generic #1 Bus) .......................................................................... 147
Figure 21-2 : Typical System Diagram (Generic #2 Bus) ......................................................................... 148
Figure 21-3 : Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000) .......................................... 149
Figure 21-4 : Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus) ............. 150
Figure 21-5 : Typical System Diagram (Hitachi SH-3 Bus)....................................................................... 151
Figure 21-6 : Typical System Diagram (Hitachi SH-4 Bus)....................................................................... 152
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Aug 2005 P 6/159
Rev 1.1
SSD1906
Tables
Table 3-1 : Ordering Information ................................................................................................................... 4
Table 4-1 : TQFP Pin Assignment Table ...................................................................................................... 7
Table 4-2 : TFBGA Pin Assignment Table.................................................................................................... 9
Table 5-1 : Host Interface Pin Descriptions ................................................................................................ 11
Table 5-2 : LCD Interface Pin Descriptions............................................................................................ 12
Table 5-3 : Clock Input Pin Descriptions..................................................................................................... 14
Table 5-4 : Miscellaneous Pin Descriptions ................................................................................................ 14
Table 5-5 : Power And Ground Pin Descriptions ........................................................................................ 14
Table 5-6 : Summary of Power-On/Reset Options ..................................................................................... 15
Table 5-7 : Host Bus Interface Pin Mapping ............................................................................................... 16
Table 5-8 : LCD Interface Pin Mapping....................................................................................................... 17
Table 5-9 : Data Bus Organization.............................................................................................................. 18
Table 5-10 : Pin State Summary................................................................................................................. 18
Table 7-1 : MCLK Divide Selection ............................................................................................................. 21
Table 7-2 : PCLK Divide Selection.............................................................................................................. 22
Table 7-3 : PCLK Source Selection ............................................................................................................ 22
Table 7-4 : Panel Data Width Selection ...................................................................................................... 26
Table 7-5 : Active Panel Resolution Selection ............................................................................................ 27
Table 7-6 : LCD Panel Type Selection........................................................................................................ 27
Table 7-7 : Color Invert Mode Options.................................................................................................... 38
Table 7-8 : LCD Bit-per-pixel Selection .................................................................................................. 38
Table 7-9 : Display Rotate Mode Select Options ........................................................................................ 40
Table 7-10 : 32-bit Address X Increments for Various Color Depths.......................................................... 44
Table 7-11 : 32-bit Address Y Increments for Various Color Depths.......................................................... 45
Table 7-12 : 32-bit Address X Increments for Various Color Depths.......................................................... 46
Table 7-13 : 32-bit Address Y Increments for Various Color Depths.......................................................... 47
Table 7-14 : PWM Clock Control................................................................................................................. 52
Table 7-15 : CV Pulse Control .................................................................................................................... 53
Table 7-16 : PWM Clock Divide Select Options.......................................................................................... 53
Table 7-17 : CV Pulse Divide Select Options ............................................................................................. 54
Table 7-18 : LPWMOUT Duty Cycle Select Options................................................................................... 55
Table 7-19 : X Increment Mode for Various Color Depths.......................................................................... 58
Table 7-20 : Y Increment Mode for Various Color Depths.......................................................................... 59
Table 8-1 : Absolute Maximum Ratings ...................................................................................................... 69
Table 8-2 : Recommended Operating Conditions ...................................................................................... 70
Table 9-1 : Electrical Characteristics for IOVDD = 3.3V typical.................................................................... 70
Table 10-1 : Clock Input Requirements for CLKI ........................................................................................ 71
Table 10-2 : Clock Input Requirements for AUXCLK.................................................................................. 72
Table 10-3 : Internal Clock Requirements .................................................................................................. 72
Table 10-4 : Generic #1 Interface Timing ................................................................................................... 74
Table 10-5 : Generic #2 Interface Timing ................................................................................................... 76
Table 10-6 : Motorola MC68K #1 Interface Timing ..................................................................................... 78
Table 10-7 : Motorola DragonBall Interface with DTACK# Timing ............................................................. 80
Table 10-8 : Motorola DragonBall Interface without DTACK# Timing ........................................................ 82
Table 10-9 : Hitachi SH-3 Interface Timing................................................................................................. 84
Table 10-10 : Hitachi SH-4 Interface Timing............................................................................................... 86
Table 10-11 : Passive/TFT Power-On Sequence Timing ........................................................................... 87
Table 10-12 : Passive/TFT Power-Off Sequence Timing ........................................................................... 88
Table 10-13 : Power Saving Status Timing................................................................................................. 89
Table 10-14 : Panel Timing Parameter Definition and Register Summary................................................. 90
Table 10-15 : Monochrome 4-Bit Panel A.C. Timing .................................................................................. 95
Table 10-16 : Monochrome 8-Bit Panel A.C. Timing .................................................................................. 98
Table 10-17 : Color 4-Bit Panel A.C. Timing............................................................................................. 101
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Aug 2005
Solomon Systech
Table 10-18 : Color 8-Bit Panel A.C. Timing (Format stripe) .................................................................... 104
Table 10-19 : TFT A.C. Timing.................................................................................................................. 109
Table 10-20 : 160x160 Sharp HR-TFT Horizontal Timing ........................................................................ 111
Table 10-21 : 160x160 Sharp HR-TFT Panel Vertical Timing .................................................................. 113
Table 10-22 : 320x240 HR-TFT Panel Horizontal Timing......................................................................... 115
Table 10-23 : 320x240 HR-TFT Panel Vertical Timing............................................................................. 115
Table 11-1 : BCLK Clock Selection........................................................................................................... 116
Table 11-2 : MCLK Clock Selection .......................................................................................................... 117
Table 11-3 : PCLK Clock Selection........................................................................................................... 118
Table 11-4 : Relationship between MCLK and PCLK ............................................................................... 118
Table 11-5 : PWMCLK Clock Selection ................................................................................................ 118
Table 11-6 : SSD1906 Internal Clock Requirements ................................................................................ 119
Table 12-1 : Power Saving Mode Function Summary .............................................................................. 120
Table 20-1 : Indexing scheme for Hardware Cursor ................................................................................. 137
Table 22-1 : SSD1906 Register Table (1 of 3).......................................................................................... 156
Table 22-2 : SSD1906 Register Table (2 of 3).......................................................................................... 157
Table 22-3 : SSD1906 Register Table (3 of 3).......................................................................................... 158
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Aug 2005 P 8/159
Rev 1.1
SSD1906
1
GENERAL DESCRIPTION
The SSD1906 is a graphics controller with built-in 256Kbyte SRAM display buffer, supporting color and mono LCD.
The SSD1906 can support a wide range of active and passive panels and interface with various CPUs. The
advanced design, together with integrated memory and timing circuits produces a low cost, low power, single chip
solution for handheld devices or appliances, including Pocket/Palm-size PCs and mobile communication devices.
The SSD1906 supports most of the common resolutions for portable appliances and features hardware display
rotation, covering various form factor requirements. The controller also features Virtual Display, Floating Window
(variable size Overlay Window) and two Cursors to reduce software manipulation. The 32-bit internal data path
provides high bandwidth display memory for fast screen updates and the SSD1906 also provides the advantage of
a single power supply.
The SSD1906 features low-latency CPU access, supporting microprocessors without RDY#/WAIT# handshaking
signals. This impartiality to CPU type or operating system makes the controller an ideal display solution for a wide
variety of applications. The SSD1906 is available in a 100 pin TQFP & TFBGA package.
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Aug 2005
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SSD1906
2
2.1
FEATURES
Integrated Display Buffer
•
2.2
CPU Interface
•
•
•
•
•
2.3
4/8-bit monochrome STN interface.
4/8-bit color STN interface.
9/12/18-bit Active Matrix TFT interface.
Direct support for 18-bit Sharp HR-TFT interface (160x160, 320x240).
Display Modes
•
•
•
•
•
2.5
Directly interfaces to:
Generic #1 bus interface with WAIT# signal
Generic #2 bus interface with WAIT# signal
Intel StrongARM/XScale
Motorola MX1 Dragonball
Motorola MC68K
Motorola DragonBall MC68EZ328/MC68VZ328
Hitachi SH-3
Hitachi SH-4
8-bit processor support with “glue logic”.
“Fixed” and low-latency CPU access times.
Registers are memory-mapped with dedicated M/R# input, which selects between memory
and register address space.
The contiguous 256K byte display buffer is directly accessible through the 18-bit address bus.
Display Support
•
•
•
•
2.4
Embedded 256K byte SRAM display buffer.
1/2/4/8/16 bit-per-pixel (bpp) color depths.
Up to 64 gray shades using Frame Rate Control (FRC) and dithering on monochrome passive
LCD panels.
Up to 256k colors on passive STN panels.
Up to 256k colors on active matrix LCD panels.
Resolution examples :
320x320 at a color depth of 16 bpp
160x160 at a color depth of 16 bpp
160x240 at a color depth of 16 bpp
Display Features
•
•
•
•
•
Solomon Systech
Display Rotation Mode: 90°, 180°, 270° counter-clockwise hardware rotation of display image.
Virtual Display Support: displays image larger than the panel size using panning and scrolling.
Floating Window Mode: displays a variable size window overlaid on the background image.
2 Hardware Cursors (for 4/8/16 bpp): simultaneously displays two cursors overlaid on the
background image.
Double Buffering/Multi-pages: provides smooth animation and instantaneous screen updates.
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SSD1906
2.6
Clock Source
•
•
•
•
2.7
Miscellaneous
•
•
•
•
2.8
Hardware/Software Color Invert
Software Power Saving mode
General Purpose Input / Output pins available
Single Supply Operation : 3.0V – 3.6V
Package
•
•
3
Two clock inputs: CLKI and AUXCLK, but possible to use one clock input only.
Bus clock (BCLK) is derived from the CLKI and can be internally divided by 2, 3, or 4.
Memory clock (MCLK) is derived from the BCLK and can be internally divided by 2, 3, or 4.
Pixel clock (PCLK) can be derived from CLKI, AUXCLK, BCLK, or MCLK and can be internally
divided by 2, 3, 4, or 8.
100-pin TQFP package
100-pin TFBGA package
ORDERING INFORMATION
Table 3-1 : Ordering Information
Solomon Systech
Ordering Part Number
Package Form
SSD1906QT2
SSD1906QT2R3
SSD1906G14
SSD1906G14R3
100 TQFP (Tray)
100 TQFP (Tape and reel)
100 TFBGA (Tray)
100 TFBGA (Tape and reel)
Aug 2005
P 4/159
Rev 1.1
SSD1906
Solomon Systech
Aug 2005
CLKI, AUXCLK
WAIT#
CF[7:0]
D[15:0]
A[17:0]
WE0#, WE1#,
RD/WR#, RD#,
BS#,CS#;
RESET#, M/R#
MCU INTERFACE
MCU
INTERFACE
CLOCK
GENERATOR
READ/WRITE
DECODE
INTERNAL
CLOCKS
GPIO &
LOOK UP TABLE (LUT)
P 5/159
DISPLAY MEMORY
WITH CONTROL
PULSE WIDTH MODULATION CLOCK AND
CONTRAST VOLTAGE PULSE CONTROL
MEMORY R/W
CONTROL
DISPLAY BUFFER (256KB)
FRC/TFT CONTROLS &
DISPLAY DATA FORMAT
CONVERTION
DISPLAY OUTPUT
DISPLAY DATA
PREFETCH UNIT
CONTROL
REGISTERS
CONTROL REGISTER & GPIO
LPWMOUT,
LCVOUT
LDATA[17:0]
LFRAME,
LLINE,
LSHIFT, LDEN,
GPO
GPIO[6:0]
4
BLOCK DIAGRAM
Figure 4-1 : Block Diagram
Rev 1.1
SSD1906
4.1
4.1.1
PIN ARRANGEMENT
100 pin TQFP
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
COREVDD
LFRAME
LLINE
LSHIFT
LDATA0
LDATA1
LDATA2
LDATA3
LDATA4
LDATA5
LDATA6
VSS
IOVDD
LDATA7
LDATA8
LDATA9
LDATA10
LDATA11
LDATA12
LDATA13
LDATA14
LDATA15
LDATA16
LDATA17
VSS
IOVDD
AUXCLK
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
VSS
VSS
IOVDD
LDEN
GPO
LCVOUT
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
LPWMOUT
IOVDD
VSS
D0
D1
D2
D3
D4
D5
D6
D7
D8
IOVDD
SSD1906
VSS
D9
D10
D11
D12
D13
D14
D15
WAIT#
IOVDD
CLKI
VSS
RESET#
RD/WR#
WE1#
WE0#
RD#
BS#
M/R#
CS#
A0
A1
A2
A3
COREVDD
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 4-2 : Pinout Diagram – 100 pin TQFP
Note
The CoreVDD is an internal regulator output pin and 0.1µF capacitor to VSS is required on each CoreVDD pin.
Solomon Systech
Aug 2005
P 6/159
Rev 1.1
SSD1906
Table 4-1 : TQFP Pin Assignment Table
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Solomon Systech
Signal Name
COREVDD
A3
A2
A1
A0
CS#
M/R#
BS#
RD#
WE0#
WE1#
RD/WR#
RESET#
VSS
CLKI
IOVDD
WAIT#
D15
D14
D13
D12
D11
D10
D9
VSS
Pin #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Signal Name
IOVDD
D8
D7
D6
D5
D4
D3
D2
D1
D0
VSS
IOVDD
LPWMOUT
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
LCVOUT
GPO
LDEN
IOVDD
VSS
Pin #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Aug 2005
Signal Name
COREVDD
LFRAME
LLINE
LSHIFT
LDATA0
LDATA1
LDATA2
LDATA3
LDATA4
LDATA5
LDATA6
VSS
IOVDD
LDATA7
LDATA8
LDATA9
LDATA10
LDATA11
LDATA12
LDATA13
LDATA14
LDATA15
LDATA16
LDATA17
VSS
P 7/159
Pin #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Rev 1.1
Signal Name
IOVDD
AUXCLK
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
VSS
SSD1906
4.1.2
100 pin TFBGA
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
BOTTOM VIEW
Figure 4-3 : Pinout Diagram – 100 pin TFBGA
Note
The CoreVDD is an internal regulator output pin and 0.1µF capacitor to VSS is required on each CoreVDD pin.
Solomon Systech
Aug 2005
P 8/159
Rev 1.1
SSD1906
Table 4-2 : TFBGA Pin Assignment Table
Pin #
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
Signal
Name
VSS
LDATA17
LDATA13
LDATA9
LDATA6
LDATA2
LSHIFT
LFRAME
COREVDD
VSS
AUXCLK
LDATA16
LDATA14
LDATA10
VSS
LDATA3
LDATA0
LLINE
IOVDD
LDEN
Solomon Systech
Pin #
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
Signal
Name
IOVDD
CF7
LDATA15
LDATA11
IOVDD
LDATA4
LDATA1
GPO
LCVOUT
GPIO0
CF6
CF5
CF4
LDATA12
LDATA7
LDATA5
GPIO1
GPIO2
GPIO3
GPIO4
Pin #
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
Signal
Name
CF3
CF2
CF1
CF0
LDATA8
GPIO5
GPIO6
LPWMOUT
IOVDD
VSS
A17
A16
A15
A14
A13
WE1#
D0
D1
D2
D3
Aug 2005
Pin #
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
P 9/159
Signal
Name
A12
A11
A10
A9
WE0#
RD#/WR
WAIT#
D4
D5
D6
A8
A7
A6
CS#
RD#
RESET#
IOVDD
D11
D7
D8
Rev 1.1
Pin #
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
Signal
Name
A5
A4
A2
A0
BS#
VSS
D14
D12
D9
IOVDD
VSS
COREVDD
A3
A1
M/R#
CLKI
D15
D13
D10
VSS
SSD1906
5
PIN DESCRIPTION
Key:
I = Input
O =Output
IO = Bi-directional (input/output)
P = Power pin
LIS = LVTTL Schmitt input
LB2 = LVTTL IO buffer (8mA/-8mA at 3.3V)
LB3 = LVTTL IO buffer (12mA/-12mA at 3.3V)
LO3 = LVTTL output buffer (12mA/-12mA at 3.3V)
LT2 = Tri-state output buffer (8mA/-8mA at 3.3V)
LT3 = Tri-state output buffer (12mA/-12mA at 3.3V)
Hi-Z = High impedance
Note : LVTTL is low voltage TTL (see Section 9 “DC CHARACTERISTICS”).
Solomon Systech
Aug 2005
P 10/159
Rev 1.1
SSD1906
5.1
Host Interface
Table 5-1 : Host Interface Pin Descriptions
Pin Name
A0
A[17:1]
Type
I
I
TQFP
Pin #
TFBGA
Pin #
RESET#
State
Description
5
J4
0
This input pin has multiple functions.
•
For Generic #1, this pin is not used and should be
connected to VSS.
•
For Generic #2, this is an input of the system address bit
0 (A0).
•
For MC68K #1, this is an input of the lower data strobe
(LDS#).
•
For DragonBall, this pin is not used and should be
connected to VSS.
•
For SH-3/SH-4, this pin is not used and should be
connected to VSS.
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
2-4, 8699
F1-F5,
G1-G4,
H1-H3,
J1-J3,
K3-K4
0
System address bus bits 17-1.
Hi-Z
D[15:0]
IO
18-24,
27-35
F7-F10,
G8-G10,
H8-H10,
J7-J9,
K7-K9
WE0#
I
10
G5
1
WE1#
I
11
F6
1
CS#
I
6
H4
1
M/R#
I
7
K5
0
Solomon Systech
Input data from the system data bus.
•
For Generic #1, these pins are connected to D[15:0].
•
For Generic #2, these pins are connected to D[15:0].
•
For MC68K #1, these pins are connected to D[15:0].
•
For DragonBall, these pins are connected to D[15:0].
•
For SH-3/SH-4, these pins are connected to D[15:0].
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin has multiple functions.
•
For Generic #1, this is an input of the write enable signal
for the lower data byte (WE0#).
•
For Generic #2, this is an input of the write enable signal
(WE#).
•
For MC68K #1, this pin must be tied to IOVDD.
•
For DragonBall, this is an input of the byte enable signal
for the D[7:0] data byte (LWE#).
•
For SH-3/SH-4, this is input of the write enable signal for
data D[7:0].
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin has multiple functions.
•
For Generic #1, this is an input of the write enable signal
for the upper data byte (WE1#).
•
For Generic #2, this is an input of the byte enable signal
for the high data byte (BHE#).
•
For MC68K #1, this is an input of the upper data strobe
(UDS#).
•
For DragonBall, this is an input of the byte enable signal
for the D[15:8] data byte (UWE#).
•
For SH-3/SH-4, this is input of the write enable signal for
data D[15:8].
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
Chip select input.
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin is used to select the display buffer or internal
registers of the SSD1906. M/R# is set high to access the
display buffer and low to access the registers.
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
Aug 2005
P 11/159
Rev 1.1
SSD1906
Pin Name
Type
TQFP
Pin #
TFBGA
Pin #
RESET#
State
BS#
I
8
J5
1
RD/WR#
I
12
G6
1
RD#
I
9
H5
1
WAIT#
O
17
G7
Hi-Z
RESET#
I
13
H6
0
Description
This input pin has multiple functions.
•
For Generic #1, this pin must be tied to IOVDD.
•
For Generic #2, this pin must be tied to IOVDD .
•
For MC68K #1, this is an input of the address strobe
(AS#).
•
For DragonBall, this pin must be tied to IOVDD .
•
For SH-3/SH-4, this is input of the bus start signal (BS#).
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin has multiple functions.
•
For Generic #1, this is an input of the read command for
the upper data byte (RD1#).
•
For Generic #2, this pin must be tied to IOVDD .
•
For MC68K #1, this is an input of the R/W# signal.
•
For DragonBall, this pin must be tied to IOVDD .
•
For SH-3/SH-4, this is input of the RD/WR# signal. The
SSD1905 needs this signal for early decode of the bus
cycle.
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin has multiple functions.
•
For Generic #1, this is an input of the read command for
the lower data byte (RD0#).
•
For Generic #2, this is an input of the read command
(RD#).
•
For MC68K #1, this pin must be tied to IOVDD.
•
For DragonBall, this is an input of the output enable
(OE#).
•
For SH-3/SH-4, this is input of the read signal (RD#).
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
During a data transfer, this output pin is driven active to force
the system to insert wait states. It is driven inactive to indicate
the completion of a data transfer. WAIT# is released to the
high impedance state after the data transfer is complete. Its
active polarity is configurable. A pull-up or pull-down resistor
should be used to resolve any data contention issues.
See Table 5-6 : Summary of Power-On/Reset Options.
•
For Generic #1, this pin outputs the wait signal (WAIT#).
•
For Generic #2, this pin outputs the wait signal (WAIT#).
•
For MC68K #1, this pin outputs the data transfer
acknowledge signal (DTACK#).
•
For DragonBall, this pin outputs the data transfer
acknowledge signal (DTACK#).
•
For SH-3 mode, this pin outputs the wait request signal
(WAIT#).
•
For SH-4 mode, this pin outputs the device ready signal
(RDY#).
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
Active low input to set all internal registers to the default state
and to force all signals to their inactive states. It is
recommended to place a 0.1µF capacitor to VSS.
Note : When reset state is released (RESET# = “H”),
normal operation can be started after 3 BCLK period.
5.2
LCD Interface
Table 5-2 : LCD Interface Pin Descriptions
Solomon Systech
Aug 2005
P 12/159
Rev 1.1
SSD1906
Pin Name
Type
TQFP
Pin #
LDATA[17:0]
O
55-61,
64-74
TFBGA
Pin #
A2-A6,
B2-B4,
B6-B7,
C3-C4,
C6-C7,
D4-D6,
E5
Cell
RESET#
State
LO3
0
LFRAME
O
52
A8
LO3
0
LLINE
O
53
B8
LO3
0
LSHIFT
O
54
A7
LO3
0
LDEN
O
48
B10
LO3
0
GPIO0
IO
45
C10
LIS/
LT3
0
GPIO1
IO
44
D7
LB3
0
GPIO2
IO
43
D8
LB3
0
GPIO3
IO
42
D9
LB3
0
GPIO4
IO
41
D10
LB3
0
GPIO5
IO
40
E6
LB3
0
GPIO6
IO
39
E7
LB3
0
LPWMOUT
O
38
E8
LB3
0
LCVOUT
O
46
C9
LB3
0
Solomon Systech
Description
Panel Data bits 17-0.
This output pin has multiple functions.
•
Frame Pulse
•
SPS for Sharp HR-TFT
See Table 5-8 : LCD Interface Pin Mapping for summary.
This output pin has multiple functions.
•
Line Pulse
•
LP for Sharp HR-TFT
See Table 5-8 : LCD Interface Pin Mapping for summary.
This output pin has multiple functions.
•
Shift Clock
•
CLK for Sharp HR-TFT
See Table 5-8 : LCD Interface Pin Mapping for summary.
This output pin has multiple functions.
•
Display enable (LDEN) for TFT panels
•
LCD back-plane bias signal (MOD) for all other LCD
panels
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
•
PS for Sharp HR-TFT
•
General purpose IO pin 0 (GPIO0)
•
Hardware Color Invert
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
•
CLS for Sharp HR-TFT
•
General purpose IO pin 1 (GPIO1)
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
•
REV for Sharp HR-TFT
•
General purpose IO pin 2 (GPIO2)
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
•
SPL for Sharp HR-TFT
•
General purpose IO pin 3 (GPIO3)
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
•
General purpose IO pin 4 (GPIO4)
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
•
General purpose IO pin 5 (GPIO5)
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
•
General purpose IO pin 6 (GPIO6)
See Table 5-8 : LCD Interface Pin Mapping for summary.
This output pin has multiple functions.
•
PWM Clock output
•
General purpose output
This output pin has multiple functions.
•
CV Pulse Output
•
General purpose output
Aug 2005
P 13/159
Rev 1.1
SSD1906
5.3
Clock Input
Table 5-3 : Clock Input Pin Descriptions
Pin Name
Type
TQFP
Pin #
TFBGA
Pin #
Cell
RESET#
State
CLKI
I
15
K6
LIS
—
AUXCLK
I
77
B1
LIS
—
5.4
Description
Typically used as input clock source for bus clock and
memory clock
This pin may be used as input clock source for pixel
clock. This input pin must be connected to VSS if not
used.
Miscellaneous
Table 5-4 : Miscellaneous Pin Descriptions
Pin Name
5.5
Type
TQFP
Pin #
TFBGA
Pin #
RESET
# State
Cell
Description
These inputs are used to configure the SSD1906 – see
Table 5-6 : Summary of Power-On/Reset Options.
CF[7:0]
I
78-85
C2, D1D3, E1E4
LIS
—
GPO
O
47
C8
LO3
0
Note: These pins are used for configuration of the
SSD1906 and must be connected directly to IOVDD
or VSS .
General Purpose Output (potentially used for controlling
the LCD power).
Power and Ground
Table 5-5 : Power And Ground Pin Descriptions
Pin Name
IOVDD
COREVDD
VSS
5.6
Type
P
TQFP
Pin #
16, 26,
37, 49,
63, 76
TFBGA
Pin #
B9, C1,
C5, E9,
H7, J10
Cell
RESET
# State
Description
P
—
Power supply pins. It is recommended to place a
0.1µF bypass capacitor close to each of these pins.
P
1, 51
A9, K2
P
—
COREVDD pins are internal voltage regulator output
pins, used by the internal circuitry only. They
cannot be used for driving external circuitry.
Place a 0.1µF bypass capacitor close to each of
these pins.
P
14, 25,
36, 50,
62, 75,
100
A1,
A10,
B5,
E10,
J6, K1,
K10
P
—
Ground pins
Summary of Configuration Options
These pins are used for configuration of the SSD1906 and must be connected directly to IOVDD or VSS. The state of
CF[5:0] is latched on the rising edge of RESET#, or after the software reset function is activated (REG[A2h] bit 0).
Changing state at any other time has no effect.
Solomon Systech
Aug 2005
P 14/159
Rev 1.1
SSD1906
Table 5-6 : Summary of Power-On/Reset Options
SSD1906
Configuration
Input
CF[2:0]
CF3
CF4
CF5
CF[7:6]
Solomon Systech
Power-On/Reset State
1 (Connected to IOVDD)
0 (Connected to VSS)
Select host bus interface as follows:
CF2
CF1
CF0
Host Bus
0
0
0
SH-3/SH-4
0
0
1
MC68K #1
0
1
0
Reserved
0
1
1
Generic#1
1
0
0
Generic#2
1
0
1
Reserved
1
1
0
DragonBall (MC68EZ328/MC68VZ328)
1
1
1
Reserved
Note: The host bus interface is 17-bit only.
Configure GPIO pins as inputs at
Configure GPIO pins as outputs at power-on
power-on
(for use by HR-TFT when selected)
Big Endian bus interface
Little Endian bus interface
WAIT# is active high
WAIT# is active low
CLKI to BCLK divide select:
CF7 CF6
CLKI to BCLK Divide Ratio
0
0
1:1
0
1
2:1
1
0
3:1
1
1
4:1
Aug 2005
P 15/159
Rev 1.1
SSD1906
5.7
Host Bus Interface Pin Mapping
Table 5-7 : Host Bus Interface Pin Mapping
SSD1906 Pin
Name
A0
A[17:1]
D[15:0]
CS#
M/R#
CLKI
BS#
Generic #1
Connected to
VSS
A[17:1]
D[15:0]
BUSCLK
Generic #2
A0
A[17:1]
D[15:0]
External Decode
BUSCLK
Connected to IOVDD
RD/WR#
RD1#
Connected to
IOVDD
RD#
RD0#
RD#
WE0#
WE0#
WE#
Motorola
MC68EZ328/
MC68VZ328
DragonBall
Connected to
LDS#
VSS
A[17:1]
A[17:1]
D[15:0]1
D[15:0]
CSX#
External Decode
CLK
CLKO
Connected to
AS#
IOVDD
Connected to
R/W#
IOVDD
Connected to
OE#
IOVDD
Connected to
LWE#
IOVDD
UDS#
UWE#
Motorola
MC68K #1
WE1#
WE1#
BHE#
WAIT#
WAIT#
WAIT#
DTACK#
RESET#
RESET#
RESET#
RESET#
DTACK#
RESET#
Hitachi
SH-3
Hitachi
SH-4
Connected to
Connected to
VSS
VSS
A[17:1]
D[15:0]
CSn#
A[17:1]
D[15:0]
CSn#
CKIO
CKIO
BS#
BS#
RD/WR#
RD/WR#
RD#
RD#
WE0#
WE0#
WE1#
WE1#
WAIT#/
RDY#
RESET#
RESET#
Note
1
If the target MC68K bus is 32-bit then these signals should be connected to D[31:16].
Solomon Systech
Aug 2005
P 16/159
Rev 1.1
SSD1906
5.8
LCD Interface Pin Mapping
Table 5-8 : LCD Interface Pin Mapping
Pin Name
Monochrome
Passive Panel
4-bit
8-bit
Color Passive Panel
4-bit
Color TFT Panel
8-bit
(format
stripe)
9-bit
12-bit
18-bit
1
HR-TFT
LFRAME
LLINE
LSHIFT
LDEN
LDATA0
LDATA1
LDATA2
LDATA3
LDATA4
LDATA5
LDATA6
LDATA7
LDATA8
LDATA9
LDATA10
LDATA11
LDATA12
LDATA13
LDATA14
LDATA15
LDATA16
LDATA17
GPIO0
GPIO1
GPIO2
GPIO3
Drive 0
Drive 0
Drive 0
Drive 0
D0
D1
D2
D3
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
GPIO0
GPIO1
GPIO2
GPIO3
D0
D1
D2
D3
D4
D5
D6
D7
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
GPIO0
GPIO1
GPIO2
GPIO3
MOD
Drive 0
Drive 0
Drive 0
Drive 0
2
D0(R2)
D1(B1)2
D2(G1)2
D3(R1)2
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
GPIO0
GPIO1
GPIO2
GPIO3
D0(G3)
2
D1(R3)
2
D2(B2)
D3(G2)2
2
D4(R2)
D5(B1)2
D6(G1)2
D7(R1)2
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
GPIO0
GPIO1
GPIO2
GPIO3
R2
R1
R0
G2
G1
G0
B2
B1
B0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
Drive 0
GPIO0
GPIO1
GPIO2
GPIO3
LDEN
R3
R2
R1
G3
G2
G1
B3
B2
B1
R0
Drive 0
Drive 0
G0
Drive 0
Drive 0
B0
Drive 0
Drive 0
GPIO0
GPIO1
GPIO2
GPIO3
R5
R4
R3
G5
G4
G3
B5
B4
B3
R2
R1
R0
G2
G1
G0
B2
B1
B0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPO
LCVOUT
LPWMOUT
LFRAME
LLINE
LSHIFT
2
18-bit Sharp
SPS
LP
CLK
Drive 0
R5
R4
R3
G5
G4
G3
B5
B4
B3
R2
R1
R0
G2
G1
G0
B2
B1
B0
PS
CLS
REV
SPL
GPIO4
(output only)
GPIO5
(output only)
GPIO6
(output only)
GPO (General Purpose Output)
LCVOUT
LPWMOUT
Note
GPIO pins must be configured as outputs (CF3 = 0 during RESET# active) when the HR-TFT panels are
selected.
2
These pin mappings use common signal names for each panel type. However signal names may differ between
panel manufacturers. The values shown in brackets represent the color components as mapped to the
corresponding LDATAxx signals at the first valid edge of LSHIFT. For further LDATAxx to LCD interface
mapping see Section 10.4 “Display Interface”.
1
Solomon Systech
Aug 2005
P 17/159
Rev 1.1
SSD1906
5.9
Data Bus Organization
There are two data bus architectures; little endian and big endian. Little endian means the bytes at lower
addresses have a lower significance. Big endian means the most significant byte has the lowest address.
Table 5-9 : Data Bus Organization
D[15:8]
2N
2N + 1
Big endian
Little endian
D[7:0]
2N + 1
2N
N : Byte Address
Table 5-10 : Pin State Summary
MCU Mode (Endian)
Generic#1 (Big)
Generic#1 (Little)
Generic#2 (Big)
Generic#2 (Little)
MC68K#1 (Big)
MC68K#1 (Little)
Solomon Systech
A0
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
RD/WR#
0
0
1
1
1
1
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
0
0
0
1
1
1
0
0
0
RD#
0
1
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
WE1#
1
1
1
0
0
1
1
1
1
0
0
1
0
1
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
Aug 2005
WE0#
1
1
1
0
1
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
P 18/159
Rev 1.1
Operation
Word read
High byte read 2N
Low byte read 2N+1
Word write
High byte write 2N
Low byte write 2N+1
Word read
High byte read 2N+1
Low byte read 2N
Word write
High byte write 2N+1
Low byte write 2N
Word read
High byte read 2N
Low byte read 2N+1
Word write
High byte write 2N
Low byte write 2N+1
Word read
High byte read 2N+1
Low byte read 2N
Word write
High byte write 2N+1
Low byte write 2N
Word read
High byte read 2N
Low byte read 2N+1
Word write
High byte write 2N
Low byte write 2N+1
Word read
High byte read 2N+1
Low byte read 2N
Word write
High byte write 2N+1
Low byte write 2N
SSD1906
MCU Mode (Endian)
MC68EZ328 /
MC68VZ328 (Big)
MC68EZ328 /
MC68VZ328 (Little)
SH-3/SH-4 (Big)
SH-3/SH-4 (Little)
6
6.1
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RD/WR#
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RD#
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
WE1#
X
0
0
1
X
0
0
1
1
0
0
1
1
0
0
1
WE0#
X
0
1
0
X
0
1
0
1
0
1
0
1
0
1
0
Operation
Word read
Word write
High byte write 2N
Low byte write 2N+1
Word read
Word write
High byte write 2N+1
Low byte write 2N
Word read
Word write
High byte write 2N
Low byte write 2N+1
Word read
Word write
High byte write 2N+1
Low byte write 2N
FUNCTIONAL BLOCK DESCRIPTIONS
MCU Interface
Responds to bus request for various kinds of MCU and translates to internal interface signals.
6.2
Control Register
The control register stores register data to control the LCD panel. The register data’s register value is controlled
through the MCU Interface read/write. The read/write access of LUT is also controlled by the control register. The
detail of this register and register mapping is discussed in Section 7 “Registers”.
6.3
Display Output
Display output serializes the display data from the display buffer and reconstructs this according to the display
panel format. When the display mode is not 16 bpp, display data is converted to color data by the built-in 18 bit
LUT. For details about LUT, please refer to Section 15 “Look-Up Table Architecture”.
6.4
Display Buffer
Display buffer consists of 256KB SRAM, organized as a 32-bit wide internal data path for fast retrieval of display
datal.
6.5
PWM Clock and CV Pulse Control
Provides programmable waveform for Pulse Width Modulation (PWM) and Contrast Voltage (CV) generation.
6.6
Clock Generator
Clock Generator provides internal clocks. For detailed operation of clock generator see Section 11 “Clocks”.
Solomon Systech
Aug 2005
P 19/159
Rev 1.1
SSD1906
7
Registers
This section details how and where to access the SSD1906 registers and also provides detailed information about
the layout and use of each register.
7.1
Register Mapping
The SSD1906 registers are memory-mapped. When the system decodes the input pins, as CS# = 0 and M/R# = 0,
the registers may be accessed. The register space is decoded by A[17:0].
7.2
Register Descriptions
Unless specified otherwise, all register bits are set to 0 during power-on or software reset (REG[A2h] bit 0 = 1). All
bits marked “0” should be programmed as zero. All bits marked “1” should be programmed as one.
Key :
RO : Read Only
WO : Write Only
RW : Read/Write
NA : Not Applicable
X : Don’t Care
7.2.1
Read-Only Configuration Registers
Display Buffer Size Register
Bit
Type
Reset
state
7
Display
Buffer
Size
Bit 7
RO
0
Bits 7-0
6
Display
Buffer
Size
Bit 6
RO
1
5
Display
Buffer
Size
Bit 5
RO
0
REG[01h]
4
Display
Buffer
Size
Bit 4
RO
0
3
Display
Buffer
Size
Bit 3
RO
0
2
Display
Buffer
Size
Bit 2
RO
0
1
Display
Buffer
Size
Bit 1
RO
0
Display Buffer Size Bits [7:0]
This register indicates the size of the SRAM display buffer in 4K byte multiple. The
SSD1906 display buffer is 256K bytes and therefore this register returns a value of 40h
(64).
Value of this register
= display buffer size ÷ 4K bytes
= 256K bytes ÷ 4K bytes
= 40h (64)
Configuration Readback Register
Bit
Type
Reset
state
0
Display
Buffer
Size
Bit 0
RO
0
7
CF7 Status
RO
X
Bits 7-0
Solomon Systech
6
CF6 Status
RO
X
5
CF5 Status
RO
X
REG[02h]
4
CF4 Status
RO
X
3
CF3 Status
RO
X
2
CF2 Status
RO
X
1
CF1 Status
RO
X
0
CF0 Status
RO
X
CF[7:0] Status
These status bits return the status of the configuration pins CF[7:0]. CF[5:0] and are
latched at the rising edge of RESET# or software reset (REG[A2h] bit 0 = 1).
Aug 2005
P 20/159
Rev 1.1
SSD1906
Product / Revision Code Register
Bit
Type
Reset
state
7
Product
Code
Bit 5
RO
0
Bits 7-2
5
Product
Code
Bit 3
RO
1
REG[03h]
4
Product
Code
Bit 2
RO
1
3
Product
Code
Bit 1
RO
1
2
Product
Code
Bit 0
RO
0
1
Revision
Code Bit 1
0
Revision
Code Bit 0
RO
X
RO
X
Product Code Bits [5:0]
These are read-only bits that indicate the product code. The product code of SSD1906
is 011110.
Revision Code Bits [1:0]
These are read-only bits that indicate the revision code.
Bits 1-0
7.2.2
6
Product
Code
Bit 4
RO
1
Clock Configuration Registers
Memory Clock Configuration Register
Bit
Type
Reset
state
7
6
0
0
NA
0
NA
0
Bits 5-4
5
MCLK
Divide
Select Bit 1
RW
0
REG[04h]
4
MCLK
Divide
Select Bit 0
RW
0
3
2
1
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
MCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Memory Clock (MCLK) from the
Bus Clock (BCLK).
Table 7-1 : MCLK Divide Selection
MCLK Divide Select Bits [1:0]
00
01
10
11
BCLK to MCLK Frequency Ratio
1:1
2:1
3:1
4:1
Pixel Clock Configuration Register
Bit
7
0
Type
Reset
state
NA
0
Bits 6-4
Solomon Systech
6
PCLK
Divide
Select Bit 2
RW
0
5
PCLK
Divide
Select Bit 1
RW
0
REG[05h]
4
PCLK
Divide
Select Bit 0
RW
0
3
2
0
0
NA
0
NA
0
1
PCLK
Source
Select Bit 1
RW
0
0
PCLK
Source
Select Bit 0
RW
0
PCLK Divide Select Bits [2:0]
These bits determine the divided used to generate the Pixel Clock (PCLK) from the
Pixel Clock Source.
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P 21/159
Rev 1.1
SSD1906
Table 7-2 : PCLK Divide Selection
PCLK Divide Select Bits [2:0]
000
001
010
011
1XX
x = don’t care
Bits 1-0
PCLK Source to PCLK Frequency Ratio
1:1
2:1
3:1
4:1
8:1
PCLK Source Select Bits [1:0]
These bits determine the source of the Pixel Clock (PCLK).
Table 7-3 : PCLK Source Selection
PCLK Source Select Bits [1:0]
00
01
10
11
7.2.3
PCLK Source
MCLK
BCLK
CLKI
AUXCLK
Look-Up Table Registers
Look-Up Table Blue Write Data Register
Bit
Type
Reset
state
7
LUT Blue
Write Data
Bit 5
WO
0
Bits 7-2
6
LUT Blue
Write Data
Bit 4
WO
0
5
LUT Blue
Write Data
Bit 3
WO
0
4
LUT Blue
Write Data
Bit 2
WO
0
REG[08h]
3
LUT Blue
Write Data
Bit 1
WO
0
2
LUT Blue
Write Data
Bit 0
WO
0
1
0
X
X
WO
0
WO
0
LUT Blue Write Data Bits [5:0]
This register contains the data to be written to the blue component of the Look-Up
Table.
The data is stored in this register, until a write to the LUT Write Address register
(REG[0Bh]) moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is
written.
Solomon Systech
Aug 2005
P 22/159
Rev 1.1
SSD1906
Look-Up Table Green Write Data Register
Bit
Type
Reset
state
7
LUT Green
Write Data
Bit 5
WO
0
Bits 7-2
6
LUT Green
Write Data
Bit 4
WO
0
5
LUT Green
Write Data
Bit 3
WO
0
4
LUT Green
Write Data
Bit 2
WO
0
REG[09h]
3
LUT Green
Write Data
Bit 1
WO
0
2
LUT Green
Write Data
Bit 0
WO
0
1
0
X
X
WO
0
WO
0
LUT Green Write Data Bits [5:0]
This register contains the data to be written to the green component of the Look-Up
Table.
The data is stored in this register, until a write to the LUT Write Address register
(REG[0Bh]) moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is
written.
Look-Up Table Red Write Data Register
Bit
Type
Reset
state
7
LUT Red
Write Data
Bit 5
WO
0
Bits 7-2
6
LUT Red
Write Data
Bit 4
WO
0
5
LUT Red
Write Data
Bit 3
WO
0
4
LUT Red
Write Data
Bit 2
WO
0
REG[0Ah]
3
LUT Red
Write Data
Bit 1
WO
0
2
LUT Red
Write Data
Bit 0
WO
0
1
0
X
X
WO
0
WO
0
LUT Red Write Data Bits [5:0]
This register contains the data to be written to the red component of the Look-Up
Table.
The data is stored in this register, until a write to the LUT Write Address register
(REG[0Bh]) moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is
written.
Solomon Systech
Aug 2005
P 23/159
Rev 1.1
SSD1906
Look-Up Table Write Address Register
Bit
7
LUT Write
Address Bit
7
WO
0
Type
Reset
state
Bits 7-0
6
LUT Write
Address Bit
6
WO
0
5
LUT Write
Address Bit
5
WO
0
REG[0Bh]
4
LUT Write
Address Bit
4
WO
0
3
LUT Write
Address Bit
3
WO
0
2
LUT Write
Address Bit
2
WO
0
1
LUT Write
Address Bit
1
WO
0
0
LUT Write
Address Bit
0
WO
0
LUT Write Address Bits [7:0]
This register is a pointer to the Look-Up Table (LUT), is used to write LUT data stored
in REG[08h], REG[09h], and REG[0Ah]. Note: The data is updated to the LUT only
upon completion of a write to this register. This is a write-only register and returns
00h if read.
Note
The SSD1906 has three 256-entry, 6-bit-wide LUT’s, one each for red, green and blue
(see Section 15 “Look-Up Table Architecture”).
Look-Up Table Blue Read Data Register
Bit
7
LUT Blue
Read Data
Bit 5
RO
0
Type
Reset
state
Bits 7-2
6
LUT Blue
Read Data
Bit 4
RO
0
5
LUT Blue
Read Data
Bit 3
RO
0
4
LUT Blue
Read Data
Bit 2
RO
0
REG[0Ch]
3
LUT Blue
Read Data
Bit 1
RO
0
2
LUT Blue
Read Data
Bit 0
RO
0
1
0
0
0
RO
0
RO
0
LUT Blue Read Data Bits [5:0]
This register contains the data from the blue component of the Look-Up Table. The
LUT entry read is controlled by the LUT Read Address Register (REG[0Fh]).Note: This
register is updated only when the LUT Read Address Register (REG[0Fh]) is
written.
Look-Up Table Green Read Data Register
Bit
Type
Reset
state
7
LUT Green
Read Data
Bit 5
RO
0
Bits 7-2
6
LUT Green
Read Data
Bit 4
RO
0
5
LUT Green
Read Data
Bit 3
RO
0
4
LUT Green
Read Data
Bit 2
RO
0
REG[0Dh]
3
LUT Green
Read Data
Bit 1
RO
0
2
LUT Green
Read Data
Bit 0
RO
0
1
0
0
0
RO
0
RO
0
LUT Green Read Data Bits [5:0]
This register contains the data from the green component of the Look-Up Table. The
LUT entry read is controlled by the LUT Read Address Register (REG[0Fh]).
Note: This register is updated only when the LUT Read Address Register
(REG[0Fh]) is written.
Solomon Systech
Aug 2005
P 24/159
Rev 1.1
SSD1906
Look-Up Table Red Read Data Register
Bit
7
LUT Red
Read Data
Bit 5
RO
0
Type
Reset
state
Bits 7-2
6
LUT Red
Read Data
Bit 4
RO
0
5
LUT Red
Read Data
Bit 3
RO
0
REG[0Eh]
4
LUT Red
Read Data
Bit 2
RO
0
3
LUT Red
Read Data
Bit 1
RO
0
2
LUT Red
Read Data
Bit 0
RO
0
1
0
0
0
RO
0
RO
0
LUT Red Read Data Bits [5:0]
This register contains the data from the red component of the Look-Up Table. The LUT
entry read is controlled by the LUT Read Address Register (REG[0Fh]). Note: This
register is updated only when the LUT Read Address Register (REG[0Fh]) is
written.
Look-Up Table Read Address Register
Bit
Type
Reset
state
7
LUT Read
Address Bit
7
WO
0
Bits 7-0
6
LUT Read
Address Bit
6
WO
0
5
LUT Read
Address Bit
5
WO
0
REG[0Fh]
4
LUT Read
Address Bit
4
WO
0
3
LUT Read
Address Bit
3
WO
0
2
LUT Read
Address Bit
2
WO
0
1
LUT Read
Address Bit
1
WO
0
0
LUT Read
Address Bit
0
WO
0
LUT Read Address Bits [7:0]
This register is a pointer to the Look-Up Table (LUT) which is used to read LUT data
and store it in REG[0Ch], REG[0Dh], REG[0Eh]. The data is read from the LUT only
when a write to this register is completed. This is a write-only register and returns
00h if read.
Note: The SSD1906 has three 256-entry, 6-bit-wide LUT’s, one each for red, green
and blue (see Section 15 “Look-Up Table Architecture”).
Solomon Systech
Aug 2005
P 25/159
Rev 1.1
SSD1906
7.2.4
Panel Configuration Registers
Panel Type Register
REG[10h]
Bit
7
Color STN
Panel
Select
6
Color/Mono
Panel
Select
5
Panel Data
Width Bit 1
4
Panel Data
Width Bit 0
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
Bit 7
3
Active
Panel
Resolution
Select
RW
0
2
Panel Type
Bit 2
1
Panel Type
Bit 1
0
Panel Type
Bit 0
RW
0
RW
0
RW
0
Color STN Panel Select
When this bit = 0, non color STN LCD panel is selected.
When this bit = 1, color STN LCD panel is selected.
Color/Mono Panel Select
When this bit = 0, monochrome LCD panel is selected.
When this bit = 1, color LCD panel is selected.
Panel Data Width Bits [1:0]
These bits are determined by the data width of the LCD panel. Refer to Table 7-4 :
Panel Data Width Selection for the selection.
Bit 6
Bits 5-4
Table 7-4 : Panel Data Width Selection
Panel Data Width Bits [1:0]
00
01
10
11
Bit 3
Passive Panel Data Width
4-bit
8-bit
Reserved
Reserved
Active Panel Data Width
9-bit
12-bit
18-bit
Reserved
Active Panel Resolution Select
This bit determines one of two panel resolutions when HR-TFT is selected, but hasno
effect unless HR-TFT is selected (REG[10h] bits 2:0 = 010).
Note
This bit sets some internal non-configurable timing values for the selected panel.
However, all panel configuration registers (REG[12h] – REG[40h]) still require
programming with the appropriate values for the selected panel.
For panel AC timing, see Section 10.4 “Display Interface”.
Solomon Systech
Aug 2005
P 26/159
Rev 1.1
SSD1906
Table 7-5 : Active Panel Resolution Selection
Active Panel Resolution Select Bit
0
1
Bits 2-0
HR-TFT Resolution
160x160
320x240
Panel Type Bits[2:0]
These bits select the panel type.
Table 7-6 : LCD Panel Type Selection
Panel Type Bits [2:0]
000
001
010
011 , 100, 101, 110, 111
Panel Type
STN
TFT
HR-TFT
Reserved
MOD Rate Register
Bit
7
0
6
0
Type
Reset
state
NA
0
NA
0
Bits 5-0
REG[11h]
5
MOD Rate
Bit 5
RW
0
4
MOD Rate
Bit 4
RW
0
3
MOD Rate
Bit 3
RW
0
2
MOD Rate
Bit 2
RW
0
1
MOD Rate
Bit 1
RW
0
0
MOD Rate
Bit 0
RW
0
MOD Rate Bits [5:0]
When these bits are all 0, the MOD output signal (LDEN) toggles every LFRAME.
For any non-zero value n, the MOD output signal (LDEN) toggles every n LLINE.
These bits are for passive LCD panels only.
Horizontal Total Register
Bit
7
0
Type
Reset
state
NA
0
Bits 6-0
6
Horizontal
Total Bit 6
RW
0
REG[12h]
5
Horizontal
Total Bit 5
RW
0
4
Horizontal
Total Bit 4
RW
0
3
Horizontal
Total Bit 3
RW
0
2
Horizontal
Total Bit 2
RW
0
1
Horizontal
Total Bit 1
RW
0
0
Horizontal
Total Bit 0
RW
0
Horizontal Total Bits [6:0]
These bits specify the LCD panel Horizontal,total period, in 8 pixel resolution. The
Horizontal Total is the sum of the Horizontal Display period plus the Horizontal NonDisplay period. The maximum Horizontal Total is 1024 pixels. See Figures 10-12.
“Panel Timing Parameters”.
Horizontal Total in number of pixels = (Bits [6:0] + 1) x 8.
Note:This register must be programmed so that:
HDPS + HDP < HT
For panel AC timing and timing parameter definitions, see Section 10.4 “Display
Interface”.
Solomon Systech
Aug 2005
P 27/159
Rev 1.1
SSD1906
Horizontal Display Period Register
Bit
7
0
Type
Reset
state
NA
0
Bits 6-0
6
Horizontal
Display
Period Bit 6
RW
0
5
Horizontal
Display
Period Bit 5
RW
0
REG[14h]
4
Horizontal
Display
Period Bit 4
RW
0
3
Horizontal
Display
Period Bit 3
RW
0
2
Horizontal
Display
Period Bit 2
RW
0
1
Horizontal
Display
Period Bit 1
RW
0
0
Horizontal
Display
Period Bit 0
RW
0
Horizontal Display Period Bits [6:0]
These bits specify the LCD panel Horizontal Display period, in 8 pixel resolution. The
Horizontal Display period should be less than the Horizontal Total, to allow for a
sufficient Horizontal Non-Display period.
Horizontal Display Period, in number of pixels = (Bits [6:0] + 1) x 8
Note:Maximum value of REG[14h] ≤ 0x3F when Display Rotate Mode (90°° or 270°°)
is selected.
For panel AC timing and timing parameter definitions, see Section 10.4 “Display
Interface”.
Horizontal Display Period Start Position Register 0
Bit
Type
Reset
state
7
Horizontal
Display
Period Start
Position Bit
7
RW
0
6
Horizontal
Display
Period Start
Position Bit
6
RW
0
5
Horizontal
Display
Period Start
Position Bit
5
RW
0
4
Horizontal
Display
Period Start
Position Bit
4
RW
0
REG[16h]
3
Horizontal
Display
Period Start
Position Bit
3
RW
0
2
Horizontal
Display
Period Start
Position Bit
2
RW
0
1
Horizontal
Display
Period Start
Position Bit
1
RW
0
1
Horizontal
Display
Period Start
Position Bit
9
RW
0
Horizontal Display Period Start Position Register 1
REG[17h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[17h] bits1-0,
REG[16h] bits 7-0
0
Horizontal
Display
Period Start
Position Bit
0
RW
0
0
Horizontal
Display
Period Start
Position Bit
8
RW
0
Horizontal Display Period Start Position Bits [9:0]
These bits specify the Horizontal Display Period Start Position in 1 pixel resolution.
For panel AC timing and timing parameter definitions, see Section 10.4 “Display
Interface”.
Vertical Total Register 0
Bit
Type
Reset
state
7
Vertical
Total Bit 7
RW
0
6
Vertical
Total Bit 6
RW
0
REG[18h]
5
Vertical
Total Bit 5
RW
0
4
Vertical
Total Bit 4
RW
0
3
Vertical
Total Bit 3
RW
0
2
Vertical
Total Bit 2
RW
0
Vertical Total Register 1
Solomon Systech
1
Vertical
Total Bit 1
RW
0
0
Vertical
Total Bit 0
RW
0
REG[19h]
Aug 2005
P 28/159
Rev 1.1
SSD1906
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[19h] bits 1-0,
REG[18h] bits 7-0
1
Vertical
Total Bit 9
RW
0
0
Vertical
Total Bit 8
RW
0
Vertical Total Bits [9:0]
These bits specify the LCD panel Vertical Total period, in 1 line resolution. The Vertical
Total is the sum of the Vertical Display Period and the Vertical Non-Display Period.
The maximum Vertical Total is 1024 lines. See Figures 10-12. “Panel Timing
Parameters”. Vertical Total in number of lines = Bits [9:0]+ 1
Note: This register must be programmed so that
VDPS + VDP < VT
For panel AC timing and timing parameter definitions see Section 10.4 “Display
Interface”.
Vertical Display Period Register 0
Bit
Type
Reset
state
7
Vertical
Display
Period Bit 7
RW
0
6
Vertical
Display
Period Bit 6
RW
0
5
Vertical
Display
Period Bit 5
RW
0
REG[1Ch]
4
Vertical
Display
Period Bit 4
RW
0
3
Vertical
Display
Period Bit 3
RW
0
2
Vertical
Display
Period Bit 2
RW
0
1
Vertical
Display
Period Bit 1
RW
0
1
Vertical
Display
Period Bit 9
RW
0
Vertical Display Period Register 1
REG[1Dh]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[1Dh] bits 1-0,
REG[1Ch] bits 7-0
0
Vertical
Display
Period Bit 0
RW
0
0
Vertical
Display
Period Bit 8
RW
0
Vertical Display Period Bits [9:0]
These bits specify the LCD panel Vertical Display period, in 1 line resolution. The
Vertical Display period should be less than the Vertical Total, allowing sufficient
Vertical Non-Display period.
Vertical Display Period, in number of lines = Bits [9:0] + 1
For panel AC timing and timing parameter definitions see Section 10.4 “Display
Interface”.
Solomon Systech
Aug 2005
P 29/159
Rev 1.1
SSD1906
Vertical Display Period Start Position Register 0
Bit
Type
Reset
state
7
Vertical
Display
Period Start
Position Bit
7
RW
0
6
Vertical
Display
Period Start
Position Bit
6
RW
0
5
Vertical
Display
Period Start
Position Bit
5
RW
0
REG[1Eh]
4
Vertical
Display
Period Start
Position Bit
4
RW
0
3
Vertical
Display
Period Start
Position Bit
3
RW
0
2
Vertical
Display
Period Start
Position Bit
2
RW
0
1
Vertical
Display
Period Start
Position Bit
1
RW
0
1
Vertical
Display
Start
Position
Period Bit 9
RW
0
Vertical Display Period Start Position Register 1
REG[1Fh]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[1Fh] bits 1-0,
REG[1Eh] bits 7-0
0
Vertical
Display
Period Start
Position Bit
0
RW
0
0
Vertical
Display
Start
Position
Period Bit 8
RW
0
Vertical Display Period Start Position Bits [9:0]
These bits specify the Vertical Display Period Start Position in 1 line resolution.
For panel AC timing and timing parameter definitions see Section 10.4 “Display
Interface”.
LLINE Pulse Width Register
Bit
Type
Reset
state
7
LLINE
Pulse
Polarity
RW
0
Bit 7
Bits 6-0
6
LLINE
Pulse Width
Bit 6
RW
0
5
LLINE
Pulse Width
Bit 5
RW
0
REG[20h]
4
LLINE
Pulse Width
Bit 4
RW
0
3
LLINE
Pulse Width
Bit 3
RW
0
2
LLINE
Pulse Width
Bit 2
RW
0
1
LLINE
Pulse Width
Bit 1
RW
0
0
LLINE
Pulse Width
Bit 0
RW
0
LLINE Pulse Polarity
This bit determines the polarity of the horizontal sync signal. The horizontal sync signal
is typically named as LLINE or LP, depending on the panel type.
When this bit = 0, the horizontal sync signal is active low.
When this bit = 1, the horizontal sync signal is active high.
LLINE Pulse Width Bits [6:0]
These bits specify the width of the panel horizontal sync signal, in number of PCLK.
The horizontal sync signal is typically named as LLINE or LP, depending on the panel
type.
LLINE Pulse Width in PCLK = Bits [6:0] + 1
For panel AC timing and timing parameter definitions see Section 10.4 “Display
Interface”.
Solomon Systech
Aug 2005
P 30/159
Rev 1.1
SSD1906
LLINE Pulse Start Position Register 0
Bit
Type
Reset
state
7
LLINE
Pulse Start
Position Bit
7
RW
0
6
LLINE
Pulse Start
Position Bit
6
RW
0
5
LLINE
Pulse Start
Position Bit
5
RW
0
REG[22h]
4
LLINE
Pulse Start
Position Bit
4
RW
0
3
LLINE
Pulse Start
Position Bit
3
RW
0
2
LLINE
Pulse Start
Position Bit
2
RW
0
1
LLINE
Pulse Start
Position Bit
1
RW
0
1
LLINE
Pulse Start
Position Bit
9
RW
0
LLINE Pulse Start Position Register 1
REG[23h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[23h] bits 1-0,
REG[22h] bits 7-0
0
LLINE
Pulse Start
Position Bit
0
RW
0
0
LLINE
Pulse Start
Position Bit
8
RW
0
LLINE Pulse Start Position Bits [9:0]
These bits specify the start position of the horizontal sync signal, in number of PCLK.
LLINE Pulses Start Position in PCLK = Bits [9:0] + 1
For panel AC timing and timing parameter definitions see Section10.4 “Display Interface”.
LFRAME Pulse Width Register
Bit
Type
Reset
state
7
LFRAME
Pulse
Polarity
RW
0
Bit 7
Bits 2-0
REG[24h]
6
0
5
0
4
0
3
0
NA
0
NA
0
NA
0
NA
0
2
LFRAME
Pulse Width
Bit 2
RW
0
1
LFRAME
Pulse Width
Bit 1
RW
0
0
LFRAME
Pulse Width
Bit 0
RW
0
LFRAME Pulse Polarity
This bit selects the polarity of the vertical sync signal. The vertical sync signal is
typically named ;LFRAME or SPS, depending on the panel type.
When this bit = 0, the vertical sync signal is active at low.
When this bit = 1, the vertical sync signal is active at high.
LFRAME Pulse Width Bits [2:0]
These bits specify the width of the panel vertical sync signal, in 1 line resolution. The
vertical sync signal is typically named; LFRAME or SPS, depending on the panel type.
LFRAME Pulse Width in number of pixels = (Bits [2:0] + 1) x Horizontal Total + offset
For panel AC timing and timing parameter definitions see Section 10.4 “Display Interface”.
Solomon Systech
Aug 2005
P 31/159
Rev 1.1
SSD1906
LFRAME Pulse Start Position Register 0
Bit
Type
Reset
state
7
LFRAME
Pulse Start
Position Bit
7
RW
0
6
LFRAME
Pulse Start
Position Bit
6
RW
0
5
LFRAME
Pulse Start
Position Bit
5
RW
0
REG[26h]
4
LFRAME
Pulse Start
Position Bit
4
RW
0
3
LFRAME
Pulse Start
Position Bit
3
RW
0
2
LFRAME
Pulse Start
Position Bit
2
RW
0
1
LFRAME
Pulse Start
Position Bit
1
RW
0
1
LFRAME
Pulse Start
Position Bit
9
RW
0
LFRAME Pulse Start Position register 1
REG[27h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[27h] bits 1-0
REG[26h] bits 7-0
0
LFRAME
Pulse Start
Position Bit
0
RW
0
0
LFRAME
Pulse Start
Position Bit
8
RW
0
LFRAME Pulse Start Position Bits [9:0]
These bits specify the start position of the vertical sync signal, in 1 line resolution.
LFRAME Pulse Start Position in number of pixels = (Bits [9:0]) x Horizontal Total +
offset
For panel AC timing and timing parameter definitions see Section 10.4 “Display Interface”.
LFRAME Pulse Start Offset Register 0
Bit
Type
Reset
state
7
LFRAME
Start Offset
Bit 7
RW
0
6
LFRAME
Start Offset
Bit 6
RW
0
5
LFRAME
Start Offset
Bit 5
RW
0
REG[30h]
4
LFRAME
Start Offset
Bit 4
RW
0
3
LFRAME
Start Offset
Bit 3
RW
0
2
LFRAME
Start Offset
Bit 2
RW
0
1
LFRAME
Start Offset
Bit 1
RW
0
1
LFRAME
Start Offset
Bit 9
RW
0
LFRAME Pulse Start Offset Register 1
REG[31h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[31h] bits 1-0
REG[30h] bits 7-0
0
LFRAME
Start Offset
Bit 0
RW
0
0
LFRAME
Start Offset
Bit 8
RW
0
LFRAME Pulse Start Offset [9:0]
These bits specify the start offset of the vertical sync signal within a line, in 1 pixel
resolution.
For panel AC timing and timing parameter definitions see Section 10.4 “Display Interface”.
Solomon Systech
Aug 2005
P 32/159
Rev 1.1
SSD1906
LFRAME Pulse Stop Offset Register 0
Bit
Type
Reset
state
7
LFRAME
Stop Offset
Bit 7
RW
0
6
LFRAME
Stop Offset
Bit 6
RW
0
5
LFRAME
Stop Offset
Bit 5
RW
0
REG[34h]
4
LFRAME
Stop Offset
Bit 4
RW
0
3
LFRAME
Stop Offset
Bit 3
RW
0
2
LFRAME
Stop Offset
Bit 2
RW
0
1
LFRAME
Stop Offset
Bit 1
RW
0
1
LFRAME
Stop Offset
Bit 9
RW
0
LFRAME Pulse Stop Offset Register 1
REG[35h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[35h] bits 1-0
REG[34h] bits 7-0
0
LFRAME
Stop Offset
Bit 0
RW
0
0
LFRAME
Stop Offset
Bit 8
RW
0
LFRAME Pulse Stop Offset [9:0]
These bits specify the stop offset of the vertical sync signal in a line, in 1 pixel
resolution.
For panel AC timing and timing parameter definitions see Section 10.4 “Display Interface”.
HR-TFT Special Output Register
Bit
7
Reserved
6
GPIO1
Control
Type
Reset
state
RW
0
RW
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Solomon Systech
5
GPIO
Preset
Enable
RW
0
REG[38h]
4
LSHIFT
Polarity
swap
RW
0
3
LSHIFT
Mask
RW
0
2
GPIO0 /
GPIO1
Swap
RW
0
1
PS
Alternate
0
CLS Double
RW
0
RW
0
Reserved bit
This bit should be programmed by 0.
GPIO1 Control
When this bit = 1, GPIO1 should be programmed with the appropriate values;
REG[3Ah] and [3Bh].
When this bit = 0, GPIO1 can toggle once per line.
GPIO Preset Enable
When this bit = 1, GPIO0 should be programmed with the appropriate values
;REG[3Ch], [3Eh] GPIO1 can be controlled by REG[38h] bit 6 and GPIO2 should be
programmed with REG[40h].
When this bit = 0, GPIO0, GPIO1 and GPIO2 signals are preset to defined values.
LSHIFT Polarity Swap
When this bit = 1, LSHIFT signal is falling trigger.
When this bit = 0, LSHIFT signal is rising trigger.
LSHIFT Mask
When this bit = 1, LSHIFT signal is enabled in non display period.
When this bit = 0, LSHIFT signal is masked in non display period.
GPIO0 / GPIO1 Swap
When this bit = 1, GPIO0/GPIO1 signals are swapped.
When this bit = 0, GPIO0/GPIO1 signals are not swapped.
PS Alternate
When this bit = 1, PS signal changes alternatively.
Aug 2005
P 33/159
Rev 1.1
SSD1906
When this bit = 0, PS signal remains the same.
CLS Double
When this bit = 1, number of CLS pulses remain the same.
When this bit = 0, number of CLS pulses doubles.
Bit 0
Note
Bits 6-5 are effective for 320x240 HR-TFT panels only (REG[10h] bits 3-0 = 1010).
Bits 4-2 are effective for HR-TFT panels only (REG[10h] bits 2-0 = 010).
Bits 1-0 are effective for 160x160 HR-TFT panels only (REG[10h] bits 3-0 = 0010).
For panel AC timing and timing parameter definitions see Section 10.4.8 “160x160 Sharp
HR-TFT Panel Timing (e.g. LQ031B1DDxx)” and 10.4.9 “Generic HR-TFT Panel Timing”.
GPIO1 Pulse Start Register
Bit
Type
Reset
state
7
GPIO1
Start Bit 7
RW
0
Bits 7-0
6
GPIO1
Start Bit 6
RW
0
5
GPIO1
Start Bit 5
RW
0
REG[3Ah]
4
GPIO1
Start Bit 4
RW
0
3
GPIO1
Start Bit 3
RW
0
2
GPIO1
Start Bit 2
RW
0
1
GPIO1
Start Bit 1
RW
0
0
GPIO1
Start Bit 0
RW
0
GPIO1 Pulse Start [7:0]
These bits specify the start offset of the GPIO1 signal within a line, in 1 pixel resolution.
See Figure 7-1 : GPIO Offset for 320x240 HR-TFT.
Note
This register must be programmed so that:.
GPIO1 Pulse Stop Value, REG[3Bh] ≥ GPIO1 Pulse Start Value, REG[3Ah]
GPIO1 Pulse Width = (STOP – START + 1) Ts
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bits 3-0 = 1010 and REG[38h] bit 6-5 = 11).
For panel AC timing and timing parameter definitions see Section 10.4.9 “Generic HR-TFT
Panel Timing.
GPIO1 Pulse Stop Register
Bit
Type
Reset
state
7
GPIO1 Stop
Bit 7
RW
0
Bits 7-0
6
GPIO1 Stop
Bit 6
RW
0
5
GPIO1 Stop
Bit 5
RW
0
REG[3Bh]
4
GPIO1 Stop
Bit 4
RW
0
3
GPIO1 Stop
Bit 3
RW
0
2
GPIO1 Stop
Bit 2
RW
0
1
GPIO1 Stop
Bit 1
RW
0
0
GPIO1 Stop
Bit 0
RW
0
GPIO1 Pulse Stop [7:0]
These bits specify the stop offset of the GPIO1 signal within a line, in 1 pixel resolution.
See Figure 7-1 : GPIO Offset for 320x240 HR-TFT.
Note
This register must be programmed such so that:.
GPIO1 Pulse Stop Value, REG[3Bh] ≥ GPIO1 Pulse Start Value, REG[3Ah]
GPIO1 Pulse Width = (STOP – START + 1) Ts
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bits 3-0 = 1010 and REG[38h] bit 6-5 = 11).
Solomon Systech
Aug 2005
P 34/159
Rev 1.1
SSD1906
For panel AC timing and timing parameter definitions see Section 10.4.9 “Generic HR-TFT
Panel Timing.
GPIO0 Pulse Start Register
Bit
Type
Reset
state
7
GPIO0
Start Bit 7
RW
0
Bits 7-0
6
GPIO0
Start Bit 6
RW
0
5
GPIO0
Start Bit 5
RW
0
REG[3Ch]
4
GPIO0
Start Bit 4
RW
0
3
GPIO0
Start Bit 3
RW
0
2
GPIO0
Start Bit 2
RW
0
1
GPIO0
Start Bit 1
RW
0
0
GPIO0
Start Bit 0
RW
0
GPIO0 Pulse Start [7:0]
These bits specify the start offset of the GPIO0 signal within a line, in 1 pixel resolution.
See Figure 7-1 : GPIO Offset for 320x240 HR-TFT.
Note
This register must be programmed so that:.
GPIO0 Pulse Stop Value, REG[3Eh] ≥ GPIO0 Pulse Start Value, REG[3Ch]
GPIO0 Pulse Width = (STOP – START + 1) Ts
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bits 3-0 = 1010 and REG[38h] bit 5 = 1).
For panel AC timing and timing parameter definitions see Section 10.4.9 “Generic HR-TFT
Panel Timing”.
GPIO0 Pulse Stop Register
Bit
Type
Reset
state
7
GPIO0 Stop
Bit 7
RW
0
Bits 7-0
6
GPIO0 Stop
Bit 6
RW
0
5
GPIO0 Stop
Bit 5
RW
0
REG[3Eh]
4
GPIO0 Stop
Bit 4
RW
0
3
GPIO0 Stop
Bit 3
RW
0
2
GPIO0 Stop
Bit 2
RW
0
1
GPIO0 Stop
Bit 1
RW
0
0
GPIO0 Stop
Bit 0
RW
0
GPIO0 Pulse Stop [7:0]
These bits specify the stop offset of the GPIO0 signal within a line, in 1 pixel resolution.
See Figure 7-1 : GPIO Offset for 320x240 HR-TFT.
Note
This register must be programmed so that:.
GPIO0 Pulse Stop Value, REG[3Eh] ≥ GPIO0 Pulse Start Value, REG[3Ch]
GPIO0 Pulse Width = (STOP – START + 1) Ts
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bits 3-0 = 1010 and REG[38h] bit 5 = 1).
For panel AC timing and timing parameter definitions see Section 10.4.9 “Generic HR-TFT
Panel Timing”.
GPIO2 Pulse Delay Register
Bit
Type
Reset
state
7
GPIO2
Delay Bit 7
RW
0
Solomon Systech
6
GPIO2
Delay Bit 6
RW
0
5
GPIO2
Delay Bit 5
RW
0
REG[40h]
4
GPIO2
Delay Bit 4
RW
0
3
GPIO2
Delay Bit 3
RW
0
Aug 2005
2
GPIO2
Delay Bit 2
RW
0
P 35/159
Rev 1.1
1
GPIO2
Delay Bit 1
RW
0
0
GPIO2
Delay Bit 0
RW
0
SSD1906
Bits 7-0
GPIO2 Pulse Delay [7:0]
These bits specify the pulse delay of the GPIO2 signal within a line, in 1 pixel
resolution. See Figure 7-1 : GPIO Offset for 320x240 HR-TFT.
Note
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bits 3-0 = 1010 and REG[38h] bit 5 = 1).
For panel AC timing and timing parameter definitions see Section 10.4.9 “Generic HR-TFT
Panel Timing”.
LLINE
(LP)
START1
GPIO1
(CLS)
STOP1
START0
GPIO0
(PS)
STOP0
DELAY
GPIO2
(REV)
* For REG[22] = 0,
START1 = 0 Ts if REG[3Ah] = 00; STOP1 = n+1 Ts if REG[3Bh] = n
START0 = 0 Ts if REG[3Ch] = 00; STOP0 = n+1 Ts if REG[3Eh] = n
DELAY = 0 Ts if REG[40h] = 00
Figure 7-1 : GPIO Offset for 320x240 HR-TFT
STN Color Depth Control Register
REG[45h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Bit 0
0
STN Color
Depth
Control
RW
0
STN Color Depth control
This bit controls the maximum number of colors available for STN panels.
When this bit = 0, it allows maximum 32k color depth.
When this bit = 1, it allows maximum 256k color depth.
Refer Table 7-8 : LCD Bit-per-pixel Selection for the color depth relationship.
Note
This register is effective for STN panel only (REG[10h] bits 2:0 = 000).
This register can be reset by the RESET signal pin only.
Solomon Systech
Aug 2005
P 36/159
Rev 1.1
SSD1906
Dithering / FRC Control Register
Bit
Type
Reset
state
7
Dynamic
Dithering
Enable
RW
0
Bit 7
REG[50h]
6
0
5
0
4
0
3
Reserved
2
Reserved
1
0
0
0
NA
0
NA
0
NA
0
RW
0
RW
0
NA
0
NA
0
Dynamic Dithering Enable
This bit enables the dynamic dithering, the dithering mask changing after each 16
frames.
When this bit = 0, dynamic dithering is disabled.
When this bit = 1, dynamic dithering is enabled.
Note
This register is effective for both STN panel and dithering enabled (REG[10h] bits 2:0 =
000 and REG[70h] bit 6 = 0).
Reserved bit
These bits should be programmed by 0.
Bits 3-2
7.2.5
Display Mode Registers
Display Mode Register
Bit
7
Display
Blank
6
Dithering
Disable
Type
Reset
state
RW
0
RW
0
Bit 7
Bit 6
REG[70h]
5
Hardware
Color Invert
Enable
RW
0
4
Software
Color Invert
3
0
2
Bit-per-pixel
Select Bit 2
1
Bit-per-pixel
Select Bit 1
0
Bit-per-pixel
Select Bit 0
RW
0
NA
0
RW
0
RW
0
RW
0
Display Blank
When this bit = 0, the LCD display output is enabled.
When this bit = 1, the LCD display output is blank and all LCD data outputs are forced
to zero (i.e., the screen is blank).
Dithering Disable
SSD1906 uses a combination of FRC and 4 pixel square formation dithering to achieve
more colors per pixel.
When this bit = 0, dithering is enabled on the passive LCD panel,allowing maximum 64
intensity levels for each color component (RGB).
When this bit = 1, dithering is disabled on the passive LCD panel, allowing maximum
16 intensity levels for each color component (RGB).
Bit 5
Solomon Systech
Note
This bit does not refer to the number of simultaneously displayed colors, but rather the
maximum available colors (refer Table 7-8 : LCD Bit-per-pixel Selection for the
maximum number of displayed colors).
Hardware Color Invert Enable
This bit allows the Color Invert feature to be controlled using the General Purpose IO
Aug 2005
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Rev 1.1
SSD1906
pin GPIO0. This bit has no effect if REG[70h] bit 7 = 1. This option is not available if
configured for a HR-TFT as GPIO0 is used as an LCD control signal.
When this bit = 0, GPIO0 has no effect on the display color.
When this bit = 1, display color may be inverted via GPIO0.
Note
Display color is inverted after the Look-Up Table.
The SSD1906 requires some configurations before the hardware color invert feature is
enabled.
• CF3 must be set to 1 during RESET# activation
• GPIO Pin Input Enable (REG[A9h] bit 7) must be set to 1
• GPIO0 Pin IO Configuration (REG[A8h] bit 0) must be set to 0
If Hardware Color Invert is not available (i.e. HR-TFT panel is used), the color invert
function can be controlled by software using REG[70h] bit 4. See Table 7-7 : Color
Invert Mode Options summarizes the color invert options available.
Software Color Invert
When this bit = 0, display color is normal.
When this bit = 1, display color is inverted.
See Table 7-7 : Color Invert Mode Options. This bit has no effect if REG[70h] bit 7 = 1
or REG[70h] bit 5 = 1.
Bit 4
Note
Display color is inverted after the Look-Up Table.
Table 7-7 : Color Invert Mode Options
Hardware Color Invert Enable
Software Color Invert
GPIO0
Display Color
0
0
1
1
0
1
X
X
X
X
0
1
Normal
Invert
Normal
Invert
x = don’t care
Bits 2-0
Bit-per-pixel Select Bits [2:0]
These bits select the bpp color depth for the displayed data for both the main window
and the floating window (if active).
Note
1, 2, 4 and 8 bpp modes use the 18-bit LUT, allowing maximum 256K colors. 16 bpp
mode bypasses the LUT, allowing 64K colors.
Table 7-8 : LCD Bit-per-pixel Selection
Bit-per-pixel
Select Bits [2:0]
Color Depth
(bpp)
000
001
010
011
100
101, 110, 111
1 bpp
2 bpp
4 bpp
8 bpp
16 bpp
Reserved
Solomon Systech
Maximum Number of Colors/Shades
Passive Panel
(Dithering On)
TFT Panel
REG[45h]
REG[45h]
bit 0 = 0
bit 0 = 1
32K/32
256K/64
256K/64
32K/32
256K/64
256K/64
32K/32
256K/64
256K/64
32K/32
256K/64
256K/64
32K/32
64K/64
64K/64
n/a
n/a
n/a
Aug 2005
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Rev 1.1
Max. No. Of
Simultaneously
Displayed
Colors/Shades
2/2
4/4
16/16
256/64
64K/64
n/a
SSD1906
Special Effects Register
Bit
Type
Reset
state
REG[71h]
7
6
5
4
3
2
1
0
Display
Data
Word Swap
Display
Data
0
0
0
Byte Swap
Floating
Window
Enable
RW
0
RW
0
NA
0
RW
0
NA
0
NA
0
Display
Rotate
Mode
Select
Bit 1
RW
0
Display
Rotate
Mode
Select
Bit 0
RW
0
Bit 7
Display Data Word Swap
The display pipe fetches 32-bit of data from the display buffer. This bit enables the
lower 16-bit word and the upper 16-bit word to be swapped before sending them to the
LCD display. If the Display Data Byte Swap bit is also enabled then the byte order of
the fetched 32-bit data is reversed.
Bit 6
Display Data Byte Swap
The display pipe fetches 32-bit of data from the display buffer. This bit enables
swapping of byte 0, byte 1, byte 2 and byte 3, before sending them to the LCD. If the
Display Data Word Swap bit is also set then the byte order of the fetched 32-bit data is
reversed.
Note
For further information on byte swapping for Big Endian mode, see Section 16 “Big-Endian
Bus Interface”.
byte 0
32-bit display data
from display buffer
byte 1
Data
Serialization
byte 2
To LUT
byte 3
Byte Swap
Word Swap
Figure 7-2 : Display Data Byte/Word Swap
Bit 4
Solomon Systech
Floating Window Enable
This bit enables the floating window, within the main window, used for the Floating
Window feature. The location of the floating window within the main window is
determined by the Floating Window Position X registers (REG[84h], REG[85h],
REG[8Ch], REG[8Dh]) and Floating Window Position Y registers (REG[88h],
REG[89h], REG[90h], REG[91h]). The floating window has its own Display Start
Address register (REG[7Ch, REG[7Dh], REG[7Eh]) and Memory Address Offset
register (REG[80h], REG[81h]). The floating window shares the same color depth and
display orientation as the main window.
Aug 2005
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Rev 1.1
SSD1906
When this bit = 1, Floating Window is enabled.
When this bit = 0, Floating Window is disabled.
Display Rotate Mode Select Bits [1:0]
These bits select different display orientations:
Bits 1-0
Table 7-9 : Display Rotate Mode Select Options
7.2.6
Display Rotate Mode Select Bits [1:0]
Display Orientation
00
01
10
11
0° (Normal)
90°
180°
270°
Main Window Registers
Main Window Display Start Address Register 0
Bit
Type
Reset
state
REG[74h]
7
6
5
4
3
2
1
0
Main
window
Display
Start
Address
Bit 7
RW
0
Main
window
Main
window
Display
Start
Address
Bit 5
RW
0
Main
window
Display
Start
Address
Bit 4
RW
0
Main
window
Display
Start
Address
Bit 3
RW
0
Main
window
Display
Start
Address
Bit 2
RW
0
Main
window
Display
Start
Address
Bit 1
RW
0
Main
window
Display
Start
Address
Bit 0
RW
0
Display
Start
Address
Bit 6
RW
0
Main Window Display Start Address Register 1
Bit
Type
Reset
state
REG[75h]
7
6
5
4
3
2
1
0
Main
window
Display
Start
Address
Bit 15
RW
0
Main
window
Display
Start
Address
Bit 14
RW
0
Main
window
Display
Start
Address
Bit 13
RW
0
Main
window
Display
Start
Address
Bit 12
RW
0
Main
window
Display
Start
Address
Bit 11
RW
0
Main
window
Display
Start
Address
Bit 10
RW
0
Main
window
Display
Start
Address
Bit 9
RW
0
Main
window
Display
Start
Address
Bit 8
RW
0
Main Window Display Start Address Register 2
Bit
Type
Reset
state
REG[76h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Main
window
Display
Start
Address
Bit 16
RW
0
REG[76h] bit 0,
REG[75h] bits 7-0,
REG[74h] bits 7-0
Solomon Systech
Main Window Display Start Address Bits [16:0]
These bits form the 17-bit address for the starting double-word of the LCD image in the
display buffer for the main window.
Aug 2005
P 40/159
Rev 1.1
SSD1906
Note that this is a double-word (32-bit) address. An entry of 00000h into these
registers represents the first double-word of display memory, an entry of 00001h
represents the second double-word of the display memory and so forth.
Calculate the Display Start Address as follows :
Main Window Display Start Address Bits 16:0
= Image address ÷ 4 (valid only for Display Rotate Mode 0°)
Note
For information on setting this register for other Display Rotate Mode see Section 18
“Display Rotate Mode”.
Main Window Line Address Offset Register 0
Bit
Type
Reset
state
REG[78h]
7
6
5
4
3
2
1
0
Main
window
Line
Address
Offset Bit 7
RW
0
Main
window
Line
Address
Offset Bit 6
RW
0
Main
window
Line
Address
Offset Bit 5
RW
0
Main
window
Line
Address
Offset Bit 4
RW
0
Main
window
Line
Address
Offset Bit 3
RW
0
Main
window
Line
Address
Offset Bit 2
RW
0
Main
window
Line
Address
Offset Bit 1
RW
0
Main
window
Line
Address
Offset Bit 0
RW
0
Main Window Line Address Offset Register 1
Bit
Type
Reset
state
REG[79h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Main
window
Line
Address
Offset Bit 9
RW
0
Main
window
Line
Address
Offset Bit 8
RW
0
REG[79h] bits 1-0,
REG[78h] bits 7-0
Main Window Line Address Offset Bits [9:0]
This register specifies the offset, in double words, from the beginning of one display
line to the beginning of the next display line, in the main window. Note that this is a
32-bit address increment.
Calculate the Line Address Offset as follows :
Main Window Line Address Offset bits 9-0
= Display Width in pixels ÷ (32 ÷ bpp)
Note
A virtual display can be created by programming this register with a value greater than
the formula requires. When a virtual display is created the image width is larger than
the display width and the displayed image becomes a window into the larger, virtual
image.
Solomon Systech
Aug 2005
P 41/159
Rev 1.1
SSD1906
7.2.7
Floating Window Registers
Floating Window Display Start Address Register 0
Bit
Type
Reset
state
REG[7Ch]
7
6
5
4
3
2
1
0
Floating
Window
Display
Start
Address
Bit 7
RW
0
Floating
Window
Display
Start
Address
Bit 6
RW
0
Floating
Window
Display
Start
Address
Bit 5
RW
0
Floating
Window
Display
Start
Address
Bit 4
RW
0
Floating
Window
Display
Start
Address
Bit 3
RW
0
Floating
Window
Display
Start
Address
Bit 2
RW
0
Floating
Window
Display
Start
Address
Bit 1
RW
0
Floating
Window
Display
Start
Address
Bit 0
RW
0
Floating Window Display Start Address Register 1
Bit
Type
Reset
state
REG[7Dh]
7
6
5
4
3
2
1
0
Floating
Window
Floating
Window
Display
Start
Address
Bit 14
RW
0
Floating
Window
Display
Start
Address
Bit 13
RW
0
Floating
Window
Display
Start
Address
Bit 12
RW
0
Floating
Window
Display
Start
Address
Bit 11
RW
0
Floating
Window
Display
Start
Address
Bit 10
RW
0
Floating
Window
Display
Start
Address
Bit 9
RW
0
Floating
Window
Display
Start
Address
Bit 8
RW
0
Display
Start
Address
Bit 15
RW
0
Floating Window Display Start Address Register 2
Bit
Type
Reset
state
REG[7Eh]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Floating
Window
Display
Start
Address
Bit 16
RW
0
REG[7Eh] bit 0,
REG[7Dh] bits 7-0,
REG[7Ch] bits 7-0
Floating Window Display Start Address Bits [16:0]
These bits form the 17-bit address for the starting double-word of the floating window.
Note that this is a double-word (32-bit) address. An entry of 00000h into these
registers represents the first double-word of display memory, an entry of 00001h
represents the second double-word of the display memory and so forth.
Note
These bits will not be effective until the Floating Window Enable bit is set to 1
(REG[71h] bit 4=1).
Solomon Systech
Aug 2005
P 42/159
Rev 1.1
SSD1906
Floating Window Line Address Offset Register 0
Bit
Type
Reset
state
REG[80h]
7
6
5
4
3
2
1
0
Floating
Window
Line
Address
Offset Bit 7
RW
0
Floating
Window
Line
Address
Offset Bit 6
RW
0
Floating
Window
Line
Address
Offset Bit 5
RW
0
Floating
Window
Line
Address
Offset Bit 4
RW
0
Floating
Window
Line
Address
Offset Bit 3
RW
0
Floating
Window
Line
Address
Offset Bit 2
RW
0
Floating
Window
Line
Address
Offset Bit 1
RW
0
Floating
Window
Line
Address
Offset Bit 0
RW
0
Floating Window Line Address Offset Register 1
Bit
Type
Reset
state
REG[81h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Floating
Window
Line
Address
Offset Bit 9
RW
0
Floating
Window
Line
Address
Offset Bit 8
RW
0
REG[81h] bits 1-0,
REG[80h] bits 7-0
Floating Window Line Address Offset Bits [9:0]
These bits are the LCD displays 10-bit address offset from the starting double-word of
line “n” to the starting double-word of line “n + 1” for the floating window. Note that this
is a 32-bit address increment.
Note
These bits will not be effective until the Floating Window Enable bit is set to 1
(REG[71h] bit 4=1).
Floating Window Start Position X Register 0
Bit
Type
Reset
state
REG[84h]
7
6
5
4
3
2
1
0
Floating
Window
Start X
Position Bit
7
RW
0
Floating
Window
Start X
Position Bit
6
RW
0
Floating
Window
Start X
Position Bit
5
RW
0
Floating
Window
Start X
Position Bit
4
RW
0
Floating
Window
Start X
Position Bit
3
RW
0
Floating
Window
Start X
Position Bit
2
RW
0
Floating
Window
Start X
Position Bit
1
RW
0
Floating
Window
Start X
Position Bit
0
RW
0
Solomon Systech
Aug 2005
P 43/159
Rev 1.1
SSD1906
Floating Window Start Position X Register 1
Bit
Type
Reset
state
REG[85h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Floating
Window
Start X
Position Bit
9
RW
0
Floating
Window
Start X
Position Bit
8
RW
0
REG[85h] bits 1-0,
REG[84h] bits 7-0
Floating Window Start Position X Bits [9:0]
These bits determine the start position X of the floating window, in relation to the origin
of the panel. Due to the SSD1906 Display Rotate feature, the start position X may not
be a horizontal position value (only true in 0° and 180° rotation). For further information
on defining the value of the Start Position X register see Section 19 “Floating Window
Mode”.
The value of this register is also increased differently, based on the display orientation.
For 0° and 180° Display Rotate Mode, the start position X is incremented by x pixels
where x is relative to the current color depth. Refer to Table 7-10 : 32-bit Address X
Increments for Various Color Depths. For 90° and 270° Display Rotate Mode, the start
position X is incremented by 1 line.
Depending on the color depth, some of the higher bits in this register are unused, as
the maximum horizontal display width is 1024 pixels.
Note
These bits will not be effective until the Floating Window Enable bit is set to 1
(REG[71h] bit 4=1).
Table 7-10 : 32-bit Address X Increments for Various Color Depths
Color Depth (bpp)
1
2
4
8
16
Pixel Increment (x)
32
16
8
4
2
Floating Window Start Position Y Register 0
Bit
Type
Reset
state
REG[88h]
7
6
5
4
3
2
1
0
Floating
Window
Start Y
Position Bit
7
RW
0
Floating
Window
Start Y
Position Bit
6
RW
0
Floating
Window
Start Y
Position Bit
5
RW
0
Floating
Window
Start Y
Position Bit
4
RW
0
Floating
Window
Start Y
Position Bit
3
RW
0
Floating
Window
Start Y
Position Bit
2
RW
0
Floating
Window
Start Y
Position Bit
1
RW
0
Floating
Window
Start Y
Position Bit
0
RW
0
Solomon Systech
Aug 2005
P 44/159
Rev 1.1
SSD1906
Floating Window Start Position Y Register 1
Bit
Type
Reset
state
REG[89h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Floating
Window
Start Y
Position Bit
9
RW
0
Floating
Window
Start Y
Position Bit
8
RW
0
REG[89h] bits 1-0,
REG[88h] bits 7-0
Floating Window Start Position Y Bits [9:0]
These bits determine the start position Y of the floating window in relation to the origin
of the panel. Due to the SSD1906 Display Rotate feature, the start position Y may not
be a vertical position value (only true in 0° and 180° Floating Window). For further
information on defining the value of the Start Position Y register see Section 19
“Floating Window Mode”.
The register is also incremented according to the display orientation. For 0° and 180°
Display Rotate Mode, the start position Y is incremented by 1 line. For 90° and 270°
Display Rotate Mode, the start position Y is incremented by y pixels where y is relative
to the current color depth. Refer to Table 7-11 : 32-bit Address Y Increments for
Various Color Depths.
Depending on the color depth, some of the higher bits in this register are unused, as
the maximum vertical display height is 1024 pixels.
Note
These bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h]
bit 4=1).
Table 7-11 : 32-bit Address Y Increments for Various Color Depths
Color Depth (bpp)
1
2
4
8
16
Pixel Increment (y)
32
16
8
4
2
Floating Window End Position X Register 0
Bit
Type
Reset
state
REG[8Ch]
7
6
5
4
3
2
1
0
Floating
Window
End X
Position Bit
7
RW
0
Floating
Window
End X
Position Bit
6
RW
0
Floating
Window
End X
Position Bit
5
RW
0
Floating
Window
End X
Position Bit
4
RW
0
Floating
Window
End X
Position Bit
3
RW
0
Floating
Window
End X
Position Bit
2
RW
0
Floating
Window
End X
Position Bit
1
RW
0
Floating
Window
End X
Position Bit
0
RW
0
Solomon Systech
Aug 2005
P 45/159
Rev 1.1
SSD1906
Floating Window End Position X Register 1
Bit
Type
Reset
state
REG[8Dh]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Floating
Window
End X
Position Bit
9
RW
0
Floating
Window
End X
Position Bit
8
RW
0
REG[8Dh] bits 1-0,
REG[8Ch] bits 7-0
Floating Window End Position X Bits [9:0]
These bits determine the end position X of the floating window in relation to the origin
of the panel. Due to the SSD1906 Display Rotate feature, the end position X may not
be a horizontal position value (only true in 0° and 180° rotation). For further information
on defining the value of the End Position X register see 19 “Floating Window Mode”.
The value of this register is also increased according to the display orientation. For 0°
and 180° Display Rotate Mode, the end position X is incremented by x pixels where x
is relative to the current color depth. Refer to Table 7-12 : 32-bit Address X Increments
for Various Color Depths. For 90° and 270° Display Rotate Mode, the end position X is
incremented by 1 line.
Depending on the color depth, some of the higher bits in this register are unused, as
the maximum horizontal display width is 1024 pixels.
Note
These bits will not be effective until the Floating Window Enable bit is set to 1
(REG[71h] bit 4=1).
Table 7-12 : 32-bit Address X Increments for Various Color Depths
Color Depth (bpp)
1
2
4
8
16
Pixel Increment (x)
32
16
8
4
2
Floating Window End Position Y Register 0
Bit
Type
Reset
state
REG[90h]
7
6
5
4
3
2
1
0
Floating
Window
End Y
Position Bit
7
RW
0
Floating
Window
Floating
Window
End Y
Position Bit
5
RW
0
Floating
Window
End Y
Position Bit
4
RW
0
Floating
Window
End Y
Position Bit
3
RW
0
Floating
Window
End Y
Position Bit
2
RW
0
Floating
Window
End Y
Position Bit
1
RW
0
Floating
Window
End Y
Position Bit
0
RW
0
Solomon Systech
End Y
Position Bit
6
RW
0
Aug 2005
P 46/159
Rev 1.1
SSD1906
Floating Window End Position Y Register 1
Bit
Type
Reset
state
REG[91h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Floating
Window
End Y
Position Bit
9
RW
0
Floating
Window
End Y
Position Bit
8
RW
0
REG[91h] bits 1-0,
REG[90h] bits 7-0
Floating Window End Position Y Bits [9:0]
Due to the SSD1906 Display Rotate feature, the end position Y may not be a vertical
position value (only true in 0° and 180° Display Rotate Mode). For further information
on defining the value of the End Position Y register see Section 19 “Floating Window
Mode”.
The value of this register is also increased according to the display orientation. For 0°
and 180° Display Rotate Mode, the end position Y is incremented by 1 line. For 90°
and 270° Display Rotate Mode, the end position Y is incremented by y pixels where y
is relative to the current color depth. Refer to Table 7-13 : 32-bit Address Y Increments
for Various Color Depths.
Depending on the color depth, some of the higher bits in this register are unused, as
the maximum vertical display height is 1024 pixels.
Note
These bits will not be effective until the Floating Window Enable bit is set to 1
(REG[71h] bit 4=1).
Table 7-13 : 32-bit Address Y Increments for Various Color Depths
Color Depth (bpp)
1
2
4
8
16
7.2.8
Pixel Increment (y)
32
16
8
4
2
Miscellaneous Registers
Power Saving Configuration Register
Bit
Type
Reset
state
REG[A0h]
7
6
5
4
3
2
1
0
Vertical
NonDisplay
Period
Status
RO
1
0
0
0
0
0
Power
Saving
Mode
Enable
NA
0
NA
0
NA
0
Memory
Controller
Power
Saving
Status
RO
0
NA
0
NA
0
RW
1
Solomon Systech
Aug 2005
P 47/159
Rev 1.1
SSD1906
Bit 7
Vertical Non-Display Period Status
When this bit = 0, the LCD panel is in Vertical Display Period.
When this bit = 1, the LCD panel is in Vertical Non-Display Period.
Memory Controller Power Saving Status
This bit indicates the Power Saving status of the memory controller.
When this bit = 0, the memory controller is powered up.
When this bit = 1, the memory controller is powered down.
Power Saving Mode Enable
When this bit = 1, Power Saving mode is enabled.
When this bit = 0, Power Saving mode is disabled.
Bit 3
Bit 0
Software Reset Register
Bit
Type
Reset
state
REG[A2h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Software
Reset
WO
0
Bit 0
Software Reset
When a one is written to this bit, the SSD1906 registers are reset. This bit has no
effect on the contents of the display buffer.
Scratch Pad Register 0
Bit
Type
Reset
state
REG[A4h]
7
6
5
4
3
2
1
0
Scratch
Pad
Bit 7
RW
0
Scratch
Pad
Bit 6
RW
0
Scratch
Pad
Bit 5
RW
0
Scratch
Pad
Bit 4
RW
0
Scratch
Pad
Bit 3
RW
0
Scratch
Pad
Bit 2
RW
0
Scratch
Pad
Bit 1
RW
0
Scratch
Pad
Bit 0
RW
0
Scratch Pad Register 1
Bit
Type
Reset
state
REG[A5h]
7
6
5
4
3
2
1
0
Scratch
Pad
Bit 15
RW
0
Scratch
Pad
Bit 14
RW
0
Scratch
Pad
Bit 13
RW
0
Scratch
Pad
Bit 12
RW
0
Scratch
Pad
Bit 11
RW
0
Scratch
Pad
Bit 10
RW
0
Scratch
Pad
Bit 9
RW
0
Scratch
Pad
Bit 8
RW
0
REG[A5h] bits 7-0,
REG[A4h] bits 7-0
Solomon Systech
Scratch Pad Bits [15:0]
This register contains general purpose read/write bits. These bits have no effect on
hardware configuration.
Aug 2005
P 48/159
Rev 1.1
SSD1906
Command Initialization Register
Bit
Type
Reset
state
6
5
4
3
2
1
0
Command
Initial bit 7
Command
Initial bit 6
Command
Initial bit 5
Command
Initial bit 4
Command
Initial bit 3
Command
Initial bit 2
Command
Initial bit 1
Command
Initial bit 0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 7-0
7.2.9
REG[134h]
7
Command Initialization Bits [7:0]
This is a startup register to initial the SSD1906 which should be programmed with 0x00
before register initialization.
General IO Pins Registers
General Purpose I/O Pins Configuration Register 0
Bit
7
0
Type
Reset
state
NA
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
6
5
4
REG[A8h]
3
2
1
0
GPIO6 I/O
GPIO5 I/O
GPIO4 I/O
GPIO3 I/O
GPIO2 I/O
GPIO1 I/O
GPIO0 I/O
Configuration Configuration Configuration Configuration Configuration Configuration Configuration
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
GPIO6 I/O Configuration
When this bit = 0, GPIO6 is configured as an input pin.
When this bit = 1, GPIO6 is configured as an output pin.
GPIO5 I/O Configuration
When this bit = 0, GPIO5 is configured as an input pin.
When this bit = 1, GPIO5 is configured as an output pin.
GPIO4 I/O Configuration
When this bit = 0, GPIO4 is configured as an input pin.
When this bit = 1, GPIO4 is configured as an output pin.
GPIO3 I/O Configuration
When this bit = 0, GPIO3 is configured as an input pin.
When this bit = 1, GPIO3 is configured as an output pin.
GPIO2 I/O Configuration
When this bit = 0, GPIO2 is configured as an input pin.
When this bit = 1, GPIO2 is configured as an output pin.
GPIO1 I/O Configuration
When this bit = 0, GPIO1 is configured as an input pin.
When this bit = 1, GPIO1 is configured as an output pin.
GPIO0 I/O Configuration
When this bit = 0, GPIO0 is configured as an input pin.
When this bit = 1, GPIO0 is configured as an output pin.
Note
If CF3 = 0 during RESET# is active, then all GPIO pins are configured as outputs only and
this register has no effect. This case allows the GPIO pins to be used by the HR-TFT
panel interfaces. For a summary of GPIO usage for HR-TFT, see Table 5-8 : LCD
Interface Pin Mapping.
The input functions of the GPIO pins are not enabled until REG[A9h] bit 7 is set to 1.
Solomon Systech
Aug 2005
P 49/159
Rev 1.1
SSD1906
General Purpose IO Pins Configuration Register 1
Bit
Type
Reset
state
REG[A9h]
7
6
5
4
3
2
1
0
GPIO Pin
Input
Enable
RW
0
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Bit 7
GPIO Pin Input Enable
This bit is used to enable the input function of the GPIO pins. It must be changed to a 1
after power-on reset to enable the input function of the GPIO pins.
General Purpose IO Pins Status/Control Register 0
Bit
Type
Reset
state
REG[ACh]
7
6
5
4
3
2
1
0
0
GPIO6 Pin
IO Status
RW
0
GPIO5 Pin
IO Status
RW
0
GPIO4 Pin
IO Status
RW
0
GPIO3 Pin
IO Status
RW
0
GPIO2 Pin
IO Status
RW
0
GPIO1 Pin
IO Status
RW
0
GPIO0 Pin
IO Status
RW
0
NA
0
Note
For information on GPIO pin mapping when HR-TFT panels are selected, see Table 5-2 : LCD Interface Pin
Descriptions.
Bit 6
GPIO6 Pin IO Status
When GPIO6 is configured as an output, writing a 1 to this bit drives GPIO6 high and
writing a 0 to this bit drives GPIO6 low.
Bit 5
When GPIO6 is configured as an input, a read from this bit returns the status of
GPIO6.
GPIO5 Pin IO Status
When GPIO5 is configured as an output, writing a 1 to this bit drives GPIO5 high and
writing a 0 to this bit drives GPIO5 low.
Bit 4
When GPIO5 is configured as an input, a read from this bit returns the status of
GPIO5.
GPIO4 Pin IO Status
When GPIO4 is configured as an output, writing a 1 to this bit drives GPIO4 high and
writing a 0 to this bit drives GPIO4 low.
Bit 3
When GPIO4 is configured as an input, a read from this bit returns the status of
GPIO4.
GPIO3 Pin IO Status
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO3 is
configured as an output, writing a 1 to this bit drives GPIO3 high and writing a 0 to this
bit drives GPIO3 low.
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO3 is
configured as an input, a read from this bit returns the status of GPIO3.
When a HR-TFT panel is enabled (REG[10h] bits 2:0 = 010), the HR-TFT signal SPL
signal is enabled whatever the value of this bit.
Solomon Systech
Aug 2005
P 50/159
Rev 1.1
SSD1906
Bit 2
GPIO2 Pin IO Status
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO2 is
configured as an output, writing a 1 to this bit drives GPIO2 high and writing a 0 to this
bit drives GPIO2 low.
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO2 is
configured as an input, a read from this bit returns the status of GPIO2.
When a HR-TFT panel is enabled (REG[10h] bits 2:0 = 010), the HR-TFT signal REV
signal is enabled whatever the value of this bit.
Bit 1
GPIO1 Pin IO Status
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO1 is
configured as an output, writing a 1 to this bit drives GPIO1 high and writing a 0 to this
bit drives GPIO1 low.
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO1 is
configured as an input, a read from this bit returns the status of GPIO1.
When a HR-TFT panel is enabled (REG[10h] bits 2:0 = 010), the HR-TFT signal CLS
signal is enabled whatever the value of this bit.
Bit 0
GPIO0 Pin IO Status
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO0 is
configured as an output, writing a 1 to this bit drives GPIO0 high and writing a 0 to this
bit drives GPIO0 low.
When a HR-TFT is not selected (REG[10h] bits 2:0 is not 010) and GPIO0 is
configured as an input, a read from this bit returns the status of GPIO0.
When a HR-TFT panel is enabled (REG[10h] bits 2:0 = 010), the HR-TFT signal PS
signal is enabled whatever the value of this bit.
General Purpose IO Pins Status/Control Register 1
Bit
Type
Reset
state
REG[ADh]
7
6
5
4
3
2
1
0
GPO
Control
RW
0
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Bit 7
GPO Control
This bit controls the General Purpose Output pin.
Writing a 0 to this bit drives GPO to low.
Writing a 1 to this bit drives GPO to high.
Note
Many implementations use the GPO pin to control the LCD bias power (see Section
10.3, “LCD Power Sequencing”).
Solomon Systech
Aug 2005
P 51/159
Rev 1.1
SSD1906
7.2.10 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration
Registers
PWM Clock Enable
PWM Clock
Divider
PWMCLK
Divided
Clock
PWM Duty Cycle
Modulation
LPWMOUT
Clock Source/ 2m
Duty = n / 256
m = PWM Clock Divide Select value
Frequency =
Clock Source / (2m X 256)
n = PWM Clock Duty Cycle
PW M Clock Force High
CV Pulse Force High
CV Pulse
Divider
Divided
Clock
CV Pulse Burst
Generation
LCVOUT
Clock Source/ 2x
y-pulse burst
x = CV Pulse Divide Select value
Frequency =
Clock Source / (2x X 2)
y = Burst Length value
CV Pulse Enable
Figure 7-3 : PWM Clock/CV Pulse Block Diagram
Note
For further information on PWMCLK, see Section 11.1.4 “PWMCLK”.
PWM Clock / CV Pulse Control Register
Bit
Type
Reset
state
REG[B0h]
7
6
5
4
3
2
1
0
PWM Clock
Force High
0
0
PWM Clock
Enable
CV Pulse
Force High
CV Pulse
Burst Start
CV Pulse
Enable
RW
0
NA
0
NA
0
RW
0
RW
0
CV Pulse
Burst
Status
RO
0
RW
0
RW
0
Bit 7 and Bit 4
PWM Clock Force High (bit 7) and PWM Clock Enable (bit 4)
These bits control the LPWMOUT pin and PWM Clock circuitry as Table 7-14 : PWM
Clock Control.
When LPWMOUT is forced low or forced high it can be used as a general purpose
output.
Note
The PWM Clock circuitry is disabled when Power Saving Mode is enabled.
Table 7-14 : PWM Clock Control
Bit 7
0
Bit 4
1
0
1
0
X
Result
PWM Clock circuitry enabled
(controlled by REG[B1h] and REG[B3h])
LPWMOUT forced low
LPWMOUT forced high
x = don’t care
Solomon Systech
Aug 2005
P 52/159
Rev 1.1
SSD1906
Bit 3 and Bit 0
CV Pulse Force High (bit 3) and CV Pulse Enable (bit 0)
These bits control the LCVOUT pin and CV Pulse circuitry as Table 7-15 : CV Pulse
Control.
When LCVOUT is forced low or forced high it can be used as a general purpose
output.
Note
Bit 3 must be set to 0 and bit 0 must be set to 1 before initiating a new burst using the
CV Pulse Burst Start bit.
The CV Pulse circuitry is disabled when Power Saving Mode is enabled.
Table 7-15 : CV Pulse Control
Bit 3
0
0
1
Bit 0
1
0
x
Result
CV Pulse circuitry enabled (controlled by REG[B1h] and REG[B2h])
LCVOUT forced low
LCVOUT forced high
x = don’t care
Bit 2
CV Pulse Burst Status
A “1” indicates a CV pulse burst is occurring. A “0” indicates no CV pulse burst is
occurring. Software should wait for this bit to clear before starting another burst.
CV Pulse Burst Start
A “1” in this bit initiates a single LCVOUT pulse burst. The number of clock pulses
generated is programmable from 1 to 256. The frequency of the pulses is the divided
CV Pulse source divided by 2, with 50/50 duty cycle. This bit should be cleared to 0 by
software before initiating a new burst.
Bit 1
Note
This bit has effect only if the CV Pulse Enable bit is 1.
PWM Clock / CV Pulse Configuration Register
Bit
Type
Reset
state
REG[B1h]
7
6
5
4
3
2
1
0
PWM Clock
Divide
Select
Bit 3
RW
0
PWM Clock
Divide
Select
Bit 2
RW
0
PWM Clock
Divide
Select
Bit 1
RW
0
PWM Clock
Divide
Select
Bit 0
RW
0
CV Pulse
Divide
Select
Bit 2
RW
0
CV Pulse
Divide
Select
Bit 1
RW
0
CV Pulse
Divide
Select
Bit 0
RW
0
PWMCLK
Source
Select
Bits 7-4
PWM Clock Divide Select Bits [3:0]
The value of these bits represents the power of 2 by which the selected PWM clock
source is divided.
Note
This divided clock is further divided by 256 before it is output at LPWMOUT.
Table 7-16 : PWM Clock Divide Select Options
PWM Clock Divide Select Bits [3:0]
0h
1h
2h
3h
...
Ch
Solomon Systech
RW
0
PWM Clock Divide Amount
1
2
4
8
...
4096
Aug 2005
P 53/159
Rev 1.1
SSD1906
Dh-Fh
Bits 3-1
1
CV Pulse Divide Select Bits [2:0]
The value of these bits represents the power of 2 by which the selected CV Pulse
source is divided.
Note
This divided clock is further divided by 2 before it is output at the LCVOUT.
Table 7-17 : CV Pulse Divide Select Options
CV Pulse Divide Select Bits [2:0]
0h
1h
2h
3h
...
7h
Bit 0
CV Pulse Divide Amount
1
2
4
8
...
128
PWMCLK Source Select
When this bit = 0, the clock source for PWMCLK is CLKI.
When this bit = 1, the clock source for PWMCLK is AUXCLK.
Note
For further information on the PWMCLK source select, see Section 11 “Clocks”.
CV Pulse Burst Length Register
Bit
6
5
4
3
2
1
0
CV Pulse
Burst
Length
CV Pulse
Burst
Length
Bit 6
RW
0
CV Pulse
Burst
Length
Bit 5
RW
0
CV Pulse
Burst
Length
Bit 4
RW
0
CV Pulse
Burst
Length
Bit 3
RW
0
CV Pulse
Burst
Length
Bit 2
RW
0
CV Pulse
Burst
Length
Bit 1
RW
0
CV Pulse
Burst
Length
Bit 0
RW
0
Bit 7
Type
Reset
state
REG[B2h]
7
RW
0
Bits 7-0
CV Pulse Burst Length Bits [7:0]
The value of this register determines the number of pulses generated in a single CV
Pulse burst:
Number of pulses in a burst = Bits [7:0] + 1
LPWMOUT Duty Cycle Register
Bit
Type
Reset
state
REG[B3h]
7
6
5
4
3
2
1
0
LPWMOUT
Duty Cycle
Bit 7
RW
0
LPWMOUT
Duty Cycle
Bit 6
RW
0
LPWMOUT
Duty Cycle
Bit 5
RW
0
LPWMOUT
Duty Cycle
Bit 4
RW
0
LPWMOUT
Duty Cycle
Bit 3
RW
0
LPWMOUT
Duty Cycle
Bit 2
RW
0
LPWMOUT
Duty Cycle
Bit 1
RW
0
LPWMOUT
Duty Cycle
Bit 0
RW
0
Bits 7-0
Solomon Systech
LPWMOUT Duty Cycle Bits [7:0]
This register determines the duty cycle of the LPWMOUT output.
Aug 2005
P 54/159
Rev 1.1
SSD1906
Table 7-18 : LPWMOUT Duty Cycle Select Options
LPWMOUT Duty Cycle [7:0]
00h
01h
02h
…
FFh
LPWMOUT Duty Cycle
Always Low
High for 1 out of 256 clock periods
High for 2 out of 256 clock periods
…
High for 255 out of 256 clock periods.
7.2.11 Cursor Mode Registers
Cursor Feature Register
Bit
Type
Reset
state
REG[C0h]
7
6
5
4
3
2
1
0
Cursor1
Enable
RW
0
Cursor2
Enable
RW
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Bit 7
Cursor1 Enable
When this bit = 0 Cursor1 is disabled.
When this bit = 1 Cursor1 is enabled.
Cursor2 Enable
When this bit = 0, Cursor2 is disabled.
When this bit = 1, Cursor2 is enabled.
Bit 6
Note
This register is effective for 4/8/16 bpp (REG[70h] Bits 2:0 = 010/011/100)
For Hardware Cursors operation, see Section 20 “Hardware Cursor Mode”.
Cursor1 Blink Total Register 0
Bit
Type
Reset
state
REG[C4h]
7
6
5
4
3
2
1
0
Cursor1
Blink Total
Bit 7
RW
0
Cursor1
Blink Total
Bit 6
RW
0
Cursor1
Blink Total
Bit 5
RW
0
Cursor1
Blink Total
Bit 4
RW
0
Cursor1
Blink Total
Bit 3
RW
0
Cursor1
Blink Total
Bit 2
RW
0
Cursor1
Blink Total
Bit 1
RW
0
Cursor1
Blink Total
Bit 0
RW
0
Cursor1 Blink Total Register 1
Bit
Type
Reset
state
REG[C5h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Cursor1
Blink Total
Bit 9
RW
0
Cursor1
Blink Total
Bit 8
RW
0
REG[C5h] bits 1-0,
REG[C4h] bits 7-0
Cursor1 Blink Total Bits [9:0]
This is the total blinking period per frame for cursor1. This register must be set to a
non-zero value in order to make the cursor visible.
Note
Solomon Systech
Aug 2005
P 55/159
Rev 1.1
SSD1906
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Cursor1 Blink On Register 0
REG[C8h]
Bit
Type
Reset
state
7
6
5
4
3
2
1
0
Cursor1
Blink On Bit
7
RW
0
Cursor1
Blink On Bit
6
RW
0
Cursor1
Blink On Bit
5
RW
0
Cursor1
Blink On Bit
4
RW
0
Cursor1
Blink On Bit
3
RW
0
Cursor1
Blink On Bit
2
RW
0
Cursor1
Blink On Bit
1
RW
0
Cursor1
Blink On Bit
0
RW
0
Cursor1 Blink On Register 1
Bit
Type
Reset
state
REG[C9h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Cursor1
Blink On Bit
9
RW
0
Cursor1
Blink On Bit
8
RW
0
REG[C9h] bits 1-0,
REG[C8h] bits 7-0
Cursor1 Blink On Bits [9:0]
This is the blink on frame period for Cursor1. This register must be set to a non-zero
value in order to make the cursor1 visible. Also, cursor1 will start to blink if the
following conditions are fulfilled :
Cursor1 Blink Total Bits [9:0] > Cursor1 Blink On Bits [9:0] > 0
Note
To enable cursor1 without blinking, user must program cursor1 blink on register with a
non-zero value, and this value must be greater than or equal to Cursor1 Blink Total
Register.
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Cursor1 Memory Start Register 0
Bit
Type
Reset
state
REG[CCh]
7
6
5
4
3
2
1
0
Cursor1
Memory
Start Bit 7
RW
0
Cursor1
Memory
Start Bit 6
RW
0
Cursor1
Memory
Start Bit 5
RW
0
Cursor1
Memory
Start Bit 4
RW
0
Cursor1
Memory
Start Bit 3
RW
0
Cursor1
Memory
Start Bit 2
RW
0
Cursor1
Memory
Start Bit 1
RW
0
Cursor1
Memory
Start Bit 0
RW
0
Cursor1 Memory Start Register 1
Bit
Type
Reset
state
REG[CDh]
7
6
5
4
3
2
1
0
Cursor1
Memory
Start Bit 15
RW
0
Cursor1
Memory
Start Bit 14
RW
0
Cursor1
Memory
Start Bit 13
RW
0
Cursor1
Memory
Start Bit 12
RW
0
Cursor1
Memory
Start Bit 11
RW
0
Cursor1
Memory
Start Bit 10
RW
0
Cursor1
Memory
Start Bit 9
RW
0
Cursor1
Memory
Start Bit 8
RW
0
Cursor1 Memory Start Register 2
Bit
Type
Reset
REG[CEh]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Cursor1
Memory
Start Bit 16
RW
0
Solomon Systech
Aug 2005
P 56/159
Rev 1.1
SSD1906
Bit
7
6
5
4
3
2
1
0
state
REG[CEh] bit 0,
REG[CDh] bits 7-0,
REG[CCh] bits 7-0
Cursor1 Memory Start Bits [16:0]
These bits form the 17-bit address for the starting double-word of the LCD image in the
display buffer for the Cursor1 image.
Note that this is a double-word (32-bit) address. An entry of 00000h into these
registers represents the first double-word of display memory, an entry of 00001h
represents the second double-word of the display memory, and so on.
Calculate the Cursor1 Start Address as follows :
Cursor1 Memory Start Bits 16:0
= Cursor Image address ÷ 4 (valid only for Display Rotate Mode 0°)
Note
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Cursor1 Position X Register 0
Bit
Type
Reset
state
REG[D0h]
7
6
5
4
3
2
1
0
Cursor1
Position X
Bit 7
RW
0
Cursor1
Position X
Bit 6
RW
0
Cursor1
Position X
Bit 5
RW
0
Cursor1
Position X
Bit 4
RW
0
Cursor1
Position X
Bit 3
RW
0
Cursor1
Position X
Bit 2
RW
0
Cursor1
Position X
Bit 1
RW
0
Cursor1
Position X
Bit 0
RW
0
Cursor1 Position X Register 1
Bit
Type
Reset
state
REG[D1h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Cursor1
Position X
Bit 9
RW
0
Cursor1
Position X
Bit 8
RW
0
REG[D1h] bits 1-0,
REG[D0h] bits 7-0
Cursor1 Position X Bits [9:0]
This is starting position X of Cursor1 image. The definition of this register is same as
Floating Window Start Position X Register.
Note
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Cursor1 Position Y Register 0
Bit
Type
Reset
state
REG[D4h]
7
6
5
4
3
2
1
0
Cursor1
Position Y
Bit 7
RW
0
Cursor1
Position Y
Bit 6
RW
0
Cursor1
Position Y
Bit 5
RW
0
Cursor1
Position Y
Bit 4
RW
0
Cursor1
Position Y
Bit 3
RW
0
Cursor1
Position Y
Bit 2
RW
0
Cursor1
Position Y
Bit 1
RW
0
Cursor1
Position Y
Bit 0
RW
0
Cursor1 Position Y Register 1
Bit
REG[D5h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Cursor1
Position Y
Bit 9
Cursor1
Position Y
Bit 8
Solomon Systech
Aug 2005
P 57/159
Rev 1.1
SSD1906
Bit
7
6
5
4
3
2
1
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
RW
0
RW
0
REG[D5h] bits 1-0,
REG[D4h] bits 7-0
Cursor1 Position Y Bits [9:0]
This is starting position Y of Cursor1 image. The definition of this register is same as
Floating Window Y Start Position Register.
Note
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Cursor1 Horizontal Size Register 0
Bit
Type
Reset
state
REG[D8h]
7
6
5
4
3
2
1
0
Cursor1
Horizontal
Size Bit 7
RW
0
Cursor1
Horizontal
Size Bit 6
RW
0
Cursor1
Horizontal
Size Bit 5
RW
0
Cursor1
Horizontal
Size Bit 4
RW
0
Cursor1
Horizontal
Size Bit 3
RW
0
Cursor1
Horizontal
Size Bit 2
RW
0
Cursor1
Horizontal
Size Bit 1
RW
0
Cursor1
Horizontal
Size Bit 0
RW
0
Cursor1 Horizontal Size Register 1
Bit
Type
Reset
state
REG[D9h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Cursor1
Horizontal
Size Bit 9
RW
0
Cursor1
Horizontal
Size Bit 8
RW
0
REG[D9h] bits 1-0,
REG[D8h] bits 7-0
Cursor1 Horizontal Size Bits [9:0]
These bits specify the horizontal size of Cursor1.
Note
The definition of this register various under different panel orientation and color depth
settings.
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Table 7-19 : X Increment Mode for Various Color Depths
Orientation
0û
90û
180û
270û
Solomon Systech
Color Depths (bpp)
4
8
16
4
8
16
4
8
16
4
8
16
Increment (x)
16 pixels increment
e.g. 0000h = 16 pixels; 0001h = 32 pixels
2 lines increment
4 lines increment
8 lines increment
16 pixels increment
2 lines increment
4 lines increment
8 lines increment
Aug 2005
P 58/159
Rev 1.1
SSD1906
Cursor1 Vertical Size Register 0
Bit
Type
Reset
state
REG[DCh]
7
6
5
4
3
2
1
0
Cursor1
Vertical
Size Bit 7
RW
0
Cursor1
Vertical
Size Bit 6
RW
0
Cursor1
Vertical
Size Bit 5
RW
0
Cursor1
Vertical
Size Bit 4
RW
0
Cursor1
Vertical
Size Bit 3
RW
0
Cursor1
Vertical
Size Bit 2
RW
0
Cursor1
Vertical
Size Bit 1
RW
0
Cursor1
Vertical
Size Bit 0
RW
0
Cursor1 Vertical Size Register 1
Bit
Type
Reset
state
REG[DDh]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Cursor1
Vertical
Size Bit 9
RW
0
Cursor1
Vertical
Size Bit 8
RW
0
REG[DDh] bits 1-0,
REG[DCh] bits 7-0
Cursor1 Vertical Size Bits [9:0]
These bits specify the vertical size of Cursor1.
Note
The definition of this register various under different panel orientation and color depth
settings.
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Table 7-20 : Y Increment Mode for Various Color Depths
Orientation
0û
90û
180û
270û
Color Depths (bpp)
4
8
16
4
8
16
4
8
16
4
8
16
Increment (y)
1 line increment
e.g. 0000h = 1 line; 0001h = 2 lines
8 pixels increment
4 pixels increment
2 pixels increment
1 line increment
8 pixels increment
4 pixels increment
2 pixels increment
Cursor1 Color Index1 Register 0
Bit
Type
Reset
state
REG[E0h]
7
6
5
4
3
2
1
0
Cursor1
Color
Index1 Bit 7
RW
0
Cursor1
Color
Index1 Bit 6
RW
0
Cursor1
Color
Index1 Bit 5
RW
0
Cursor1
Color
Index1 Bit 4
RW
0
Cursor1
Color
Index1 Bit 3
RW
0
Cursor1
Color
Index1 Bit 2
RW
0
Cursor1
Color
Index1 Bit 1
RW
0
Cursor1
Color
Index1 Bit 0
RW
0
Solomon Systech
Aug 2005
P 59/159
Rev 1.1
SSD1906
Cursor1 Color Index1 Register 1
Bit
Type
Reset
state
REG[E1h]
7
6
5
4
3
2
1
0
Cursor1
Color
Index1 Bit
15
RW
0
Cursor1
Color
Index1 Bit
14
RW
0
Cursor1
Color
Index1 Bit
13
RW
0
Cursor1
Color
Index1 Bit
12
RW
0
Cursor1
Color
Index1 Bit
11
RW
0
Cursor1
Color
Index1 Bit
10
RW
0
Cursor1
Color
Index1 Bit
9
RW
0
Cursor1
Color
Index1 Bit
8
RW
0
REG[E1h] bits 7-0,
REG[E0h] bits 7-0
Cursor1 Color Index1 Bits [15:0]
Each cursor pixel is represented by 2 bits. This register stores the color index for pixel
value 01 of Cursor1, refer to Table 20-1.
Note
These bits will not be effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit
7=1).
For Hardware Cursors operation see Section 20 “Hardware Cursor Mode”.
Cursor1 Color Index2 Register 0
Bit
Type
Reset
state
REG[E4h]
7
6
5
4
3
2
1
0
Cursor1
Color
Index2 Bit 7
RW
0
Cursor1
Color
Index2 Bit 6
RW
0
Cursor1
Color
Index2 Bit 5
RW
0
Cursor1
Color
Index2 Bit 4
RW
0
Cursor1
Color
Index2 Bit 3
RW
0
Cursor1
Color
Index2 Bit 2
RW
0
Cursor1
Color
Index2 Bit 1
RW
0
Cursor1
Color
Index2 Bit 0
RW
0
Cursor1 Color Index2 Register 1
Bit
Type
Reset
state
REG[E5h]
7
6
5
4
3
2
1
0
Cursor1
Color
Index2 Bit
15
RW
0
Cursor1
Color
Index2 Bit
14
RW
0
Cursor1
Color
Index2 Bit
13
RW
0
Cursor1
Color
Index2 Bit
12
RW
0
Cursor1
Color
Index2 Bit
11
RW
0
Cursor1
Color
Index2 Bit
10
RW
0
Cursor1
Color
Index2 Bit
9
RW
0
Cursor1
Color
Index2 Bit
8
RW
0
REG[E5h] bits 7-0,
REG[E4h] bits 7-0
Cursor1 Color Index2 Bits [15:0]
Each cursor pixel is represented by 2 bits. This register stores the color index for pixel
value 10 of Cursor1, refer to Table 20-1.
Note
These bits will not be effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit
7=1).
For Hardware Cursors operation see Section 20 “Hardware Cursor Mode”.
Cursor1 Color Index3 Register 0
Bit
Type
Reset
state
REG[E8h]
7
6
5
4
3
2
1
0
Cursor1
Color
Index3 Bit 7
RW
0
Cursor1
Color
Index3 Bit 6
RW
0
Cursor1
Color
Index3 Bit 5
RW
0
Cursor1
Color
Index3 Bit 4
RW
0
Cursor1
Color
Index3 Bit 3
RW
0
Cursor1
Color
Index3 Bit 2
RW
0
Cursor1
Color
Index3 Bit 1
RW
0
Cursor1
Color
Index3 Bit 0
RW
0
Solomon Systech
Aug 2005
P 60/159
Rev 1.1
SSD1906
Solomon Systech
Aug 2005
P 61/159
Rev 1.1
SSD1906
Cursor1 Color Index3 Register 1
Bit
Type
Reset
state
REG[E9h]
7
6
5
4
3
2
1
0
Cursor1
Color
Index3 Bit
15
RW
0
Cursor1
Color
Index3 Bit
14
RW
0
Cursor1
Color
Index3 Bit
13
RW
0
Cursor1
Color
Index3 Bit
12
RW
0
Cursor1
Color
Index3 Bit
11
RW
0
Cursor1
Color
Index3 Bit
10
RW
0
Cursor1
Color
Index3 Bit
9
RW
0
Cursor1
Color
Index3 Bit
8
RW
0
REG[E9h] bits 7-0,
REG[E8h] bits 7-0
Cursor1 Color Index3 Bits [15:0]
Each cursor pixel is represented by 2 bits. This register stores the color index for pixel
value 11 of Cursor1, refer to Table 20-1.
Note
These bits will not be effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit
7=1).
For Hardware Cursors operation see Section 20 “Hardware Cursor Mode”.
Cursor2 Blink Total Register 0
Bit
Type
Reset
state
REG[ECh]
7
6
5
4
3
2
1
0
Cursor2
Blink Total
Bit 7
RW
0
Cursor2
Blink Total
Bit 6
RW
0
Cursor2
Blink Total
Bit 5
RW
0
Cursor2
Blink Total
Bit 4
RW
0
Cursor2
Blink Total
Bit 3
RW
0
Cursor2
Blink Total
Bit 2
RW
0
Cursor2
Blink Total
Bit 1
RW
0
Cursor2
Blink Total
Bit 0
RW
0
Cursor2 Blink Total Register 1
Bit
Type
Reset
state
REG[EDh]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Cursor2
Blink Total
Bit 9
RW
0
Cursor2
Blink Total
Bit 8
RW
0
REG[EDh] bits 1-0,
REG[ECh] bits 7-0
Cursor2 Blink Total Bits [9:0]
This is the total blinking period per frame for Cursor2. This register must be set to a
non-zero value in order to make the cursor visible.
Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).
Cursor2 Blink On Register 0
Bit
Type
Reset
state
REG[F0h]
7
6
5
4
3
2
1
0
Cursor2
Blink On Bit
7
RW
0
Cursor2
Blink On Bit
6
RW
0
Cursor2
Blink On Bit
5
RW
0
Cursor2
Blink On Bit
4
RW
0
Cursor2
Blink On Bit
3
RW
0
Cursor2
Blink On Bit
2
RW
0
Cursor2
Blink On Bit
1
RW
0
Cursor2
Blink On Bit
0
RW
0
Solomon Systech
Aug 2005
P 62/159
Rev 1.1
SSD1906
Cursor2 Blink On Register 1
Bit
Type
Reset
state
REG[F1h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Cursor2
Blink On Bit
9
RW
0
Cursor2
Blink On Bit
8
RW
0
REG[F1h] bits 1-0,
REG[F0h] bits 7-0
Cursor2 Blink On Bits [9:0]
This is the blink on frame period for Cursor2. This register must be set to a non-zero
value in order to make the Cursor2 visible. Cursor2 will start to blink if:
Cursor2 Blink Total Bits [9:0] > Cursor2 Blink On Bits [9:0] > 0
Note
To enable Cursor2 without blinking the user must program Cursor2 Blink On Register
with a non-zero value and this value must be greater than or equal to Cursor2 Blink
Total Register.
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).
Cursor2 Memory Start Register 0
Bit
Type
Reset
state
REG[F4h]
7
6
5
4
3
2
1
0
Cursor2
Memory
Start Bit 7
RW
0
Cursor2
Memory
Start Bit 6
RW
0
Cursor2
Memory
Start Bit 5
RW
0
Cursor2
Memory
Start Bit 4
RW
0
Cursor2
Memory
Start Bit 3
RW
0
Cursor2
Memory
Start Bit 2
RW
0
Cursor2
Memory
Start Bit 1
RW
0
Cursor2
Memory
Start Bit 0
RW
0
Cursor2 Memory Start Register 1
Bit
Type
Reset
state
REG[F5h]
7
6
5
4
3
2
1
0
Cursor2
Memory
Start Bit 15
RW
0
Cursor2
Memory
Start Bit 14
RW
0
Cursor2
Memory
Start Bit 13
RW
0
Cursor2
Memory
Start Bit 12
RW
0
Cursor2
Memory
Start Bit 11
RW
0
Cursor2
Memory
Start Bit 10
RW
0
Cursor2
Memory
Start Bit 9
RW
0
Cursor2
Memory
Start Bit 8
RW
0
Cursor2 Memory Start Register 2
Bit
Type
Reset
state
REG[F6h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Cursor2
Memory
Start Bit 16
RW
0
Solomon Systech
Aug 2005
P 63/159
Rev 1.1
SSD1906
REG[F6h] bit 0,
REG[F5h] bits 7-0,
REG[F4h] bits 7-0
Cursor2 Memory Start Bits [16:0]
These bits form the 17-bit address for the starting double-word of the LCD image in the
display buffer for the Cursor2 image.
Note that this is a double-word (32-bit) address. An entry of 00000h into these
registers represents the first double-word of display memory, an entry of 00001h
represents the second double-word of the display memory and so forth.
Calculate the Cursor2 Start Address as follows:
Cursor2 Memory Start Bits 16:0
= Cursor Image address ÷ 4 (valid only for Display Rotate Mode 0°)
Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).
Cursor2 Position X Register 0
Bit
Type
Reset
state
REG[F8h]
7
6
5
4
3
2
1
0
Cursor2
Position X
Bit 7
RW
0
Cursor2
Position X
Bit 6
RW
0
Cursor2
Position X
Bit 5
RW
0
Cursor2
Position X
Bit 4
RW
0
Cursor2
Position X
Bit 3
RW
0
Cursor2
Position X
Bit 2
RW
0
Cursor2
Position X
Bit 1
RW
0
Cursor2
Position X
Bit 0
RW
0
Cursor2 Position X Register 1
Bit
Type
Reset
state
REG[F9h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Cursor2
Position X
Bit 9
RW
0
Cursor2
Position X
Bit 8
RW
0
REG[F9h] bits 1-0,
REG[F8h] bits 7-0
Cursor2 Position X Bits [9:0]
This is starting position X of Cursor2 image. The definition of this register is the same
as the Floating Window Start Position X Register.
Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).
Cursor2 Position Y Register 0
Bit
Type
Reset
state
REG[FCh]
7
6
5
4
3
2
1
0
Cursor2
Position Y
Bit 7
RW
0
Cursor2
Position Y
Bit 6
RW
0
Cursor2
Position Y
Bit 5
RW
0
Cursor2
Position Y
Bit 4
RW
0
Cursor2
Position Y
Bit 3
RW
0
Cursor2
Position Y
Bit 2
RW
0
Cursor2
Position Y
Bit 1
RW
0
Cursor2
Position Y
Bit 0
RW
0
Cursor2 Position Y Register 1
Bit
Type
REG[FDh]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
NA
NA
NA
NA
NA
Cursor2
Position Y
Bit 9
RW
Cursor2
Position Y
Bit 8
RW
Solomon Systech
Aug 2005
P 64/159
Rev 1.1
SSD1906
Bit
7
6
5
4
3
2
1
0
Reset
state
0
0
0
0
0
0
0
0
REG[FDh] bits 1-0,
REG[FCh] bits 7-0
Cursor2 Position Y Bits [9:0]
This is the starting position Y of Cursor2 image. The definition of this register is the
same as the Floating Window Y Start Position Register.
Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).
Cursor2 Horizontal Size Register 0
Bit
Type
Reset
state
REG[100h]
7
6
5
4
3
2
1
0
Cursor2
Horizontal
Size Bit 7
RW
0
Cursor2
Horizontal
Size Bit 6
RW
0
Cursor2
Horizontal
Size Bit 5
RW
0
Cursor2
Horizontal
Size Bit 4
RW
0
Cursor2
Horizontal
Size Bit 3
RW
0
Cursor2
Horizontal
Size Bit 2
RW
0
Cursor2
Horizontal
Size Bit 1
RW
0
Cursor2
Horizontal
Size Bit 0
RW
0
Cursor2 Horizontal Size Register 1
Bit
Type
Reset
state
REG[101h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Cursor2
Horizontal
Size Bit 9
RW
0
Cursor2
Horizontal
Size Bit 8
RW
0
REG[101h] bits 1-0,
REG[100h] bits 7-0
Cursor2 Horizontal Size Bits [9:0]
These bits specify the horizontal size of Cursor2.
Note
The definition of this register varies under different panel orientation and color depth
settings, refer to Table 7-19 : X Increment Mode for Various Color Depths.
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).
Cursor2 Vertical Size Register 0
Bit
Type
Reset
state
REG[104h]
7
6
5
4
3
2
1
0
Cursor2
Vertical
Size Bit 7
RW
0
Cursor2
Vertical
Size Bit 6
RW
0
Cursor2
Vertical
Size Bit 5
RW
0
Cursor2
Vertical
Size Bit 4
RW
0
Cursor2
Vertical
Size Bit 3
RW
0
Cursor2
Vertical
Size Bit 2
RW
0
Cursor2
Vertical
Size Bit 1
RW
0
Cursor2
Vertical
Size Bit 0
RW
0
Cursor2 Vertical Size Register 1
Bit
Type
Reset
state
REG[105h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Cursor2
Vertical
Size Bit 9
RW
0
Cursor2
Vertical
Size Bit 8
RW
0
Solomon Systech
Aug 2005
P 65/159
Rev 1.1
SSD1906
Solomon Systech
Aug 2005
P 66/159
Rev 1.1
SSD1906
REG[105h] bits 1-0,
REG[104h] bits 7-0
Cursor2 Vertical Size Bits [9:0]
These bits specify the vertical size of Cursor2.
Note
The definition of this register varies under different panel orientation and color depth
settings, refer to Table 7-20 : Y Increment Mode for Various Color Depths.
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).
Cursor2 Color Index1 Register 0
Bit
Type
Reset
state
REG[108h]
7
6
5
4
3
2
1
0
Cursor2
Color
Index1 Bit 7
RW
0
Cursor2
Color
Index1 Bit 6
RW
0
Cursor2
Color
Index1 Bit 5
RW
0
Cursor2
Color
Index1 Bit 4
RW
0
Cursor2
Color
Index1 Bit 3
RW
0
Cursor2
Color
Index1 Bit 2
RW
0
Cursor2
Color
Index1 Bit 1
RW
0
Cursor2
Color
Index1 Bit 0
RW
0
Cursor2 Color Index1 Register 1
Bit
Type
Reset
state
REG[109h]
7
6
5
4
3
2
1
0
Cursor2
Color
Index1 Bit
15
RW
0
Cursor2
Color
Index1 Bit
14
RW
0
Cursor2
Color
Index1 Bit
13
RW
0
Cursor2
Color
Index1 Bit
12
RW
0
Cursor2
Color
Index1 Bit
11
RW
0
Cursor2
Color
Index1 Bit
10
RW
0
Cursor2
Color
Index1 Bit 9
Cursor2
Color
Index1 Bit 8
RW
0
RW
0
REG[109h] bits 7-0
REG[108h] bits 7-0
Cursor2 Color Index1 Bits [15:0]
Each cursor pixel is represented by 2 bits. This register stores the color index for pixel
value 01 of Cursor2, refer to Table 20-1.
Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).
For Hardware Cursor operation see Section 20 “Hardware Cursor Mode”.
Cursor2 Color Index2 Register 0
Bit
Type
Reset
state
REG[10Ch]
7
6
5
4
3
2
1
0
Cursor2
Color
Index2 Bit 7
RW
0
Cursor2
Color
Index2 Bit 6
RW
0
Cursor2
Color
Index2 Bit 5
RW
0
Cursor2
Color
Index2 Bit 4
RW
0
Cursor2
Color
Index2 Bit 3
RW
0
Cursor2
Color
Index2 Bit 2
RW
0
Cursor2
Color
Index2 Bit 1
RW
0
Cursor2
Color
Index2 Bit 0
RW
0
Cursor2 Color Index2 Register 1
REG[10Dh]
Bit
7
6
5
4
3
2
1
0
Cursor2
Color
Index2 Bit
14
RW
0
Cursor2
Color
Index2 Bit
13
RW
0
Cursor2
Color
Index2 Bit
12
RW
0
Cursor2
Color
Index2 Bit
11
RW
0
Cursor2
Color
Index2 Bit
10
RW
0
Cursor2
Color
Index2 Bit 9
Cursor2
Color
Index2 Bit 8
Type
Reset
Cursor2
Color
Index2 Bit
15
RW
0
RW
0
RW
0
Solomon Systech
Aug 2005
P 67/159
Rev 1.1
SSD1906
Bit
7
6
5
4
3
2
1
0
state
Solomon Systech
Aug 2005
P 68/159
Rev 1.1
SSD1906
REG[10Dh] bits 7-0
REG[10Ch] bits 7-0
Cursor2 Color Index2 Bits [15:0]
Each cursor pixel is represented by 2 bits. This register stores the color index for pixel
value 10 of Cursor2, refer to Table 20-1.
Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).
For Hardware Cursor operation see Section 20 “Hardware Cursor Mode”.
Cursor2 Color Index3 Register 0
Bit
Type
Reset
state
REG[110h]
7
6
5
4
3
2
1
0
Cursor2
Color
Index3 Bit 7
RW
0
Cursor2
Color
Index3 Bit 6
RW
0
Cursor2
Color
Index3 Bit 5
RW
0
Cursor2
Color
Index3 Bit 4
RW
0
Cursor2
Color
Index3 Bit 3
RW
0
Cursor2
Color
Index3 Bit 2
RW
0
Cursor2
Color
Index3 Bit 1
RW
0
Cursor2
Color
Index3 Bit 0
RW
0
Cursor2 Color Index3 Register 1
Bit
Type
Reset
state
REG[111h]
7
6
5
4
3
2
1
0
Cursor2
Color
Index3 Bit
15
RW
0
Cursor2
Color
Index3 Bit
14
RW
0
Cursor2
Color
Index3 Bit
13
RW
0
Cursor2
Color
Index3 Bit
12
RW
0
Cursor2
Color
Index3 Bit
11
RW
0
Cursor2
Color
Index3 Bit
10
RW
0
Cursor2
Color
Index3 Bit 9
Cursor2
Color
Index3 Bit 8
RW
0
RW
0
REG[111h] bits 7-0
REG[110h] bits 7-0
Cursor2 Color Index3 Bits [15:0]
Each cursor pixel is represented by 2 bits. This register stores the color index for pixel
value 11 of Cursor2, refer to Table 20-1.
Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).
For Hardware Cursor operation, see Section 20 “Hardware Cursor Mode”.
8
MAXIMUM RATINGS
Table 8-1 : Absolute Maximum Ratings
Symbol
Parameter
Rating
IOVDD
VIN
VOUT
TSTG
TSOL
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Solder Temperature/Time
VSS - 0.3 to 4.0
VSS - 0.3 to 5.0
VSS - 0.3 to IOVDD + 0.5
-65 to 150
260 for 10 sec. max at lead
Units
V
V
V
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be
restricted to the limits in the Electrical Characteristics tables or Pin Description section.
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Aug 2005
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Rev 1.1
SSD1906
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields;
however, it is advised that normal precautions are taken to avoid exposure to the high impedance circuit of any voltage
higher than the maximum rated voltages . For correct operation it is recommended that VIN and VOUT be constrained to
the range VSS ≤ (VIN or VOUT) ≤ IOVDD. Reliability of operation is enhanced if unused input is connected to an
appropriate logic voltage level (e.g., either VSS or IOVDD). This device is not radiation protected.
Table 8-2 : Recommended Operating Conditions
Symbol
IOVDD
VIN
TOPR
9
Parameter
Supply Voltage
Input Voltage
Operating Temperature
Condition
VSS = 0V
Min
3.0
VSS
-30
Typ
3.3
Max
3.6
IOVDD
85
25
Units
V
V
°C
DC CHARACTERISTICS
Table 9-1 : Electrical Characteristics for IOVDD = 3.3V typical
Symbol
IDDS
IIZ
IOZ
VOH
Parameter
Quiescent Current
Input Leakage Current
Output Leakage Current
High Level Output Voltage
VOL
Low Level Output Voltage
VIH
VIL
VT+
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
VTVH1
CI
CO
CIO
Low Level Input Voltage
Hysteresis Voltage
Input Pin Capacitance
Output Pin Capacitance
Bi-Directional Pin
Capacitance
Condition
Quiescent Conditions
IOVDD = min
IOH = -8mA (Type 2)
-12mA (Type 3)
IOVDD = min
IOL = 8mA (Type2)
12mA (Type 3)
LVTTL Level, IOVDD = max
LVTTL Level, IOVDD = min
LVTTL Schmitt
LVTTL Schmitt
LVTTL Schmitt
Min
Typ
-1
-1
IOVDD -0.4
Max
120
1
1
Units
µA
µA
µA
V
0.4
V
0.8
V
V
V
IOVDD -0.8
1.1
0.94
0.15
10
10
10
V
V
pF
pF
pF
10 AC CHARACTERISTICS
Conditions:
Solomon Systech
IOVDD = 3.3V ± 10%
TA = -30°C to 85°C
Trise and Tfall for all inputs must be < 5 ns (10% ~ 90%)
CL = 50pF (Bus/CPU Interface)
CL = 0pF (LCD Panel Interface)
Aug 2005
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Rev 1.1
SSD1906
10.1 Clock Timing
10.1.1 Input Clocks
Clock Input Waveform
tPWH
tPWL
90%
VIH
VIL
10%
tf
tr
TOSC
Figure 10-1 : Clock Input Requirements
Table 10-1 : Clock Input Requirements for CLKI
Symbol
fOSC
TOSC
tPWH
tPWL
tf
tr
Parameter
Input Clock Frequency (CLKI)
Input Clock period (CLKI)
Input Clock Pulse Width High (CLKI)
Input Clock Pulse Width Low (CLKI)
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)
Min
Max
66
1/fOSC
5
5
5
5
Units
MHz
ns
ns
ns
ns
ns
Note
Maximum internal requirements for clocks, derived from CLKI, must be considered when determining the
frequency of CLKI. See Section 10.1.2 “Internal Clocks” for internal clock requirements.
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Aug 2005
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Rev 1.1
SSD1906
Table 10-2 : Clock Input Requirements for AUXCLK
Symbol
fOSC
TOSC
tPWH
t PWL
tf
tr
Parameter
Input Clock Frequency (AUXCLK)
Input Clock period (AUXCLK)
Input Clock Pulse Width High
(AUXCLK)
Input Clock Pulse Width Low
(AUXCLK)
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)
Min
Max
66
1/fOSC
5
Units
MHz
ns
ns
5
ns
5
5
ns
ns
Note :
Maximum internal requirements for clocks, derived from AUXCLK, must be considered when determining the
frequency of AUXCLK. See Section 10.1.2 “Internal Clocks” for internal clock requirements.
10.1.2 Internal Clocks
Table 10-3 : Internal Clock Requirements
Symbol
fBCLK
fMCLK
fPCLK
fPWMCLK
Parameter
Bus Clock frequency
Memory Clock frequency
Pixel Clock frequency
PWM Clock frequency
Min
Max
66
55
55
66
Units
MHz
MHz
MHz
MHz
Note :
For further information on internal clocks refer to Section 11 “Clocks”.
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Aug 2005
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Rev 1.1
SSD1906
10.2 CPU Interface Timing
The following section is the CPU interface AC Timing based on IOVDD = 3.3V.
10.2.1 Generic #1 Interface Timing
TCLK
t1
t2
CLK
t3
t4
A[17:1],
M/R#,
t5
t6
CS#
t7
t8
RD0#, RD1#
WE0#, WE1#
t10
t9
WAIT#
t11
t12
D[15:0]
(write)
t13
t14
D[15:0]
(read)
t15
VALID
Figure 10-2 : Generic #1 Interface Timing
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Aug 2005
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Rev 1.1
SSD1906
Table 10-4 : Generic #1 Interface Timing
Symbol
fCLK
TCLK
t1
t2
t3
t4
t5
t6
t7a
t7b
t7c
t7d
t8
t9
t10
t11
t12
t13
t14
t15
Parameter
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
A[17:1], M/R# setup to first CLK rising edge where CS# = 0 and
either RD0#, RD1# = 0 or WE0#, WE1# = 0
A[17:1], M/R# hold from either RD0#, RD1# or WE0#, WE1#
rising edge
CS# setup to CLK rising edge
CS# hold from either RD0#, RD1# or WE0#, WE1# rising edge
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷2
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷3
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷4
RD0#, RD1#, WE0#, WE1# setup to CLK rising edge
Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT#
driven low
Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT#
high impedance
D[15:0] setup to third CLK rising edge where CS# = 0 and
WE0#,WE1#=0 (write cycle)(see note 1)
D[15:0] hold from WAIT# rising edge (write cycle)
RD0#, RD1# falling edge to D[15:0] driven (read cycle)
WAIT# rising edge to D[15:0] valid (read cycle)
RD0#, RD1# rising edge to D[15:0] high impedance (read cycle)
Min
Max
66
1/fCLK
6
6
1
Units
MHz
ns
ns
ns
ns
0
ns
1
1
1
3
15
ns
ns
TCLK
TCLK
TCLK
TCLK
ns
ns
3
13
ns
13
18
23
28
0
0
3
3
ns
14
2
11
ns
ns
ns
ns
1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
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Aug 2005
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SSD1906
10.2.2 Generic #2 Interface Timing (e.g. ISA)
TBUSCLK
t1
t2
BUSCLK
t3
t4
SA[17:0],
M/R#, SBHE#
t5
t6
CS#
t7
t8
MEMR#
MEMW#
t10
t9
IOCHRDY
t11
t12
SD[15:0]
(write)
t13
t14
SD[15:0]
(read)
t15
VALID
Figure 10-3 : Generic #2 Interface Timing
Solomon Systech
Aug 2005
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Rev 1.1
SSD1906
Table 10-5 : Generic #2 Interface Timing
Symbol
fBUSCLK
TBUSCLK
t1
t2
t3
t5
t6
t7a
t7b
t7c
Parameter
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
SA[17:0], M/R#, SBHE# setup to first BUSCLK rising edge
where CS# = 0 and either MEMR# = 0 or MEMW# = 0
SA[17:0], M/R#, SBHE# hold from either MEMR# or MEMW#
rising edge
CS# setup to BUSCLK rising edge
CS# hold from either MEMR# or MEMW# rising edge
MEMR# or MEMW# asserted for MCLK = BCLK
MEMR# or MEMW# asserted for MCLK = BCLK ÷2
MEMR# or MEMW# asserted for MCLK = BCLK ÷3
t7d
MEMR# or MEMW# asserted for MCLK = BCLK ÷4
t8
t9
MEMR# or MEMW# setup to BUSCLK rising edge
Falling edge of either MEMR# or MEMW# to IOCHRDY driven
low
Rising edge of either MEMR# or MEMW# to IOCHRDY high
impedance
SD[15:0] setup to third BUSCLK rising edge where CS# = 0 and
MEMW#=0 (write cycle)(see note1)
SD[15:0] hold from IOCHRDY rising edge (write cycle)
MEMR# falling edge to SD[15:0] driven (read cycle)
IOCHRDY rising edge to SD[15:0] valid (read cycle)
Rising edge of MEMR# to SD[15:0] high impedance (read
cycle)
t4
t10
t11
t12
t13
t14
t15
Min
Max
66
Units
MHz
ns
ns
ns
ns
1/fBUSCLK
6
6
1
0
ns
1
0
ns
ns
13
18
23
TBUSCLK
TBUSCLK
TBUSCLK
28
TBUSCLK
1
3
15
ns
ns
3
13
ns
0
0
3
3
ns
ns
ns
ns
ns
13
2
12
1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
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Aug 2005
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10.2.3 Motorola MC68K #1 Interface Timing (e.g. MC68000)
TCLK
t1
t2
CLK
t4
t3
A[17:1],
M/R#
t5
t6
CS#
t7
t8
t9
AS#
t11
t10
UDS#,
LDS#
t12
t14
t13
R/W#
t15
t16
DTACK#
t17
t18
D[15:0]
(write)
t20
t19
t21
D[15:0]
VALID
(read)
Figure 10-4 : Motorola MC68K #1 Interface Timing
Solomon Systech
Aug 2005
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SSD1906
Table 10-6 : Motorola MC68K #1 Interface Timing
Symbol
fCLK
TCLK
t1
t2
t3
t4
t5
t6
t7a
t7b
t7c
t7d
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
Parameter
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
A[17:1], M/R# setup to first CLK rising edge where CS# = 0,
AS#=0,UDS#=0,and LDS#=0
A[17:1], M/R# hold from AS# rising edge
CS# setup to CLK rising edge while AS#, UDS#/LDS# = 0
CS# hold from AS# rising edge
AS# asserted for MCLK = BCLK
AS# asserted for MCLK = BCLK ÷2
AS# asserted for MCLK = BCLK ÷3
AS# asserted for MCLK = BCLK ÷4
AS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# =0
AS# setup to CLK rising edge
UDS#/LDS# setup to CLK rising edge while CS#, AS#,
UDS#/LDS# = 0
UDS#/LDS# high setup to CLK rising edge
First CLK rising edge where AS#=1 to DTACK# high
impedance
R/W# setup to CLK rising edge before all CS#, AS#, UDS#
and/or LDS# = 0
R/W# hold from AS# rising edge
AS# = 0 and CS# = 0 to DTACK# driven high
AS# rising edge to DTACK# rising edge
D[15:0] valid to third CLK rising edge where CS# = 0, AS# = 0
and either UDS# = 0 or LDS# = 0 (write cycle) (see note 1)
D[15:0] hold from DTACK# falling edge (write cycle)
UDS# = 0 and/or LDS# = 0 to D[15:0] driven (read cycle)
DTACK# falling edge to D[15:0] valid (read cycle)
UDS#, LDS# rising edge to D[15:0] high impedance (read
cycle)
Min
Max
66
1/fCLK
6
6
1
0
1
0
13
18
23
28
1
2
1
2
3
14
1
0
3
4
0
0
3
3
Units
MHz
ns
ns
ns
ns
ns
ns
ns
TCLK
TCLK
TCLK
TCLK
ns
TCLK
ns
ns
ns
ns
13
16
13
2
13
ns
ns
ns
ns
ns
ns
ns
ns
1. t17 is the delay from when data is placed on the bus until the data is latched into the write buffer.
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Aug 2005
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SSD1906
10.2.4 Motorola DragonBall Interface Timing with DTACK# (e.g. MC68EZ328/MC68VZ328)
t1
TCLKO
t2
CLKO
t3
t4
A[17:1]
t5
t7
t6
CSX#
t8
UWE#/LWE#
t9
(write)
t10
OE#
t11
(read)
t12
D[15:0]
t13
Hi-Z
Hi-Z
(write)
t14
D[15:0]
t15
Hi-Z
Hi-Z
VALID
(read)
t16
t17
t18
t19
DTACK#
Figure 10-5 : Motorola DragonBall Interface with DTACK# Timing
Solomon Systech
Aug 2005
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Rev 1.1
SSD1906
Table 10-7 : Motorola DragonBall Interface with DTACK# Timing
Symbol
fCLKO
TCLKO
t1
t2
t3
t4
t5a
t5b
t5c
t5d
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
1
Parameter
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
A[17:1] setup 1st CLKO when CSX# = 0 and
either UWE#/LWE# or OE# =0
A[17:1] hold from CSX# rising edge
CSX# asserted for MCLK = BCLK
CSX# asserted for MCLK = BCLK ÷2
CSX# asserted for MCLK = BCLK ÷3
CSX# asserted for MCLK = BCLK ÷4
CSX# setup to CLKO rising edge
CSX# rising edge to CLKO rising edge
UWE#/LWE# falling edge to CLKO rising
edge
UWE#/LWE# rising edge to CSX# rising
edge
OE# falling edge to CLKO rising edge
OE# hold from CSX# rising edge
D[15:0] setup to 3rd CLKO when CSX#,
UWE#/LWE# asserted (write cycle) (see
note 1)
D[15:0] in hold from CSX# rising
edge(write cycle)
Falling edge of OE# to D[15:0] driven
(read cycle)
CLKO rising edge to D[15:0] output Hi-Z
(read cycle)
CSX# falling edge to DTACK# driven
high
DTACK# falling edge to D[15:0]valid
(read cycle)
CSX# high to DTACK# high
CLKO rising edge to DTACK# Hi-Z
MC68EZ328
Min
Max
MC68VZ328
Min
Max
16
1/fCLKO
28.1
28.1
0
33
1/fCLKO
13.5
13.5
0
0
0
13
18
23
28
13
18
23
28
Units
MHz
ns
ns
ns
ns
ns
TCLKO
TCLKO
TCLKO
TCLKO
0
0
0
0
0
0
ns
ns
ns
0
0
ns
1
0
1
0
0
0
ns
ns
ns
0
0
ns
3
15
3
15
ns
2
12
2
12
ns
3
13
3
13
ns
2
ns
16
6
ns
ns
2
3
1
16
6
3
1
t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
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Aug 2005
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Rev 1.1
SSD1906
10.2.5 Motorola DragonBall Interface Timing without DTACK# (e.g. MC68EZ328/MC68VZ328)
t1
TCLKO
t2
CLKO
t3
t4
A[17:1]
t5
t7
t6
CSX#
t8
UWE#/LWE#
t9
(write)
t10
OE#
t11
(read)
t12
D[15:0]
t13
Hi-Z
Hi-Z
(write)
t14
D[15:0]
t15
t16
Hi-Z
Hi-Z
VALID
(read)
Figure 10-6 : Motorola DragonBall Interface without DTACK# Timing
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Aug 2005
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Rev 1.1
SSD1906
Table 10-8 : Motorola DragonBall Interface without DTACK# Timing
Symbol
fCLKO
TCLKO
t1
t2
t3
t4
t5a
t5b
t5c
t5d
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15a
t15b
t15c
t15d
t16
Parameter
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
A[17:1] setup 1st CLKO when CSX# = 0 and
either UWE#/LWE# or OE# =0
A[16:1] hold from CSX# rising edge
CSX# asserted for MCLK = BCLK
CSX# asserted for MCLK = BCLK ÷2
CSX# asserted for MCLK = BCLK ÷3
CSX# asserted for MCLK = BCLK ÷4
CSX# setup to CLKO rising edge
CSX# rising edge to CLKO rising edge
UWE#/LWE# falling edge to CLKO rising
edge
UWE#/LWE# rising edge to CSX# rising
edge
OE# falling edge to CLKO rising edge
OE# hold from CSX# rising edge
D[15:0] setup to 3rd CLKO when CSX#,
UWE#/LWE# asserted (write cycle) (see
note 1)
D[15:0] hold from CSX# rising edge(write
cycle)
Falling edge of OE# to D[15:0] driven
(read cycle)
1st CLKO rising edge after OE# and
CSX# asserted low to D[15:0] valid for
MCLK = BCLK (read cycle)
1st CLKO rising edge after OE# and
CSX# asserted low to D[15:0] valid for
MCLK = BCLK ÷2 (read cycle)
1st CLKO rising edge after OE# and
CSX# asserted low to D[15:0] valid for
MCLK = BCLK ÷3 (read cycle)
1st CLKO rising edge after OE# and
CSX# asserted low to D[15:0] valid for
MCLK = BCLK ÷4 (read cycle)
CLKO rising edge to D[15:0] output Hi-Z
(read cycle)
MC68EZ328
Min
Max
MC68VZ328
Min
Max
16
1/fCLKO
28.1
28.1
0
33
1/fCLKO
13.6
13.6
0
0
0
13
18
23
28
13
18
23
28
Units
MHz
ns
ns
ns
ns
ns
TCLKO
TCLKO
TCLKO
TCLKO
0
0
0
0
0
0
ns
ns
ns
0
0
ns
1
0
1
0
0
0
ns
ns
ns
0
0
ns
3
2
15
15
ns
13
13
TCLKO
18
18
TCLKO
23
23
TCLKO
28
28
TCLKO
12
ns
12
3
2
Note
1 t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
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Aug 2005
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SSD1906
10.2.6 Hitachi SH-3 Interface Timing (e.g. SH7709A)
TCKIO
t1
t2
CKIO
t4
t3
A[17:1], M/R#,
RD/WR#
t5
t6
BS#
t8
t7
CSn#
t9
t10
t11
WEn#, RD#
t13
t12
Hi-Z
Hi-Z
WAIT#
t14
D[15:0]
t15
Hi-Z
Hi-Z
(write)
t16
D[15:0]
(read)
t17
Hi-Z
Hi-Z
VALID
Figure 10-7 : Hitachi SH-3 Interface Timing
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Aug 2005
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Rev 1.1
SSD1906
Table 10-9 : Hitachi SH-3 Interface Timing
Symbol
fCKIO
TCKIO
t1
t2
t3
t4
t5
t6
t7
t8
t9a
t9b
t9c
t9d
t10
t11
t12
Parameter
Bus Clock frequency
Bus Clock period
Bus Clock pulse width low
Bus Clock pulse width high
A[17:1], M/R#, RD/WR# setup to CKIO
CSn# high setup to CKIO
BS# setup
BS# hold
CSn# setup
A[17:1], M/R#, RD/WR# hold from CS#
RD# or WEn# asserted for MCLK = BCLK (max.
MCLK=50MHz)
RD# or WEn# asserted for MCLK = BCLK ÷2
RD# or WEn# asserted for MCLK = BCLK ÷3
RD# or WEn# asserted for MCLK = BCLK ÷4
Falling edge RD# to D[15:0] driven (read cycle)
Rising edge CSn# to WAIT# high impedance
Falling edge CSn# to WAIT# driven low
Min
t13
t14
t15
t16
t17
CLIO to WAIT# delay
D[15:0] setup to 2nd CKIO after BS# (write cycle) (see note 1)
D[15:0] hold (write cycle)
WAIT# rising edge to D[15:0] valid (read cycle)
Rising edge RD# to D[15:0] high impedance (read cycle)
Max
66
1/fCKIO
9
9
1
1
1
2
1
0
13
3
2
3 TCKIO + 2
4
0
0
18
23
28
12
10
3 TCKIO +
12
18
2
12
3
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCKIO
TCKIO
TCKIO
TCKIO
ns
ns
ns
ns
ns
ns
ns
ns
1. t14 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Note:Minimum three software WAIT states are required.
Solomon Systech
Aug 2005
P 84/159
Rev 1.1
SSD1906
10.2.7 Hitachi SH-4 Interface Timing (e.g. SH7751)
TCKIO
t1
t2
CKIO
t8
t3
A[17:1], M/R#,
RD/WR#
t5
t6
BS#
t4
t7
CSn#
t9
t10
t13
WEn#, RD#
t14
t12
t11
Hi-Z
Hi-Z
RDY#
t15
D[15:0]
t16
Hi-Z
Hi-Z
(write)
t17
D[15:0]
(read)
t18
Hi-Z
Hi-Z
VALID
Figure 10-8 : Hitachi SH-4 Interface Timing
Solomon Systech
Aug 2005
P 85/159
Rev 1.1
SSD1906
Table 10-10 : Hitachi SH-4 Interface Timing
Symbol
fCKIO
TCKIO
t1
t2
t3
t4
t5
t6
t7
t8
t9a
t9b
t9c
t9d
t10
t11
Parameter
Clock frequency
Clock period
Clock pulse width low
Clock pulse width high
A[17:1], M/R#, RD/WR# setup to CKIO
A[17:1], M/R#, RD/WR# hold from CSn#
BS# setup
BS# hold
CSn# setup
CSn# high setup to CKIO
RD# or WEn# asserted for MCLK = BCLK (max.
MCLK=50MHz)
RD# or WEn# asserted for MCLK = BCLK ÷2
RD# or WEn# asserted for MCLK = BCLK ÷3
RD# or WEn# asserted for MCLK = BCLK ÷4
Falling edge RD# to D[15:0] driven (read cycle)
Falling edge CSn# to RDY# driven high
Min
t12
t13
t14
t15
t16
t17
t18
CKIO to RDY# low
CSn# high to RDY# high
Falling edge CKIO to RDY# high impedance
D[15:0] setup to 2 nd CKIO after BS# (write cycle) (see note 1)
D[15:0] hold (write cycle)
RDY# falling edge to D[15:0] valid (read cycle)
Rising edge RD# to D[15:0] high impedance (read cycle)
Max
66
1/fCKIO
6.8
6.8
1
0
1
2
1
2
13
3
3 TCKIO + 3
4
4
4
0
0
18
23
28
12
3 TCKIO +
12
18
14
14
2
12
3
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCKIO
TCKIO
TCKIO
TCKIO
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. t15 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Note:Minimum three software WAIT states are required.
Solomon Systech
Aug 2005
P 86/159
Rev 1.1
SSD1906
10.3 LCD Power Sequencing
10.3.1 Passive/TFT Power-On Sequence
GPO*
t1
Power Saving
Mode Enable**
(REG[A0h] bit 0)
t2
LCD Signals***
*It is recommended to use the general purpose output pin GPO to control the LCD bias power.
**The LCD power-on sequence is activated by programming the Power Saving Mode Enable bit (REG[A0h] bit 0) to 0.
***LCD Signal include: LDATA[17:0], LSHIFT, LLINE, LFRAME, and LDEN.
Figure 10-9 : Passive/TFT Power-On Sequence Timing
Table 10-11 : Passive/TFT Power-On Sequence Timing
Symbol
t1
t2
Parameter
LCD signals active to LCD bias active
Power Saving Mode disabled to LCD signals
active
Min
Note 1
0
Max
Note 1
20
Units
ns
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the
panel connected.
Note:For HR-TFT Power-On/Off sequence information see referenced document of Sharp HR-TFT Panels.
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Aug 2005
P 87/159
Rev 1.1
SSD1906
10.3.2 Passive/TFT Power-Off Sequence
t1
GPO*
Power Saving
Mode Enable**
(REG[A0h] bit 0)
t2
LCD Signals***
*It is recommended to use the general purpose output pin GPO to control the LCD bias power.
**The LCD power-off sequence is activated by programming the Power Saving Mode Enable bit (REG[A0h] bit 0) to 1.
***LCD Signal include: LDATA[17:0], LSHIFT, LLINE, LFRAME, and LDEN.
Figure 10-10 : Passive/TFT Power-Off Sequence Timing
Table 10-12 : Passive/TFT Power-Off Sequence Timing
Symbol
t1
t2
Parameter
LCD bias deactivated active to LCD signals
inactive
Power Saving Mode disabled to LCD signals
low
Min
Note 1
Max
Note 1
Units
0
20
ns
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
connected.
Solomon Systech
Aug 2005
P 88/159
Rev 1.1
SSD1906
10.3.3 Power Saving Status
t1
Power Saving
Mode Enable*
(REG[A0h] bit 0)
t2
Memory Controller
Power Saving Status**
* Power Saving Mode is controlled by the Power Saving Mode Enable bit (REG[A0h] bit 0).
** Memory Controller Power Saving Status is controlled by the Memory Controller Power Saving Status bit (REG[A0h] bit3).
Figure 10-11 : Power Saving Status Timing
Table 10-13 : Power Saving Status Timing
Symbol
t1
t2
Parameter
Power Saving Mode disabled to Memory
Controller Power Saving Status low
Power Saving Mode enabled to Memory
Controller Power Saving Status high
Min
Note 1
Max
Note 1
Units
ns
0
20
MCLK
(note 1)
Rev 1.1
SSD1906
1. For further information on the internal clock MCLK see Section11.1.2, “MCLK”.
Solomon Systech
Aug 2005
P 89/159
10.4 Display Interface
Figure 10-12 : Panel Timing Parameters shows the timing parameters required to drive a flat panel display.
Timing details for each supported panel types are provided in the remainder of this section.
HT
HDPS
HPS
HPW
VDPS
HDP
VPS
VT
VDP
VPW
Figure 10-12 : Panel Timing Parameters
Table 10-14 : Panel Timing Parameter Definition and Register Summary
Symbol
HT
2
HDP
HDPS
HPS
HPW
VT
4
VDP
VDPS
VPS
3
VPW
Description
Horizontal Total
2
Horizontal Display Period
Horizontal Display Period Start Position
LLINE Pulse Start Position
LLINE Pulse Width
Vertical Total
4
Vertical Display Period
Vertical Display Period Start Position
LFRAME Pulse Start Position
LFRAME Pulse Width
Derived From
((REG[12h] bits 6-0) + 1) x 8
((REG[14h] bits 6-0) + 1) x 8
3
Units
5
((REG[17h]bits1-0,REG[16h]bits7-0)+ Offset )
(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1
(REG[20h] bits 6-0) + 1
((REG[19h] bits 1-0, REG[18h] bits 7-0) + 1) x HT
((REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1) x HT
(REG[1Fh] bits 1-0, REG[1Eh] bits 7-0) x HT
(REG[27h] bits 1-0, REG[26h] bits 7-0) x HT +
(REG[31h] bits 1-0, REG[30h] bits 7-0)
((REG[24h] bits 2-0) + 1) x HT + (REG[35h] bits 10, REG[34h] bits 7-0) – (REG[31h] bits 1-0,
REG[30h] bits 7-0)
Ts
1
Ts
1
The following conditions must be fulfilled for all panel timings:
Solomon Systech
Aug 2005
P 90/159
Rev 1.1
SSD1906
1
2
3
4
5
HDPS + HDP < HT
VDPS + VDP < VT
Ts = pixel clock period
The HDP must be a minimum of 32 pixels and can be increased by multiples of 8.
The HDPS parameter contains an offset that depends on the panel type. This offset is the constant in the
equation to describes parameter t14 min in the AC Timing tables for the various panel types.
The VDP must be a minimum of 2 lines.
Offset for STN and CSTN panel = 22, offset for TFT panel = 5.
10.4.1 Generic STN Panel Timing
VT (= 1 Frame)
VPS
VPW
LFRAME
VDPS
VDP
LLINE
MOD (LDEN)
LDATA[17:0]
HT (= 1 Line)
HPS
HPW
LLINE
LSHIFT
1PCLK
MOD (LDEN)
HDPS
HDP
LDATA[17:0]
Figure 10-13 : Generic STN Panel Timing
Solomon Systech
Aug 2005
P 91/159
Rev 1.1
SSD1906
VT
= Vertical Total
= [(REG[19h]bits1-0,REG[18h]bits7-0)+ 1] lines
VPS
= LFRAME Pulse Start Position
= [(REG[27h] bits 1-0, REG[26h] bits 7-0)] x HT + (REG[31h] bits 1-0, REG[30h] bits 7-0) pixels
VPW = LFRAME Pulse Width
= [(REG[24h] bits 2-0) + 1] x HT + (REG[35h] bits 1-0, REG[34h] bits 7-0) – (REG[31h] bits 1-0, REG[30h]
bits 7-0) pixels
VDPS = Vertical Display Period Start Position
= [(REG[1Fh]bits1-0,REG[1Eh]bits7-0)] lines
VDP
= Vertical Display Period
= [(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1] lines
* The VDP must be a minimum of 2 lines
HT
= Horizontal Total
= [((REG[12h] bits 6-0) + 1) x 8] pixels
HPS
= LLINE Pulse Start Position
= [(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1] pixels
HPW = LLINE Pulse Width
= [(REG[20h] bits 6-0) + 1] pixels
HDPS = Horizontal Display Period Start Position
= [(REG[17h]bits1-0,REG[16h]bits7-0)+ 22] pixels
HDP
= Horizontal Display Period
= [((REG[14h] bits 6-0) + 1) x 8] pixels
∗ The HDP must be a minimum of 32 pixels and can be increased by multiples of 8.
*Panel Type Bits (REG[10h] bits 2-0) = 000b (STN)
*LFRAME Pulse Polarity Bit (REG[24h] bit 7) = 1 (active high)
*LLINE Polarity Bit (REG[20h] bit 7) = 1 (active high).
Solomon Systech
Aug 2005
P 92/159
Rev 1.1
SSD1906
10.4.2 Monochrome 4-Bit Panel Timing
VDP
VNDP
LFRAME
LLINE
LDEN (MOD)
LDATA[7:4]
LINE1
LINE2
LINE3
LINE239
LINE240
LINE1
LINE2
LLINE
LDEN (MOD)
HDP
HNDP
LSHIFT
LDATA7
1-1
LDATA6
1-2
1-6
1-318
LDATA5
1-3
1-7
1-319
LDATA4
1-4
1-8
1-320
1-5
1-317
*Diagram drawn with 2 LLINE vertical blank period
Example timing for a 320x240 panel
Figure 10-14 : Monochrome 4-Bit Panel Timing
VDP
= Vertical Display Period
= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT -VDP
= (REG[19h] bits 1:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines
HDP
= Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6:0) + 1) x 8Ts) - (((REG[14h] bits 6:0) + 1) x 8Ts)
Solomon Systech
Aug 2005
P 93/159
Rev 1.1
SSD1906
t1
Sync Timing
t2
LFRAME
t4
t3
LLINE
t5
LDEN (MOD)
Data Timing
LLINE
t6
t8
t7
t9
t10
t11
t14
LSHIFT
t12
LDATA[7:4]
t13
1
2
Figure 10-15 : Monochrome 4-Bit Panel A.C. Timing
Solomon Systech
Aug 2005
P 94/159
Rev 1.1
SSD1906
Table 10-15 : Monochrome 4-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Parameter
LFRAME setup to LLINE falling edge
LFRAME hold from LLINE falling edge
LLINE period
LLINE pulse width
MOD transition to LLINE falling edge
LSHIFT falling edge to LLINE rising edge
LSHIFT falling edge to LLINE falling edge
LLINE falling edge to LSHIFT falling edge
LSHIFT period
LSHIFT pulse width low
LSHIFT pulse width high
LDATA[7:4] setup to LSHIFT falling edge
LDATA[7:4] hold from LSHIFT falling edge
LLINE falling edge to LSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t 6 + t4
t14 + 2
4
2
2
2
2
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
1. Ts = pixel clock period
2. t1 min = (HPS+ HPW) – (REG[31h] bits 1-0, REG[30h] bits 7-0)
3. t2 min = VPW - t1 min
4. t3 min = HT
5. t4 min = HPW
6. t5 min = HT - HPS
if negative add t3 min
7. t6 min = HPS - (HDP + HDPS - 2)
8. t14 min = HDPS - (HPS + t4 min)
if negative add t3 min
Solomon Systech
Aug 2005
P 95/159
Rev 1.1
SSD1906
10.4.3 Monochrome 8-Bit Panel Timing
VDP
VNDP
LFRAME
LLINE
LDEN (MOD)
LDATA[7:0]
LINE1
LINE2
LINE3
LINE479
LINE480
LINE1
LINE2
LLINE
LDEN (MOD)
HDP
HNDP
LSHIFT
LDATA7
1-1
1-9
1-633
LDATA6
1-2
1-10
1-634
LDATA5
1-3
1-11
1-635
LDATA4
1-4
1-12
1-636
LDATA3
1-5
1-13
1-637
LDATA2
1-6
1-14
1-638
LDATA1
1-7
1-15
1-639
LDATA0
1-8
1-16
1-640
*Diagram drawn with 2 LLINE vertical blank period
Example timing for a 640x480 panel
Figure 10-16 : Monochrome 8-Bit Panel Timing
VDP
= Vertical Display Period
= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT-VDP
= (REG[19h] bits 1:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines
HDP
= Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6:0) + 1) x 8Ts) - (((REG[14h] bits 6:0) + 1) x 8Ts)
Solomon Systech
Aug 2005
P 96/159
Rev 1.1
SSD1906
t1
Sync Timing
t2
LFRAME
t4
t3
LLINE
t5
LDEN (MOD)
Data Timing
LLINE
t6
t8
t7
t9
t10
t11
t14
LSHIFT
t12
LDATA[7:0]
t13
1
2
Figure 10-17 : Monochrome 8-Bit Panel A.C. Timing
Solomon Systech
Aug 2005
P 97/159
Rev 1.1
SSD1906
Table 10-16 : Monochrome 8-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Parameter
LFRAME setup to LLINE falling edge
LFRAME hold from LLINE falling edge
LLINE period
LLINE pulse width
MOD transition to LLINE falling edge
LSHIFT falling edge to LLINE rising edge
LSHIFT falling edge to LLINE falling edge
LLINE falling edge to LSHIFT falling edge
LSHIFT period
LSHIFT pulse width low
LSHIFT pulse width high
LDATA[7:0] setup to LSHIFT falling edge
LDATA[7:0] hold from LSHIFT falling edge
LLINE falling edge to LSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t 6 + t4
t14 + 4
8
4
4
4
4
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
1. Ts = pixel clock period
2. t1 min = (HPS+ HPW) – (REG[31h] bits 1-0, REG[30h] bits 7-0)
3. t2 min = VPW - t1 min
4. t3 min = HT
5. t4 min = HPW
6. t5 min = HT - HPS
7. t6 min = HPS - (HDP + HDPS - 4)
if negative add t3 min
8. t14 min = HDPS - (HPS + t4 min)
if negative add t3 min
Solomon Systech
Aug 2005
P 98/159
Rev 1.1
SSD1906
10.4.4 Color 4-Bit Panel Timing
VDP
VNDP
LFRAME
LLINE
LDEN (MOD)
LDATA[7:4]
LINE1
LINE2
LINE3
LINE239
LINE240
LINE1
LINE2
LLINE
LDEN (MOD)
HDP
HNDP
LSHIFT
LDATA7
1-R1
LDATA6
1-G1
1-B2
1-R4
1-R320
LDATA5
1-B1
1-R3
1-G4
1-G320
LDATA4
1-R2
1-G3
1-B4
1-B320
1-G2
1-B3
1-B319
*Diagram drawn with 2 LLINE vertical blank period
Example timing for a 320x240 panel
Figure 10-18 : Color 4-Bit Panel Timing
VDP
= Vertical Display Period
= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT-VDP
= (REG[19h] bits 1:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines
HDP
= Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
(((REG[12h] bits 6:0) + 1) x 8Ts) - (((REG[14h] bits 6:0) + 1) x 8Ts)
Solomon Systech
Aug 2005
P 99/159
Rev 1.1
SSD1906
t1
Sync Timing
t2
LFRAME
t4
t3
LLINE
t5
LDEN (MOD)
Data Timing
LLINE
t6
t8
t7
t9
t10
t11
t14
LSHIFT
t12
LDATA[7:4]
t13
1
2
Figure 10-19 : Color 4-Bit Panel A.C. Timing
Solomon Systech
Aug 2005
P 100/159
Rev 1.1
SSD1906
Table 10-17 : Color 4-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Parameter
LFRAME setup to LLINE falling edge
LFRAME hold from LLINE falling edge
LLINE period
LLINE pulse width
MOD transition to LLINE falling edge
LSHIFT falling edge to LLINE rising edge
LSHIFT falling edge to LLINE falling edge
LLINE falling edge to LSHIFT falling edge
LSHIFT period
LSHIFT pulse width low
LSHIFT pulse width high
LDATA[7:4] setup to LSHIFT falling edge
LDATA[7:4] hold from LSHIFT falling edge
LLINE falling edge to LSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t 6 + t4
t14 + 0.5
2
1
1
1
1
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
1. Ts
= pixel clock period
2. t1 min = (HPS+ HPW) – (REG[31h] bits 1-0, REG[30h] bits 7-0)
3. t2 min = VPW - t1 min
4. t3 min = HT
5. t4 min = HPW
6. t5 min = HT - HPS
7. t6 min = HPS - (HDP + HDPS - 3)
if negative add t3 min
8. t14 min = HDPS - (HPS + t4 min) + 1
if negative add t3 min
Solomon Systech
Aug 2005
P 101/159
Rev 1.1
SSD1906
10.4.5 Color 8-Bit Panel Timing (Format stripe)
VDP
VNDP
LFRAME
LLINE
LDEN (MOD)
LDATA[7:0]
LINE1
LINE2
LINE3
LINE479
LINE480
LINE1
LINE2
LLINE
LDEN (MOD)
HDP
HNDP
LSHIFT
LDATA7
1-R1
LDATA6
1-G1
1-R4
1-B6
1-B638
LDATA5
1-B1
1-G4
1-R7
1-R639
LDATA4
1-R2
1-B4
1-G7
1-G639
LDATA3
1-G2
1-R5 1-B7
1-B639
LDATA2
1-B2
1-G5
1-R8
1-R640
LDATA1
1-R3
1-B5
1-G8
1-G640
LDATA0
1-G3
1-R6
1-B8
1-B640
1-B3
1-G6
1-G638
*Diagram drawn with 2 LLINE vertical blank period
Example timing for a 640X480 panel
Figure 10-20 : Color 8-Bit Panel Timing (Format stripe)
Solomon Systech
Aug 2005
P 102/159
Rev 1.1
SSD1906
VDP
= Vertical Display Period
= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT-VDP
= (REG[19h] bits 1:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines
HDP
= Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6:0) + 1) x 8Ts) - (((REG[14h] bits 6:0) + 1) x 8Ts)
t1
Sync Timing
t2
LFRAME
t4
t3
LLINE
t5
LDEN (MOD)
Data Timing
LLINE
t6
t8
t7
t9
t10
t11
t14
LSHIFT
t12
LDATA[7:0]
t13
1
2
Figure 10-21 : Color 8-Bit Panel A.C. Timing (Format stripe)
Solomon Systech
Aug 2005
P 103/159
Rev 1.1
SSD1906
Table 10-18 : Color 8-Bit Panel A.C. Timing (Format stripe)
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Parameter
LFRAME setup to LLINE falling edge
LFRAME hold from LLINE falling edge
LLINE period
LLINE pulse width
MOD transition to LLINE falling edge
LSHIFT falling edge to LLINE rising edge
LSHIFT falling edge to LLINE falling edge
LLINE falling edge to LSHIFT falling edge
LSHIFT period
LSHIFT pulse width low
LSHIFT pulse width high
LDATA[7:0] setup to LSHIFT falling edge
LDATA[7:0] hold to LSHIFT falling edge
LLINE falling edge to LSHIFT rising edge
Min
note 2
note 3
note 4
note 5
note 6
note 7
t 6 + t4
t14 + 2
2
1
1
1
1
note 8
Typ
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
1. Ts = pixel clock period
2. t1 min = (HPS+ HPW) – (REG[31h] bits 1-0, REG[30h] bits 7-0)
3. t2 min = VPW - t1 min
4. t3 min = HT
5. t4 min = HPW
6. t5 min = t3 min -HPS
7. t6 min = HPS - (HDP + HDPS - 1)
if negative add t3 min
8. t14 min = HDPS - (HPS + t4 min)
if negative add t3 min
Solomon Systech
Aug 2005
P 104/159
Rev 1.1
SSD1906
10.4.6 Generic TFT Panel Timing
VT (= 1 Frame)
VPS
VPW
LFRAME
VDPS
VDP
LLINE
LDEN
LDATA[17:0]
HT (= 1 Line)
HPW
HPS
LLINE
LSHIFT
LDEN
HDPS
HDP
LDATA[17:0]
Figure 10-22 : Generic TFT Panel Timing
VT
VPS
VPW
= Vertical Total
= [(REG[19h] bits 1-0, REG[18h] bits 7-0) + 1] lines
= LFRAME Pulse Start Position
= [(REG[27h] bits 1-0, REG[26h] bits 7-0)] x HT + (REG[31h] bits 1-0, REG[30h] bits 7-0) pixels
= LFRAME Pulse Width
= [(REG[24h]bits2-0)+ 1] x HT + (REG[35h] bits 1-0, REG[34h] bits 7-0) – (REG[31h] bits 1-0, REG[30h]
bits 7-0) pixels
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VDPS = Vertical Display Period Start Position
= [(REG[1Fh]bits1-0,REG[1Eh]bits7-0)] lines
VDP
= Vertical Display Period
= [(REG[1Dh]bits1-0,REG[1Ch]bits7-0)+ 1] lines
* The VDP must be a minimum of 2 lines
HT
= Horizontal Total
= [((REG[12h] bits 6-0) + 1) x 8] pixels
HPS
= LLINE Pulse Start Position
= [(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1] pixels
HPW = LLINE Pulse Width
= [(REG[20h] bits 6-0)+ 1] pixels
HDPS = Horizontal Display Period Start Position
= [(REG[17h] bits 1-0, REG[16h] bits 7-0) + 5] pixels
HDP
= Horizontal Display Period
= [((REG[14h] bits 6-0) + 1) x 8] pixels
∗ The HDP must be a minimum of 32 pixels and can be increased by multiples of 8.
*Panel Type Bits (REG[10h] bits 2-0) = 001 (TFT)
*LLINE Pulse Polarity Bit (REG[24h] bit 7) = 0 (active low)
*LFRAME Polarity Bit (REG[20h] bit 7) = 0 (active low)
10.4.7 9/12/18-Bit TFT Panel Timing
VNDP2
VDP
VNDP1
LFRAME
LLINE
LDATA[11:0]
LINE1
LINE480
LINE480
LDEN
LLINE
HDP
HNDP1
HNDP2
LSHIFT
LDEN
LDATA[11:0]
1-1
1-2
1-640
Note: LDEN is used to indicated the first pixel
Example Timing for 12-bit 640x480 panel
Figure 10-23 : 12-Bit TFT Panel Timing
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Aug 2005
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SSD1906
VDP
= Vertical Display Period
= VDP Lines
VNDP = Vertical Non-Display Period
= VNDP1 + VNDP2
= VT – VDP Lines
VNDP1 = Vertical Non-Display Period 1
= VNDP - VNDP2 Lines
VNDP2 = Vertical Non-Display Period 2
= VDPS - VPS Lines
if negative add VT
HDP
= Horizontal Display Period
= HDP Ts
HNDP = Horizontal Non-Display Period
= HNDP1 + HNDP2
= HT - HDP Ts
HNDP1 = Horizontal Non-Display Period 1
= HDPS - HPS Ts
if negative add HT
HNDP2 = Horizontal Non-Display Period 2
= HPS – (HDP + HDPS) Ts
if negative add HT
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SSD1906
t1
t2
LFRAME
t3
LLINE
t4
LLINE
t5
t8
t7
t6
LDEN
t9
tt10
10
t12
t11
t13
t14
LSHIFT
t15
t16
1
LDATA[11:0]
2
639
640
Figure 10-24 : TFT A.C. Timing
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Table 10-19 : TFT A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
Parameter
LFRAME cycle time
LFRAME pulse width low
LFRAME falling edge to LLINE falling edge phase
difference
LLINE cycle time
LLINE pulse width low
LLINE falling edge to LDEN active
LDEN pulse width
LDEN falling edge to LLINE falling edge
LSHIFT period
LSHIFT pulse width high
LSHIFT pulse width low
LLINE setup to LSHIFT falling edge
LDEN to LSHIFT falling edge setup time
LDEN hold from LSHIFT falling edge
Data setup to LSHIFT falling edge
Data hold from LSHIFT falling edge
1. Ts = pixel clock period
2. t6min = HDPS - HPS
3. t8min = HPS - (HDP + HDPS )
Solomon Systech
Min
VT
VPW
HPS
Typ
HT
HPW
note 2
HDP
note 3
1
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Max
250
Units
Lines
Lines
Ts(note1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
if negative add HT
if negative add HT
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10.4.8 160x160 Sharp HR-TFT Panel Timing (e.g. LQ031B1DDxx)
LFRAME
(SPS)
t1
LLINE
(LP)
t2
t3
LLINE
(LP)
t4
LSHIFT (CLK)
REG[38h] bit 4 = 0
LSHIFT (CLK)
REG[38h] bit 4 = 1
t5 t6
D1
LDATA[17:0]
t7
t9
D2
D3
D159 D160
t8
t10
GPIO3
(SPL)
t11
GPIO1
(CLS)
t12
GPIO0
(PS)
t13
GPIO2
(REV)
Figure 10-25 : 160x160 Sharp HR-TFT Panel Horizontal Timing
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Table 10-20 : 160x160 Sharp HR-TFT Horizontal Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Parameter
LLINE start position
Horizontal total period
LLINE width
LSHIFT period
Data setup to LSHIFT rising edge
Data hold from LSHIFT rising edge
Horizontal display start position
Horizontal display period
LLINE rising edge to GPIO3 rising edge
GPIO3 pulse width
GPIO1(GPIO0) pulse width
GPIO1 rising edge (GPIO0 falling edge) to LLINE rise edge
GPIO2 toggle edge to LLINE rise edge
Min
Typ
13
180
2
1
0.5
0.5
5
160
4
1
136
4
10
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
1. Ts = pixel clock period
2. t1typ = (REG[22h] bits 7-0) + 1
3. t2typ = ((REG[12h] bits 6-0) + 1) x 8
4. t3typ = (REG[20h] bits 6-0) + 1
5. t7typ = ((REG[16h] bits 7-0) + 1) - ((REG[22h] bits 7-0) + 1)
6. t8typ = ((REG[14h] bits 6-0) + 1) x 8
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SSD1906
t1
t2
t3
LDATA[17:0]
LINE1
LINE2
LINE160
t4
LFRAME
(SPS)
GPIO1(CLS)
REG[38h]
bit 0 = 0
t5
t6
GPIO1(CLS)
REG[38h]
bit 0 = 1
GPIO0(PS)
REG[38h]
bit 1 = 0
t7
GPIO0(PS)
REG[38h]
bit 1 = 1
t8
t9
LLINE
(LP)
LSHIFT
(CLK)
t10
GPIO1(CLS)
REG[38h]
bit 0 = 0
GPIO0(PS)
REG[38h]
bit 1 = 1
t11
t12
t13
t14
Figure 10-26 : 160x160 Sharp HR-TFT Panel Vertical Timing
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SSD1906
Table 10-21 : 160x160 Sharp HR-TFT Panel Vertical Timing
Symbol
t1
t2
t3
t4
1
t5
1
t6
2
t7
2
t8
t9
1
t10
1
t11
1
t12
2
t13
2
t14
1.
1
2
Parameter
Vertical total period
Vertical display start position
Vertical display period
FPRAME sync pulse width
LFRAME falling edge to GPIO1 alternate timing start
GPIO1 alternate timing period
LFRAME falling edge to GPIO0 alternate timing start
GPIO0 alternate timing period
GPIO1 first pulse rising edge to LLINE rising edge
GPIO1 first pulse width
GPIO1 first pulse falling edge to second pulse rising edge
GPIO1 second pulse width
GPIO0 falling edge to LLINE rising edge
GPIO0 low pulse width
Min
Typ
203
40
160
2
5
4
40
162
4
48
40
48
4
24
Max
Units
Lines
Lines
Lines
Lines
Lines
Lines
Lines
Lines
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts = pixel clock period
Timing for CLS signal change bit enabled (REG[38h] bit 0 = 0) only
Timing for PS signal change bit enabled (REG[38h] bit 1 = 1) only
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10.4.9 Generic HR-TFT Panel Timing
LFRAME
(SPS)
t1
LLINE
(LP)
t2
t3
LLINE
(LP)
t4
LSHIFT (CLK)
REG[38h] bit 4 = 0
LSHIFT (CLK)
REG[38h] bit 4 = 1
t5 t6
D1
LDATA[17:0]
t7
t9
D2
D3
D319 D320
t8
t10
GPIO3
(SPL)
t11
GPIO1
(CLS)
t12
GPIO0
(PS)
t13
GPIO2
(REV)
Example timing for a 320x240 panel
Figure 10-27 : HR-TFT Panel Horizontal Timing
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SSD1906
Table 10-22 : 320x240 HR-TFT Panel Horizontal Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Parameter
LLINE start position
Horizontal total period
LLINE width
LSHIFT period
Data setup to LSHIFT rising edge
Data hold from LSHIFT rising edge
Horizontal display start position
Horizontal display period
LLINE rising edge to GPIO3 rising edge
GPIO3 pulse width
GPIO1(GPIO0) pulse width
GPIO1 rising edge (GPIO0 falling edge) to LLINE rise edge
GPIO2 toggle edge to LLINE rise edge
Min
Typ
14
400
Max
440
1
1
0.5
0.5
60
320
59
1
353
5
11
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
1. Ts = pixel clock period
2. t1typ = (REG[22h] bits 7-0) + 1
3. t2typ = ((REG[12h] bits 6-0) + 1) x 8
4. t3typ = (REG[20h] bits 6-0) + 1
5. t7typ = ((REG[16h] bits 7-0) + 1) - ((REG[22h] bits 7-0) + 1)
6. t8typ = ((REG[14h] bits 6-0) + 1) x 8
t1
t2
LDATA[17:0]
t3
LINE1
LINE2
LINE240
t4
LFRAME
(SPS)
Example timing for 320x240 panel
Figure 10-28 : HR-TFT Panel Vertical Timing
Table 10-23 : 320x240 HR-TFT Panel Vertical Timing
Symbol
t1
t2
t3
t4
Solomon Systech
Parameter
Vertical total period
Vertical display start position
Vertical display period
Vertical sync pulse width
Min
245
Typ
4
240
2
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Rev 1.1
Max
330
Units
Lines
Lines
Lines
Lines
SSD1906
11 Clocks
The following is a block diagram of the SSD1906’s internal clocks.
CLK MUX
CLKI
CLKI-GEN
BCLK
MCLK
CLKI
MCLK
PCLK1
PWMCLK1
PCLK
STOP CONTROL
STOP CONTROL
PWMCLK
PWMCLK2
AUXCLK
PCLK2
AUXCLK-GEN
Figure 11-1 : Clock Generator Block Diagram
11.1 Clock Descriptions
11.1.1 BCLK
BCLK is an internal clock derived from CLKI. BCLK can be a divided version (÷ 1, ÷ 2, ÷ 3, ÷ 4) of CLKI. CLKI is
typically derived from the host CPU bus clock.
The source clock options for BCLK can be selected from the following table.
Table 11-1 : BCLK Clock Selection
Source Clock Options
CLKI
CLKI ÷ 2
CLKI ÷ 3
CLKI ÷ 4
Solomon Systech
BCLK Selection
CF[7:6] = 00
CF[7:6] = 01
CF[7:6] = 10
CF[7:6] = 11
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Note
For synchronous bus interfaces the BCLK should be set the same as the CPU bus clock (not a divided version of
CLKI) e.g. SH-3, SH-4.
11.1.2 MCLK
The MCLK provides the internal clock required to access the embedded SRAM. The SSD1906 has an efficient
power saving control for clocks ,as they are off when not in use.
Further, reducing the MCLK frequency relative to the BCLK frequency increases the CPU cycle latency and
therefore reduces screen update performance. For a balance between power saving and performance the MCLK
should be configured so it has a high enough frequency setting to provide sufficient screen refresh with acceptable
CPU cycle latency.
The source clock options for MCLK can be selected from the following table.
Table 11-2 : MCLK Clock Selection
Source Clock Options
BCLK
BCLK ÷ 2
BCLK ÷ 3
BCLK ÷ 4
MCLK Selection (REG[04h])
00h
10h
20h
30h
11.1.3 PCLK
The PCLK is the internal clock used to control the LCD panel. The PCLK should be chosen to match the optimum
frame rate of the LCD panel. See Section 13 ”Frame Rate Calculation” for details on the relationship between the
PCLK and frame rate.
Some flexibility is possible in selected the PCLK. Firstly, LCD panels typically have a range of permissible frame
rates. Secondly, it may be possible to choose a higher PCLK frequency and tailor the horizontal and vertical nondisplay periods. This will lower the frame-rate to its optimal value.
The source clock options for PCLK can be selected from the following Table 11-3 : PCLK Clock Selection.
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Table 11-3 : PCLK Clock Selection
Source Clock Options
MCLK
MCLK ÷ 2
MCLK ÷ 3
MCLK ÷ 4
MCLK ÷ 8
BCLK
BCLK ÷ 2
BCLK ÷ 3
BCLK ÷ 4
BCLK ÷ 8
CLKI
CLKI ÷ 2
CLKI ÷ 3
CLKI ÷ 4
CLKI ÷ 8
AUXCLK
AUXCLK ÷ 2
AUXCLK ÷ 3
AUXCLK ÷ 4
AUXCLK ÷ 8
PCLK Selection (REG[05h])
00h
10h
20h
30h
40h
01h
11h
21h
31h
41h
02h
12h
22h
32h
42h
03h
13h
23h
33h
43h
A relationship exists between the frequency of MCLK and PCLK which must be maintained, as detailed in the
following Table 11-4 : Relationship between MCLK and PCLK.
Table 11-4 : Relationship between MCLK and PCLK
Color Depth (bpp)
16
8
4
2
1
MCLK to PCLK Relationship
fMCLK ≥ fPCLK x 2
fMCLK ≥ fPCLK
fMCLK ≥ fPCLK ÷ 2
fMCLK ≥ fPCLK ÷ 4
fMCLK ≥ fPCLK ÷ 8
11.1.4 PWMCLK
The PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel.
The source clock options for PWMCLK can be selected from the following table.
For further information on controlling the PWMCLK see Section 0 “
Note: The SSD1906 provides Pulse Width Modulation output on the pin LPWMOUT, which can be used
to control the LCD panels, supporting PWM control of the back-light inverter.
Table 11-5 : PWMCLK Clock Selection
Source Clock Options
CLKI
AUXCLK
Solomon Systech
PWMCLK Selection REG[B1h] bit 0
0
1
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11.2 Clocks versus Functions
The following Table 11-6 : SSD1906 Internal Clock Requirements, lists the internal clocks required for the following
SSD1906 functions.
Table 11-6 : SSD1906 Internal Clock Requirements
Function
Bus Clock
(BCLK)
Memory Clock
(MCLK)
Pixel Clock
(PCLK)
PWM Clock
(PWMCLK)
Register Read/Write
Memory Read/Write
Look-Up Table Register
Read/Write
Software Power Saving
LCD Output
PWM/CV Output
Required
Required
Required
Not Required
Required
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Required
Required
Required
Not Required
Required
Required
Not Required
Required
Required
Not Required
Not Required
Required
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12 Power Saving Mode
The Power Saving Mode is incorporated into the SSD1906 to accommodate the need for reduced power
consumption in the hand-held device market. This mode is enabled via the Power Saving Mode Enable bit
(REG[A0h] bit 0).
Power Saving Mode powers down the panel and stops display refresh accesses to the display buffer.
Table 12-1 : Power Saving Mode Function Summary
IO Access Possible?
Memory Access Possible?
Software Power Saving
Yes
No1
Normal
Yes
Yes
Look-Up Table Registers Access Possible?
Sequence Controller Running?
Yes
No
Yes
Yes
Display Active?
LCD Interface Outputs
PWMCLK
2
GPIO3:0 Pins configured for HR-TFT
2
GPIO Pins configured as GPIO’s Access Possible ?
No
Forced Low
Stopped
Forced Low
3
Yes
Yes
Active
Active
Active
Yes
Note :
1
When Power Saving mode is enabled the controlled memory is powered down. The status of the controlled
memory is indicated by the Memory Controller Power Saving Status bit (REG[A0h] bit 3). For Power Saving Status
AC timing see Section 10.3.3 “Power Saving Status”.
2
GPIO Pins are configured using the configurations pin CF3 which is latched on the rising edge of RESET#. For
information on CF3 see Table 5-6 : Summary of Power-On/Reset Options.
3
GPIO’s can be accessed, and if configured as outputs, can also be changed.
After reset, the SSD1906 stays in Power Saving Mode. Software must initialize the chip (i.e. program all the
registers) and then clear the Power Saving Mode Enable bit.
13 Frame Rate Calculation
The following formula is used to calculate the display frame rate.
f PCLK
FrameRate =
( HT ) x(VT )
Where:
fPCLK
HT
VT
Solomon Systech
= PCLK frequency (Hz)
= Horizontal Total
= ((REG[12h] bits 6-0) + 1) x 8 Ts
= Vertical Total
= ((REG[19h] bits 1-0, REG[18h] bits 7-0) + 1) Lines
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14 Display Data Formats
The following diagram show the display mode data formats.
1 bpp:
bit 7
bit 0
Byte 0
A0
A1
A2
Byte 1
A8
A9
A10 A11 A12 A13 A 14 A15
Byte 2
A16 A17 A18 A19 A20 A21 A 22 A23
A3
A4
A5
A6
P0 P1 P2 P3 P4 P5 P6 P7
A7
LUT
Pn = RGB value from LUT
Index (An)
Host Address
Display Buffer
2 bpp:
Panel Display
bit 7
bit 0
Byte 0
A0
B0
A1
B1
A2
B2
A3
B3
Byte 1
A4
B4
A5
B5
A6
B6
A7
B7
Byte 2
A8
B8
A9
B9
A10 B10 A 11 B11
P0 P1 P2 P3 P4 P5 P6 P7
LUT
Pn = RGB value from LUT
Index (An, Bn)
Host Address
Display Buffer
4 bpp:
Panel Display
bit 7
bit 0
Byte 0
A0
B0
C0
D0
A1
B1
C1
D1
Byte 1
A2
B2
C2
D2
A3
B3
C3
D3
Byte 2
A4
B4
C4
D4
A5
B5
C5
D5
P0 P1 P2 P3 P4 P5 P6 P7
LUT
Pn = RGB value from LUT
Index (An, Bn, Cn, D n)
Host Address
Display Buffer
8 bpp:
Panel Display
bit 7
bit 0
Byte 0
A0
B0
C0
D0
E0
F0
G0
H0
Byte 1
A1
B1
C1
D1
E1
F1
G1
H1
Byte 2
A2
B2
C2
D2
E2
F2
G2
H2
P0 P1 P2 P3 P4 P5 P6 P7
LUT
Pn = RGB value from LUT Index
(An, Bn, Cn, Dn, En, Fn, Gn, H n)
Host Address
Display Buffer
16 bpp:
Panel Display
Byte 0
bit 7
bit 0
G02 G01 G00 B04 B03 B02 B 01 B00
Byte 1
R04 R03 R02 R01 R00 G05 G04 G03
Byte 2
G12
Byte 3
R14 R13 R12 R11 R10 G15 G14 G13
Host Address
Display Buffer
G11
G10
B14
B13
B12
B 11
P0 P1 P2 P3 P4 P5 P6 P7
Bypasses LUT
Pn = (Rn4-0, Gn5-0, Bn4-0)
B10
Panel Display
Figure 14-1 : 1/2/4/8/16 Bit-Per-Pixel Display Data Memory Organization
Note
1. For 16 bpp format Rn, Gn and Bn represent the red, green, and blue color components.
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15 Look-Up Table Architecture
The following figures show the display data output path only.
Note
When Color Invert is enabled the display color is inverted after the Look-Up Table.
15.1 Monochrome Modes
The green Look-Up Table (LUT) is used for all monochrome modes.
15.1.1 1 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
1 bit-per-pixel data
from Display Buffer
6-bit Gray Data
00
01
Figure 15-1 : 1 Bit-per-pixel Monochrome Mode Data Output Path
15.1.2 2 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
2 bit-per-pixel data
from Display Buffer
6-bit Gray Data
00
01
02
03
Figure 15-2 : 2 Bit-per-pixel Monochrome Mode Data Output Path
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15.1.3 4 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
4 bit-per-pixel data
from Display Buffer
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
6-bit Gray Data
Figure 15-3 : 4 Bit-per-pixel Monochrome Mode Data Output Path
15.1.4 8 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
6-bit Gray Data
8 bit-per-pixel data
from Display Buffer
F8
F9
FA
FB
FC
FD
FE
FF
Figure 15-4 : 8 Bit-per-pixel Monochrome Mode Data Output Path
15.1.5 16 Bit-Per-Pixel Monochrome Mode
The LUT is bypassed and the green data is directly mapped for this color depth– See
Figure 14-1 : 1/2/4/8/16 Bit-Per-Pixel Display Data Memory Organization.
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SSD1906
15.2 Color Modes
15.2.1 1 Bit-Per-Pixel Color
Red Look-Up Table 256x6
00
01
6-bit Red Data
Green Look-Up Table 256x6
1 bit-per-pixel data
from Display Buffer
6-bit Green Data
00
01
Blue Look-Up Table 256x6
6-bit Blue Data
00
01
Figure 15-5 : 1 Bit-Per-Pixel Color Mode Data Output Path
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15.2.2 2 Bit-Per-Pixel Color
Red Look-Up Table 256x6
00
01
02
03
6-bit Red Data
Green Look-Up Table 256x6
2 bit-per-pixel data
from Display Buffer
00
01
02
03
6-bit Green Data
Blue Look-Up Table 256x6
6-bit Blue Data
00
01
02
03
Figure 15-6 : 2 Bit-Per-Pixel Color Mode Data Output Path
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15.2.3 4 Bit-Per-Pixel Color
Red Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
6-bit Red Data
Green Look-Up Table 256x6
4 bit-per-pixel data
from Display Buffer
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
6-bit Green Data
Blue Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
6-bit Blue Data
Figure 15-7 : 4 Bit-Per-Pixel Color Mode Data Output Path
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15.2.4 8 Bit-per-pixel Color Mode
Red Look-Up Table 256x6
00
01
02
03
04
05
06
07
6-bit Red Data
F8
F9
FA
FB
FC
FD
FE
FF
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
6-bit Green Data
8 bit-per-pixel data
from Display Buffer
F8
F9
FA
FB
FC
FD
FE
FF
Blue Look-Up Table 256x6
00
01
02
03
04
05
06
07
6-bit Blue Data
F8
F9
FA
FB
FC
FD
FE
FF
Figure 15-8 : 8 Bit-per-pixel Color Mode Data Output Path
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15.2.5 16 Bit-Per-Pixel Color Mode
The LUT is bypassed at 16 bpp and the color data is directly mapped for this color depth. The color pixel is
arranged as 5-6-5 RGB format. See Figure 14-1 : 1/2/4/8/16 Bit-Per-Pixel Display Data Memory Organization.
16 Big-Endian Bus Interface
16.1 Byte Swapping Bus Data
The display buffer and register architecture of the SSD1906 is inherently little-endian. If configured as bigendian (CF4 = 1 at reset), bus accesses are automatically handled by byte swapping all the read/write
data to/from the internal display buffer and registers.
Bus data byte swapping translates all byte accesses correctly to the SSD1906 register and display buffer
locations. To maintain the correct translation for 16-bit word access, even address bytes must be mapped
to the MSB of the 16-bit word, and odd address bytes to the LSB of the 16-bit word. For example:
Display
Buffer
Address
D[15:8]
D[7:0]
System
Memory
Address
15
0 aa
bb
2 cc
dd
MSB
15
0
CPU Data
Byte Swap
bb
0
aa 0
dd
cc
2
Display
Data
Byte Swap
LSB
System
Memory
(Big-Endian)
aabb ccdd
Display
Buffer
(Little-Endian)
* MSB is assumed to be associated with even address.
* LSB is assumed to be associated with odd address.
Byte write 11h to register address 1Eh ->
Byte write 22h to register address 1Fh ->
Word write 1122h to register address 1Eh->
REG[1Eh] <= 11h
REG[1Fh] <= 22h
REG[1Eh] <= 11h
REG[1Fh] <= 22h
Figure 16-1 : Byte-swapping for 16 Bpp
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Aug 2005
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Rev 1.1
SSD1906
16.1.1 16 Bpp Color Depth
For 16 bpp color depth, the Display Data Byte Swap bit (REG[71h] bit 6) must be set to 1
For 16 bpp color depth, the MSB of the 16-bit pixel data is stored at the even system memory address
location and the LSB of the 16-bit pixel data is stored at the odd system memory address location. Bus
data byte swapping (automatic when the SSD1906 is configured for Big-Endian) causes the 16-bit pixel
data to be stored and byte-swapped in the SSD1906 display buffer. During display refresh this stored data
must be byte-swapped again before it is sent to the display.
16.1.2 1/2/4/8 Bpp Color Depth
For 1/2/4/8 bpp color depth, byte swapping must be performed on the bus data, but not the display data.
For 1/2/4/8 bpp color depth, the Display Data Byte Swap bit (REG[71h] bit 6) must be set to 0.
Display
Buffer
Address
D[15:8]
D[7:0]
15
0 11
15
0
CPU Data
Byte Swap
22
22
0
11 0
System
Memory
Address
11
System
Memory
(Big-Endian)
22
Display
Buffer
(Little-Endian)
* High byte lane (D[15:8]) data (e.g. 11) is associated with even address.
* Low byte lane (D[7:0]) data (e.g. 22) is associated with odd address.
Figure 16-2 : Byte-swapping for 1/2/4/8 Bpp
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Aug 2005
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Rev 1.1
SSD1906
17 Virtual Display Mode
Virtual display is where the image to be viewed is larger than the physical display. This difference can be in the
horizontal, vertical, or both, dimensions. To view the image the display is used as a window into the display
buffer. At any given time only a portion of the image is visible. Panning and scrolling are used to view the full
image. Panning describes the horizontal (side to side) motion of the display area. Scrolling describes the
vertical (up and down) motion of the display area.
The Main Window Display Start Address register specifies the starting address of main window image in the
display buffer. The Main Window Line Address Offset register determines the number of horizontal pixels in
the virtual image. See Figure 17-1 : Main Window inside Virtual Image Area .
240 x 160
Main Window
Panning
Scrolling
320 x 240
Virtual Image Area
Figure 17-1 : Main Window inside Virtual Image Area
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Aug 2005
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SSD1906
18 Display Rotate Mode
Most computer displays are refreshed in landscape orientation – from left to right and top to bottom. Computer
images are stored in the same manner. Display Rotate Mode is designed to rotate the displayed image on a
LCD by 90°, 180°, or 270° in an counter-clockwise direction. The rotation is done in hardware and is
transparent to the user for all display buffer reads and writes. By processing the rotation in hardware, Display
Rotate Mode offers a performance advantage over software rotation of the displayed image.
The image is not actually rotated in the display buffer since there is no address translation during CPU
read/write. The image is rotated during display refresh.
18.1 90° Display Rotate Mode
The following figure shows how the programmer sees a 320x480 rotated image and how the image is being
displayed. The application image is written to the SSD1906 as: A–B–C–D. The display is refreshed by the
SSD1906 as: B-D-A-C.
physical memory
start address
B
320
C
display start address
(panel origin)
A
480
Display
Rotate
Window
D
B
Display
Rotate
Window
A
C
D
480
320
image refreshed by SSD1906
image seen by programmer
= image in display buffer
Figure 18-1 : Relationship Between The Screen Image and the Image Refreshed in 90° Display Rotate
Mode.
18.1.1 Register Programming
Enable 90° Display Rotate Mode
Set Display Rotate Mode Select bits to 01 (REG[71h] bits 1:0 = 01).
Display Start Address
The display refresh circuitry starts at pixel “B”, therefore the Main Window Display Start Address
registers (REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “B”.
To calculate the value of the address of pixel “B” use the following formula (assuming 8bpp color
depth).
Main Window Display Start Address bits 16-0
= ((Image address + (panel height x bpp ÷ 8)) ÷ 4) –1
= ((0 + (320 pixels x 8 bpp ÷ 8)) ÷ 4) – 1
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= 79 (4Fh)
Line Address Offset
The Main Window Line Address Offset register (REG[78h], REG[79h]) is based on the display
width and programmed using the following formula.
Main Window Line Address Offset bits 9-0
= Display width in pixels ÷ (32 ÷ bpp)
= 320 pixels ÷ (32 ÷ 8 bpp)
= 80 (50h)
18.2 180° Display Rotate Mode
The following figure shows how the programmer sees a 480x320 landscape image and how the image is
being displayed. The application image is written to the SSD1906 as: A–B–C–D. The display is refreshed
by the SSD1906 as: D-C-B-A.
physical memory
start address
display start address
(panel origin)
B
D
320
320
B
D
A
C
Display
Rotate
Window
Display
Rotate
Window
C
A
480
480
image refreshed by SSD1906
image seen by programmer
= image in display buffer
Figure 18-2 : Relationship Between The Screen Image and the Image Refreshed in 180° Display Rotate
Mode.
18.2.1 Register Programming
Enable 180° Display Rotate Mode
Set Display Rotate Mode Select bits to 10 (REG[71h] bits 1:0 = 10).
Display Start Address
The display refresh circuitry starts at pixel “D”, therefore the Main Window Display Start Address
registers (REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “D”.
To calculate the value of the address of pixel “D” use the following formula (assumes 8bpp color
depth).
Main Window Display Start Address bits 16-0
= ((Image address + (image width x (panel height – 1) + panel width) x bpp ÷ 8) ÷ 4) –1
= ((0 + (480 pixels x 319 pixels + 480 pixels) x 8 bpp ÷ 8) ÷ 4) – 1
= 38399 (95FFh)
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Aug 2005
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Rev 1.1
SSD1906
Line Address Offset
The Main Window Line Address Offset register (REG[78h], REG[79h]) is based on the display
width and programmed using the following formula.
Main Window Line Address Offset bits 9-0
= Display width in pixels ÷ (32 ÷ bpp)
= 480 pixels ÷ (32 ÷ 8 bpp)
= 120 (78h)
18.3 270° Display Rotate Mode
The following figure shows how the programmer sees a 320x480 rotated image and how the image is
being displayed. The application image is written to the SSD1906 as: A–B–C–D. The display is refreshed
by the SSD1906 as: C-A-D-B.
physical memory
start address
B
Display
Rotate
Window
480
A
C
Display
Rotate
Window
display start address
(panel origin)
D
B
D
C
320
A
480
320
image seen by programmer
image refreshed by SSD1906
= image in display buffer
Figure 18-3 : Relationship Between The Screen Image and the Image Refreshed in 270° Display Rotate
Mode.
18.3.1 Register Programming
Enable 270° Display Rotate Mode
Set Display Rotate Mode Select bits to 11 (REG[71h] bits 1:0 = 11).
Display Start Address
The display refresh circuitry starts at pixel “C”, therefore the Main Window Display Start Address
registers (REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “C”.
To calculate the value of the address of pixel “C” use the following formula (assuming 8bpp color
depth).
Main Window Display Start Address bits 16-0
= (Image address + ((panel width – 1) x image width x bpp ÷ 8) ÷ 4)
= (0 + ((480 pixels – 1) x 320 pixels x 8 bpp ÷ 8) ÷ 4)
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Aug 2005
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Rev 1.1
SSD1906
= 38320 (95B0h)
Line Address Offset
The Main Window Line Address Offset register (REG[78h], REG[79h]) is based on the display
width and programmed using the following formula.
Main Window Line Address Offset bits 9-0
= Display width in pixels ÷ (32 ÷ bpp)
= 320 pixels ÷ (32 ÷ 8 bpp)
= 80 (50h)
19 Floating Window Mode
This mode enables a floating window within the main display window. The floating window can be
positioned anywhere within the virtual display and is controlled through the Floating Window control
registers (REG[7Ch] throughREG[91h]). The floating window retains the same color depth and display
orientation as the main window.
The following diagram shows an example of a floating window within a main window and the registers
used to position it.
Normal Orientation Mode
Floating Window Start Y Position
(REG[89h],REG[88h])
panel’s origin
Floating Window End Y Position
(REG[91h],REG[90h])
Main Window
Floating Window
Floating Window Start X Position
(REG[85h],REG[84h])
Floating Window End X Position
(REG[8Dh],REG[8Ch])
Figure 19-1 : Floating Window with Display Rotate Mode disabled
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Aug 2005
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Rev 1.1
SSD1906
19.1 With Display Rotate Mode Enabled
19.1.1 Display Rotate Mode 90°
panel’s origin
90°° Display Rotate Mode
Floating Window End X Position
(REG[8Dh],REG[8Ch])
Floating Window Start X Position
(REG[85h],REG[84h])
Floating window
Floating Window Start Y Position
(REG[89h],REG[88h])
Floating Window End Y Position
(REG[91h],REG[90h])
Main Window
Figure 19-2 : Floating Window with Display Rotate Mode 90° enabled
19.1.2 Display Rotate Mode 180°
180°° Display Rotate Mode
Floating Window Start X Position
(REG[85h],REG[84h])
Floating Window End X Position
(REG[8Dh],REG[8Ch])
Floating Window
Main Window
Floating Window End Y Position
(REG[91h],REG[90h]) Floating Window Start Y Position
(REG[89h],REG[88h])
panel’s origin
Figure 19-3 : Floating Window with Display Rotate Mode 180° enabled
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Aug 2005
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Rev 1.1
SSD1906
19.1.3 Display Rotate Mode 270°
270°° Display Rotate Mode
Floating Window End Y Position
(REG[91h],REG[90h])
Main Window
Floating Window Start Y Position
(REG[89h],REG[88h])
Floating Window
Floating Window Start X Position
(REG[85h],REG[84h])
Floating Window End X Position
(REG[8Dh],REG[8Ch])
panel’s origin
Figure 19-4 : Floating Window with Display Rotate Mode 270° enabled
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Aug 2005
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SSD1906
20 Hardware Cursor Mode
This mode enables two cursors on the main display window. The cursors can be positioned anywhere within the
display and are controlled through Cursor Mode registers (REG[C0h] through REG[111h]). Cursor support is
available only at 4/8/16-bpp display modes.
Each cursor pixel is 2-bit and the indexing scheme is as follows:
Table 20-1 : Indexing scheme for Hardware Cursor
Value
00
01
10
11
Color of Cursor 1 / Cursor 2
Transparent
(REG[E1h], REG[E0h] / REG[109h], REG[108h])
(REG[E5h], REG[E4h] / REG[10Dh], REG[10Ch])
(REG[E9h], REG[E8h] / REG[111h], REG[110h])
Content of color index 1 register
Content of color index 2 register
Content of color index 3 register
Three 16-bit color index registers (REG[E0h] through REG[E9h] and REG[108h] through REG[111h]) have been
implemented for each cursor. Only the lower portion of the color index register is used in 4/8-bpp display modes.
The LUT is bypassed and the color data is directly mapped for 16-bpp display mode.
4 Bit-per-pixel
15
12
11
8
7
4
3
Don’t Care
0
4-bit Color Index
8 Bit-per-pixel
15
12
11
8
7
Don’t Care
4
3
0
8-bit Color Index
16 Bit-per-pixel (the index registers represents the 16-bit color component)
15
13
Green Component
Bits 2-0
12
8
Blue Component
Bits 4-0
7
3
Red Component
Bits 4-0
2
0
Green Component
Bits 5-3
The display precedence is Cursor1 > Cursor2 > Floating window > Main Window.
Cursor 1
Cursor 2
Floating Window
Main Window
Figure 20-1 : Display Precedence in Hardware Cursor
Note :
The minimum size varies for different color depths and display orientations.
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Aug 2005
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Rev 1.1
SSD1906
The cursors retains the same color depth and display orientation as the main window. The following diagram
shows an example of two cursors within a main window and the registers used to position it.
Cursor1 Position Y
(REG[D5h],REG[D4h])
Cursor2 Position Y
(REG[FDh],REG[FCh])
panel’s origin
Main-Window
Cursor1
Cursor1 Position X
(REG[D1h],REG[D0h])
Cursor2
Cursor2 Position X
(REG[F9h],REG[F8h])
Figure 20-2 : Cursors on the main window
20.1 With Display Rotate Mode Enabled
20.1.1 Display Rotate Mode 90°°
Cursor1 Position X
(REG[D1h],REG[D0h])
Cursor2 Position X
(REG[F9h],REG[F8h])
panel’s origin
Cursor1
Cursor1 Position Y
(REG[D5h],REG[D4h])
Cursor2
Main-Window
Cursor2 Position Y
(REG[FDh],REG[FCh])
Figure 20-3 : Cursors with Display Rotate Mode 90° enabled
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Aug 2005
P 138/159
Rev 1.1
SSD1906
20.1.2 Display Rotate Mode 180°°
Cursor2 Position X
(REG[F9h],REG[F8h])
Cursor1 Position X
(REG[D1h],REG[D0h])
Main-Window
Cursor1
Cursor2
Cursor1 Position Y
(REG[D5h],REG[D4h])
Cursor2 Position Y
(REG[FDh],REG[FCh])
panel’s origin
Figure 20-4 : Cursors with Display Rotate Mode 180° enabled
20.1.3 Display Rotate Mode 270°°
Cursor1 Position Y
(REG[D5h],REG[D4h])
Cursor2 Position Y
(REG[FDh],REG[FCh])
Main-Window
Cursor1
Cursor2
panel’s origin
Cursor1 Position X
(REG[D1h],REG[D0h])
Cursor2 Position X
(REG[F9h],REG[F8h])
Figure 20-5 : Cursors with Display Rotate Mode 270° enabled
20.2 Pixel format (Normal orientation mode)
Assuming the pixel data stores start at address n, where n must be divisible by 4 (i.e. aligned to 32-bit
boundary). In this example, a 16x16 cursor is displayed which each cursor index is defined by x and y
coordinate, C(y,x).
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Aug 2005
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Rev 1.1
SSD1906
20.2.1 4/8/16 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
n+4
6
5
C(0,0)
C(0,4)
C(0,8)
C(0,12)
C(1,0)
4
3
C(0,1)
C(0,5)
C(0,9)
C(0,13)
C(1,1)
2
1
0
C(0,2)
C(0,6)
C(0,10)
C(0,14)
C(1,2)
C(0,3)
C(0,7)
C(0,11)
C(0,15)
C(1,3)
C(15,2)
C(15,6)
C(15,10)
C(15,14)
C(15,3)
C(15,7)
C(15,11)
C(15,15)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
C(15,0)
C(15,4)
C(15,8)
C(15,12)
C(15,1)
C(15,5)
C(15,9)
C(15,13)
20.3 Pixel format (90˚ Display Rotate Mode)
Assuming the pixel data stores start at address n, where n must be divisible by 4 (i.e. aligned to 32-bit
boundary). In this example, a 16x16 cursor is displayed which each cursor index is defined x and y coordinate,
C(y,x).
20.3.1 4 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
6
C(0,8)
C(0,12)
C(1,8)
C(1,12)
5
4
C(0,9)
C(0,13)
C(1,9)
C(1,13)
3
2
1
0
C(0,10)
C(0,14)
C(1,10)
C(1,14)
C(0,11)
C(0,15)
C(1,11)
C(1,15)
C(14,10)
C(14,14)
C(15,10)
C(15,14)
C(0,2)
C(0,6)
C(1,2)
C(1,6)
C(14,11)
C(14,15)
C(15,11)
C(15,15)
C(0,3)
C(0,7)
C(1,3)
C(1,7)
C(14,2)
C(14,6)
C(15,2)
C(15,6)
C(14,3)
C(14,7)
C(15,3)
C(15,7)
.
.
.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
n + 28
n + 29
n + 30
n + 31
n + 32
n + 33
n + 34
n + 35
C(14,8)
C(14,12)
C(15,8)
C(15,12)
C(0,0)
C(0,4)
C(1,0)
C(1,4)
C(14,9)
C(14,13)
C(15,9)
C(15,13)
C(0,1)
C(0,5)
C(1,1)
C(1,5)
.
.
.
Addr.
Addr.
Addr.
Addr.
Solomon Systech
n + 60
n + 61
n + 62
n + 63
C(14,0)
C(14,4)
C(15,0)
C(15,4)
C(14,1)
C(14,5)
C(15,1)
C(15,5)
Aug 2005
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Rev 1.1
SSD1906
Solomon Systech
Aug 2005
P 141/159
Rev 1.1
SSD1906
20.3.2 8 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
6
5
C(0,12)
C(1,12)
C(2,12)
C(3,12)
4
3
C(0,13)
C(1,13)
C(2,13)
C(3,13)
2
1
0
C(0,14)
C(1,14)
C(2,14)
C(3,14)
C(0,15)
C(1,15)
C(2,15)
C(3,15)
C(12,14)
C(13,14)
C(14,14)
C(15,14)
C(0,10)
C(1,10)
C(2,10)
C(3,10)
C(12,15)
C(13,15)
C(14,15)
C(15,15)
C(0,11)
C(1,11)
C(2,11)
C(3,11)
C(12,2)
C(13,2)
C(14,2)
C(15,2)
C(12,3)
C(13,3)
C(14,3)
C(15,3)
.
.
.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
n + 12
n + 13
n + 14
n + 15
n + 16
n + 17
n + 18
n + 19
C(12,12)
C(13,12)
C(14,12)
C(15,12)
C(0,8)
C(1,8)
C(2,8)
C(3,8)
C(12,13)
C(13,13)
C(14,13)
C(15,13)
C(0,9)
C(1,9)
C(2,9)
C(3,9)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
C(12,0)
C(13,0)
C(14,0)
C(15,0)
C(12,1)
C(13,1)
C(14,1)
C(15,1)
20.3.3 16 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n + 10
n + 11
6
C(0,14)
C(2,14)
C(4,14)
C(6,14)
C(8,14)
C(10,14)
C(12,14)
C(14,14)
C(0,12)
C(2,12)
C(4,12)
C(6,12)
5
4
C(0,15)
C(2,15)
C(4,15)
C(6,15)
C(8,15)
C(10,15)
C(12,15)
C(14,15)
C(0,13)
C(2,13)
C(4,13)
C(6,13)
3
2
1
0
C(1,14)
C(3,14)
C(5,14)
C(7,14)
C(9,14)
C(11,14)
C(12,14)
C(15,14)
C(1,12)
C(3,12)
C(5,12)
C(7,12)
C(1,15)
C(3,15)
C(5,15)
C(7,15)
C(9,15)
C(11,15)
C(12,15)
C(15,15)
C(1,13)
C(3,13)
C(5,13)
C(7,13)
C(9,0)
C(11,0)
C(12,0)
C(15,0)
C(9,1)
C(11,1)
C(12,1)
C(15,1)
.
.
.
Addr.
Addr.
Addr.
Addr.
Solomon Systech
n + 60
n + 61
n + 62
n + 63
C(8,0)
C(10,0)
C(12,0)
C(14,0)
C(8,1)
C(10,1)
C(12,1)
C(14,1)
Aug 2005
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Rev 1.1
SSD1906
20.4 Pixel format (180˚ Display Rotate Mode)
Assuming the pixel data stores start at address n, where n must be divisible by 4 (i.e. aligned to 32-bit
boundary). In this example, a 16x16 cursor is displayed which each cursor index is defined by x and y
coordinate, C(y,x).
20.4.1 4 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
n+4
6
5
C(15,8)
C(15,12)
C(15,0)
C(15,4)
C(14,8)
4
C(15,9)
C(15,13)
C(15,1)
C(15,5)
C(14,9)
3
2
1
0
C(15,10)
C(15,14)
C(15,2)
C(15,6)
C(14,10)
C(15,11)
C(15,15)
C(15,3)
C(15,7)
C(14,11)
C(0,10)
C(0,14)
C(0,2)
C(0,6)
C(0,11)
C(0,15)
C(0,3)
C(0,7)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
C(0,8)
C(0,12)
C(0,0)
C(0,4)
C(0,9)
C(0,13)
C(0,1)
C(0,5)
20.4.2 8 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
n+4
6
C(15,12)
C(15,8)
C(15,4)
C(15,0)
C(14,12)
5
4
C(15,13)
C(15,9)
C(15,5)
C(15,1)
C(14,13)
3
2
1
0
C(15,14)
C(15,10)
C(15,6)
C(15,2)
C(14,14)
C(15,15)
C(15,11)
C(15,7)
C(15,3)
C(14,15)
C(0,14)
C(0,10)
C(0,6)
C(0,2)
C(0,15)
C(0,11)
C(0,7)
C(0,3)
.
.
.
Addr.
Addr.
Addr.
Addr.
Solomon Systech
n + 60
n + 61
n + 62
n + 63
C(0,12)
C(0,8)
C(0,4)
C(0,0)
C(0,13)
C(0,9)
C(0,5)
C(0,1)
Aug 2005
P 143/159
Rev 1.1
SSD1906
20.4.3 16 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
n+4
6
5
C(15,14)
C(15,10)
C(15,6)
C(15,2)
C(14,14)
4
3
C(15,15)
C(15,11)
C(15,7)
C(15,3)
C(14,15)
2
1
0
C(15,12)
C(15,8)
C(15,4)
C(15,0)
C(14,12)
C(15,13)
C(15,9)
C(15,5)
C(15,1)
C(14,13)
C(0,12)
C(0,8)
C(0,4)
C(0,0)
C(0,13)
C(0,9)
C(0,5)
C(0,1)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
C(0,14)
C(0,10)
C(0,6)
C(0,2)
C(0,15)
C(0,11)
C(0,7)
C(0,3)
20.5 Pixel format (270˚ Display Rotate Mode)
Assuming the pixel data stores start at address n, where n must be divisible by 4 (i.e. aligned to 32-bit
boundary). In this example, a 16x16 cursor is displayed which each cursor index is defined by x and y
coordinate, C(y,x).
20.5.1 4 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
6
C(15,0)
C(15,4)
C(14,0)
C(14,4)
5
4
C(15,1)
C(15,5)
C(14,1)
C(14,5)
3
2
1
0
C(15,2)
C(15,6)
C(14,2)
C(14,6)
C(15,3)
C(15,7)
C(14,3)
C(14,7)
C(1,2)
C(1,6)
C(0,2)
C(0,6)
C(15,10)
C(15,14)
C(14,10)
C(14,14)
C(1,3)
C(1,7)
C(0,3)
C(0,7)
C(15,11)
C(15,15)
C(14,11)
C(14,15)
C(1,10)
C(1,14)
C(0,10)
C(1,11)
C(1,15)
C(0,11)
.
.
.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
n + 28
n + 29
n + 30
n + 31
n + 32
n + 33
n + 34
n + 35
C(1,0)
C(1,4)
C(0,0)
C(0,4)
C(15,8)
C(15,12)
C(14,8)
C(14,12)
C(1,1)
C(1,5)
C(0,1)
C(0,5)
C(15,9)
C(15,13)
C(14,9)
C(14,13)
.
.
.
Addr. n + 60
Addr. n + 61
Addr. n + 62
Solomon Systech
C(1,8)
C(1,12)
C(0,8)
C(1,9)
C(1,13)
C(0,9)
Aug 2005
P 144/159
Rev 1.1
SSD1906
Addr. n + 63
C(0,12)
C(0,13)
C(0,14)
C(0,15)
20.5.2 8 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
6
5
C(15,0)
C(14,0)
C(13,0)
C(12,0)
4
3
C(15,1)
C(14,1)
C(13,1)
C(12,1)
2
1
0
C(15,2)
C(14,2)
C(13,2)
C(12,2)
C(15,3)
C(14,3)
C(13,3)
C(12,3)
C(3,2)
C(2,2)
C(1,2)
C(0,2)
C(15,6)
C(14,6)
C(13,6)
C(12,6)
C(3,3)
C(2,3)
C(1,3)
C(0,3)
C(15,7)
C(14,7)
C(13,7)
C(12,7)
C(3,14)
C(2,14)
C(1,14)
C(0,14)
C(3,15)
C(2,15)
C(1,15)
C(0,15)
.
.
.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
n + 12
n + 13
n + 14
n + 15
n + 16
n + 17
n + 18
n + 19
C(3,0)
C(2,0)
C(1,0)
C(0,0)
C(15,4)
C(14,4)
C(13,4)
C(12,4)
C(3,1)
C(2,1)
C(1,1)
C(0,1)
C(15,5)
C(14,5)
C(13,5)
C(12,5)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
C(3,12)
C(2,12)
C(1,12)
C(0,12)
C(3,13)
C(2,13)
C(1,13)
C(0,13)
20.5.3 16 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n + 10
n + 11
6
C(15,0)
C(13,0)
C(11,0)
C(9,0)
C(7,0)
C(5,0)
C(3,0)
C(1,0)
C(15,2)
C(13,2)
C(11,2)
C(9,2)
5
4
C(15,1)
C(13,1)
C(11,1)
C(9,1)
C(7,1)
C(5,1)
C(3,1)
C(1,1)
C(15,3)
C(13,3)
C(11,3)
C(9,3)
3
2
1
0
C(14,0)
C(12,0)
C(10,0)
C(8,0)
C(6,0)
C(4,0)
C(2,0)
C(0,0)
C(14,2)
C(12,2)
C(10,2)
C(8,2)
C(14,1)
C(12,1)
C(10,1)
C(8,1)
C(6,1)
C(4,1)
C(2,1)
C(0,1)
C(14,3)
C(12,3)
C(10,3)
C(8,3)
C(6,14)
C(4,14)
C(6,15)
C(4,15)
.
.
.
Addr. n + 60
Addr. n + 61
Solomon Systech
C(7,14)
C(5,14)
C(7,15)
C(5,15)
Aug 2005
P 145/159
Rev 1.1
SSD1906
Addr. n + 62
Addr. n + 63
Solomon Systech
C(3,14)
C(1,14)
C(3,15)
C(1,15)
C(2,14)
C(0,14)
Aug 2005
P 146/159
C(2,15)
C(0,15)
Rev 1.1
SSD1906
21 APPLICATION EXAMPLES
IOVDD
Oscillator
10kΩ
Decoder
M/R#
3.3V
IOVDD
CS#
A[17:1]
D[15:0]
WE0#
WE1#
RD0#
RD1#
WAIT#
WE0#
WE1#
RD0#
RD/WR#
WAIT#
BUSCLK
RESET#
CLKI
RESET#
A0
0.1µF
4.7kΩ
0.1µF
LDATA[7:0]
LFRAME
SSD1906
D[7:0]
LFRAME
LLINE
LSHIFT
LDEN
CF2
CF0
A[17:1]
D[15:0]
CF1
CSn#
0.1µF
0.1µF
LLINE
LSHIFT
MOD
8-Bit
CSTN
LCD
Display
Bias Power
BS#
CF0
A[27:18]
COREVDD
AUXCLK
Generic #1
BUS
GPO
IOVDD
4.7kΩ
10kΩ
10kΩ
Figure 21-1: Typical System Diagram (Generic #1 Bus)
Solomon Systech
Aug 2005
P 147/159
Rev 1.1
SSD1906
Oscillator
IOVDD
Decoder
M/R#
COREVDD
3.3V
CS#
IOVDD
A[17:0]
D[15:0]
WE#
BHE#
RD#
WE0#
WE1#
RD#
WAIT#
WAIT#
0.1µF
0.1µF
LDATA[8:0]
LFRAME
SSD1906
CLKI
RESET#
9-Bit
TFT
Display
D[8:0]
LFRAME
LLINE
LSHIFT
LDEN
LLINE
LSHIFT
LDEN
GPO
CF2
CF0
A[17:0]
D[15:0]
0.1µF
0.1µF
Bias Power
BS#
RD/WR#
CSn#
BUSCLK
RESET#
AUXCLK
10kΩ
CF1
A[27:18]
10kΩ
CF0
Generic #2
BUS
IOVDD
4.7kΩ
4.7kΩ
10kΩ
Figure 21-2 : Typical System Diagram (Generic #2 Bus)
Solomon Systech
Aug 2005
P 148/159
Rev 1.1
SSD1906
Oscillator
IOVDD
IOVDD
A[17:1]
D[15:0]
A0
WE1#
BS#
RD/WR#
WAIT#
CLK
RESET#
CLKI
RESET#
0.1µF
3.3V
CS#
A[17:1]
D[15:0]
LDS#
UDS#
AS#
R/W#
DTACK#
0.1µF
COREVDD
0.1µF
LDATA[17:0]
LFRAME
LLINE
LSHIFT
SSD1906
D[17:0]
SPS
LP
CLK
GPIO0
GPIO1
GPIO2
GPIO3
PS
CLS
REV
SPL
18-Bit
HR-TFT
Display
Bias Power
RD#
WE0#
M/R#
CF2
CF0
Decoder
AUXCLK
Decoder
10kΩ
CF1
A[23:18],
FC0, FC1
10kΩ
CF0
MC68K #1
BUS
GPO
IOVDD
4.7kΩ
10kΩ
4.7kΩ
Figure 21-3 : Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000)
Solomon Systech
Aug 2005
P 149/159
Rev 1.1
SSD1906
Oscillator
IOVDD
AUXCLK
10kΩ
BS#
RD/WR#
CSX#
COREVDD
IOVDD
M/R#
LDATA[11:0]
LSHIFT
A[17:1]
D[15:0]
0.1µF
SSD1906
WE0#
WE1#
RD #
WAIT#
CLKI
RESET#
A0
CF2
CF0
LWE#
UWE#
OE#
DTACK#
CLKO
RESET#
3.3V
0.1µF
CS#
A[17:1]
D[15:0]
0.1µF
0.1µF
4.7kΩ
D[11:0]
LSHIFT
LFRAME
LLINE
LDEN
LFRAME
LLINE
LDEN
12-bit
TFT
Display
Bias Power
Decoder
CF1
A[25:18]
10kΩ
CF0
MC68EZ328/
MC68VZ328
DragonBall
BUS
GPO
IOVDD
4.7kΩ
10kΩ
10kΩ
Figure 21-4 : Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus)
Solomon Systech
Aug 2005
P 150/159
Rev 1.1
SSD1906
Oscillator
CKIO
RESET#
IOVDD
3.3V
CS#
12-Bit
TFT
Display
A[17:1]
D[15:0]
WE0#
WE1#
BS#
RD/WR#
RD#
SSD1906
WAIT#
CLKI
RESET#
A0
4.7kΩ
LDATA[11:0]
LFRAME
LLINE
LSHIFT
LDEN
4.7kΩ
D[11:0]
LFRAME
LLINE
LSHIFT
LDEN
Bias Power
WAIT#
COREVDD
GPO
CF2
CF0
A[17:1]
D[15:0]
WE0#
WE1#
BS#
RD/WR#
RD#
M/R#
CF1
CSn#
Decoder
CF0
A[25:18]
AUXCLK
SH-3
BUS
4.7kΩ
4.7kΩ
Figure 21-5 : Typical System Diagram (Hitachi SH-3 Bus)
Solomon Systech
Aug 2005
P 151/159
Rev 1.1
SSD1906
Oscillator
CKIO
RESET#
IOVDD
3.3V
CS#
18-Bit
TFT
Display
A[17:1]
D[15:0]
WE0#
WE1#
BS#
RD/WR#
RD#
SSD1906
LDATA[17:0]
LFRAME
LLINE
LSHIFT
LDEN
WAIT#
CLKI
RESET#
A0
4.7kΩ
4.7kΩ
D[17:0]
LFRAME
LLINE
LSHIFT
LDEN
Bias Power
RDY#
COREVDD
CF2
CF0
A[17:1]
D[15:0]
WE0#
WE1#
BS#
RD/WR#
RD#
M/R#
CF1
CSn#
Decoder
CF0
A[25:18]
AUXCLK
SH-4
BUS
GPO
4.7kΩ
4.7kΩ
Figure 21-6 : Typical System Diagram (Hitachi SH-4 Bus)
Solomon Systech
Aug 2005
P 152/159
Rev 1.1
SSD1906
22 APPENDIX
22.1 Package Mechanical Drawing for 100 pins TQFP
Solomon Systech
Aug 2005
P 153/159
Rev 1.1
SSD1906
22.2 Package Mechanical Drawing for 100 pins TFBGA
Solomon Systech
Aug 2005
P 154/159
Rev 1.1
SSD1906
Solomon Systech
Aug 2005
P 155/159
Rev 1.1
SSD1906
22.3 Register Table
Table 22-1 : SSD1906 Register Table (1 of 3)
Register
Read-Only Configuration Registers
Pg
REG[01h] Display Buffer Size Register
REG[02h] Configuration Readback Register
REG[03h] Product / Revision Code Register
Clock Configuration Registers
REG[04h] Memory Clock Configuration Register
REG[05h] Pixel Clock Configuration Register
Look-Up Table Registers
REG[08h] Look-Up Table Blue Write Data Register
REG[09h] Look-Up Table Green Write Data Register
REG[0Ah] Look-Up Table Red Write Data Register
REG[0Bh] Look-Up Table Write Address Register
REG[0Ch] Look-Up Table Blue Read Data Register
REG[0Dh] Look-Up Table Green Read Data Register
REG[0Eh] Look-Up Table Red Read Data Register
REG[0Fh] Look-Up Table Read Address Register
Panel Configuration Registers
REG[10h] Panel Type Register
REG[11h] MOD Rate Register
REG[12h] Horizontal Total Register
REG[14h] Horizontal Display Period Register
REG[16h] Horizontal Display Period Start Position Register 0
REG[17h] Horizontal Display Period Start Position Register 1
REG[18h] Vertical Total Register 0
REG[19h] Vertical Total Register 1
REG[1Ch] Vertical Display Period Register 0
REG[1Dh] Vertical Display Period Register 1
REG[1Eh] Vertical Display Period Start Position Register 0
REG[1Fh] Vertical Display Period Start Position Register 1
REG[20h] LLINE Pulse Width Register
REG[22h] LLINE Pulse Start Position Register 0
REG[23h] LLINE Pulse Start Position Register 1
REG[24h] LFRAME Pulse Width Register
REG[26h] LFRAME Pulse Start Position Register 0
REG[27h] LFRAME Pulse Start Position Register 1
REG[30h] LFRAME Pulse Start Offset Register 0
REG[31h] LFRAME Pulse Start Offset Register 1
REG[34h] LFRAME Pulse Stop Offset Register 0
REG[35h] LFRAME Pulse Stop Offset Register 1
REG[38h] HR-TFT Special Output Register
REG[3Ah] GPIO1 Pulse Start Register
REG[3Bh] GPIO1 Pulse Stop Register
REG[3Ch] GPIO0 Pulse Start Register
REG[3Eh] GPIO0 Pulse Stop Register
REG[40h] GPIO2 Pulse Delay Register
REG[45h] STN Color Depth Control Register
REG[50h] Dynamic Dithering Control Register
Display Mode Registers
REG[70h] Display Mode Register
REG[71h] Special Effects Register
20
20
21
21
21
22
23
23
24
24
24
25
25
26
27
27
28
28
28
28
28
29
29
30
30
30
31
31
31
32
32
32
32
33
33
33
34
34
35
35
35
36
37
37
39
Main Window Registers
REG[74h] Main Window Display Start Address Register 0
REG[75h] Main Window Display Start Address Register 1
REG[76h] Main Window Display Start Address Register 2
REG[78h] Main Window Line Address Offset Register 0
REG[79h] Main Window Line Address Offset Register 1
Solomon Systech
Aug 2005
P 156/159
40
40
40
41
41
Rev 1.1
SSD1906
Table 22-2 : SSD1906 Register Table (2 of 3)
Solomon Systech
Register
Floating Window Registers
Pg
REG[7Ch] Floating Window Display Start Address Register 0
REG[7Dh] Floating Window Display Start Address Register 1
REG[7Eh] Floating Window Display Start Address Register 2
REG[80h] Floating Window Line Address Offset Register 0
REG[81h] Floating Window Line Address Offset Register 1
REG[84h] Floating Window Start Position X Register 0
REG[85h] Floating Window Start Position X Register 1
REG[88h] Floating Window Start Position Y Register 0
REG[89h] Floating Window Start Position Y Register 1
REG[8Ch] Floating Window End Position X Register 0
REG[8Dh] Floating Window End Position X Register 1
REG[90h] Floating Window End Position Y Register 0
REG[91h] Floating Window End Position Y Register 1
Miscellaneous Registers
REG[A0h] Power Saving Configuration Register
REG[A2h] Software Reset Register
REG[A4h] Scratch Pad Register 0
REG[A5h] Scratch Pad Register 1
REG[134h] Command Initialization Register
General Purpose IO Pins Registers
REG[A8h] General Purpose IO Pins Configuration Register 0
REG[A9h] General Purpose IO Pins Configuration Register 1
REG[ACh] General Purpose IO Pins Status/Control Register 0
REG[ADh] General Purpose IO Pins Status/Control Register 1
PWM Clock and CV Pulse Configuration Registers
REG[B0h] PWM Clock / CV Pulse Control Register
REG[B1h] PWM Clock / CV Pulse Configuration Register
REG[B2h] CV Pulse Burst Length Register
REG[B3h] LPWMOUT Duty Cycle Register
42
42
42
43
43
43
44
44
45
45
46
46
47
Aug 2005
P 157/159
47
48
48
48
49
49
50
50
51
52
53
54
54
Rev 1.1
SSD1906
Table 22-3 : SSD1906 Register Table (3 of 3)
Solomon Systech
Register
Pg
Cursor Mode Registers
REG[C0h] Cursor Feature Register
REG[C4h] Cursor1 Blink Total Register 0
REG[C5h] Cursor1 Blink Total Register 1
REG[C8h] Cursor1 Blink On Register 0
REG[C9h] Cursor1 Blink On Register 1
REG[CCh] Cursor1 Memory Start Register 0
REG[CDh] Cursor1 Memory Start Register 1
REG[CEh] Cursor1 Memory Start Register 2
REG[D0h] Cursor1 Position X Register 0
REG[D1h] Cursor1 Position X Register 1
REG[D4h] Cursor1 Position Y Register 0
REG[D5h] Cursor1 Position Y Register 1
REG[D8h] Cursor1 Horizontal size Register 0
REG[D9h] Cursor1 Horizontal size Register 1
REG[DCh] Cursor1 Vertical size Register 0
REG[DDh] Cursor1 Vertical size Register 1
REG[E0h] Cursor1 Color Index1 Register 0
REG[E1h] Cursor1 Color Index1 Register 1
REG[E4h] Cursor1 Color Index2 Register 0
REG[E5h] Cursor1 Color Index2 Register 1
REG[E8h] Cursor1 Color Index3 Register 0
REG[E9h] Cursor1 Color Index3 Register 1
REG[ECh] Cursor2 Blink Total Register 0
REG[EDh] Cursor2 Blink Total Register 1
REG[F0h] Cursor2 Blink On Register 0
REG[F1h] Cursor2 Blink On Register 1
REG[F4h] Cursor2 Memory Start Register 0
REG[F5h] Cursor2 Memory Start Register 1
REG[F6h] Cursor2 Memory Start Register 2
REG[F8h] Cursor2 Position X Register 0
REG[F9h] Cursor2 Position X Register 1
REG[FCh] Cursor2 Position Y Register 0
REG[FDh] Cursor2 Position Y Register 1
REG[100h] Cursor2 Horizontal size Register 0
REG[101h] Cursor2 Horizontal size Register 1
REG[104h] Cursor2 Vertical size Register 0
REG[105h] Cursor2 Vertical size Register 1
REG[108h] Cursor2 Color Index1 Register 0
REG[109h] Cursor2 Color Index1 Register 1
REG[10Ch] Cursor2 Color Index2 Register 0
REG[10Dh] Cursor2 Color Index2 Register 1
REG[110h] Cursor2 Color Index3 Register 0
REG[111h] Cursor2 Color Index3 Register 1
55
55
55
56
56
56
56
56
57
57
57
57
58
58
59
59
59
60
60
60
60
62
62
62
62
63
63
63
63
64
64
64
64
65
65
65
65
67
67
67
67
69
69
Aug 2005
P 158/159
Rev 1.1
SSD1906
Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any, and all, liability, including without limitation consequential or incidental
damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each
customer application by the customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others.
Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or
manufacture of the part.
http://www.solomon-systech.com
Solomon Systech
Aug 2005
P 159/159
Rev 1.1
SSD1906