ACCUTEK SSD2123

SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD2123
Product Preview
480 x 272 RGB TFT LCD Driver
Integrated Power Circuit, Gate and Source Driver
This document contains information on a product under development. Solomon Systech reserves the right to change
or discontinue this product without notice.
http://www.solomon-systech.com
Rev 0.30 P 1/66
SSD2123
Jan 2008
Copyright © 2008 Solomon Systech Limited
CONTENTS
1
GENERAL DESCRIPTION ....................................................................................................... 5
2
FEATURES................................................................................................................................... 5
3
ORDERING INFORMATION ................................................................................................... 6
4
BLOCK DIAGRAM .................................................................................................................... 6
5
DIE PAD FLOOR PLAN ............................................................................................................ 7
6
PIN DESCRIPTION .................................................................................................................. 15
7
COMMAND TABLE ................................................................................................................. 20
8
COMMAND DESCRIPTION................................................................................................... 23
9
EXTENDED COMMAND DESCRIPTION............................................................................ 36
10
GAMMA ADJUSTMENT FUNCTION ............................................................................... 41
10.1 STRUCTURE OF GRAYSCALE AMPLIFIER ..............................................................................................................42
10.2 GAMMA ADJUSTMENT REGISTER.........................................................................................................................44
10.2.1 Gradient adjusting register.........................................................................................................................44
10.2.2 Amplitude adjusting register.......................................................................................................................44
10.2.3 Micro adjusting register..............................................................................................................................44
10.3 LADDER RESISTOR / 8 TO 1 SELECTOR .................................................................................................................45
11
BLOCK FUNCTION DESCRIPTION ................................................................................. 50
SERIAL INTERFACE ..........................................................................................................................................................50
Serial Interface – 4-wires (8 bits) ...............................................................................................................................50
Serial Interface – 3-wires (9 bits) ...............................................................................................................................51
Serial Interface – 3-wires (24 bits) .............................................................................................................................52
DATA CONTROL ..............................................................................................................................................................53
BOOSTER AND REGULATOR CIRCUIT ...............................................................................................................................53
SHIFT REGISTER ..............................................................................................................................................................53
DATA LATCHES ...............................................................................................................................................................53
RESET CIRCUIT ................................................................................................................................................................53
12
DC CHARACTERISTICS..................................................................................................... 54
13
AC CHARACTERISTICS..................................................................................................... 55
13.1 DISPLAY SIGNAL OUTPUT TIMING ........................................................................................................................55
13.2 SPI TIMING ..........................................................................................................................................................57
SERIAL PERIPHERAL INTERFACE (SPI) ............................................................................................................................57
13.3 8-BIT SERIAL INTERFACE .....................................................................................................................................63
13.4 24-BIT RGB INTERFACE ......................................................................................................................................64
14
SSD2123Z OUTPUT VOLTAGE RELATIONSHIP .......................................................... 65
SSD2123
Rev 0.30
P 2/66
Jan 2008
Solomon Systech
TABLES
TABLE 3-1 : ORDERING INFORMATION ..................................................................................................................................6
TABLE 5-1: SSD2123 BUMP DIE PAD COORDINATES (BUMP CENTRE) .................................................................................8
TABLE 6-1: POWER SUPPLY PINS .........................................................................................................................................15
TABLE 6-2: INTERFACE LOGIC PINS .....................................................................................................................................17
TABLE 6-3: INTERFACE LOGIC PINS .....................................................................................................................................18
TABLE 6-4: DRIVER OUTPUT PINS .......................................................................................................................................19
TABLE 6-5: MISCELLANEOUS PINS ......................................................................................................................................19
TABLE 7-1: COMMAND TABLE AND POR (POWER ON RESET) VALUES ...............................................................................20
SSD2123
Rev 0.30
P 3/66
Jan 2008
Solomon Systech
FIGURES
FIGURE 4-1 : BLOCK DIAGRAM ..............................................................................................................................................6
FIGURE 5-1 - DIE FLOOR PLAN (BUMP FACE UP) ...................................................................................................................7
FIGURE 8-1: LINE INVERSION AC DRIVER ...........................................................................................................................26
FIGURE 13-1: GATE AND SOURCE OUTPUT TIMING (LINE INVERSION)..................................................................................55
FIGURE 13-2- EXAMPLE OF COLOR FILTER ARRANGEMENT .................................................................................................56
FIGURE 13-3- PIXEL CLOCK TIMING ....................................................................................................................................57
FIGURE 13-4 COLOR MODE CONVERSION TIMING ...............................................................................................................58
FIGURE 13-5 VGH OUTPUT AGAINST SHUT & RESB ........................................................................................................59
FIGURE 13-6 - POWER UP SEQUENCE ..................................................................................................................................60
FIGURE 13-7 - POWER DOWN SEQUENCE .............................................................................................................................61
FIGURE 13-8 - SPI INTERFACE TIMING DIAGRAM & TRANSACTION EXAMPLE ....................................................................62
FIGURE 13-9 – 8-BIT SERIAL INTERFACE TIMING DIAGRAM & TRANSACTION EXAMPLE ....................................................63
FIGURE 13-10 – 24-BIT SERIAL INTERFACE TIMING DIAGRAM & TRANSACTION EXAMPLE ................................................64
FIGURE 14-1- LCD DRIVING VOLTAGE RELATIONSHIP .......................................................................................................65
SSD2123
Rev 0.30
P 4/66
Jan 2008
Solomon Systech
1
GENERAL DESCRIPTION
SSD2123 is an all in one driver that integrated the power circuits, gate driver and source driver into single chip. It
can drive a 16.7M/262k/8 color a-TFT panel with resolution of 480 x 272 RGB.
SSD2123 embeds DC-DC Converter and Voltage generator to provide all necessary voltage required by the driver
with minimum external components. A Common Voltage Generation Circuit is included to drive the TFT-display
counter electrode. The driver supports three separated RGB Gamma settings. An Integrated Gamma Control Circuit
is also included that can be adjusted by software commands to provide maximum flexibility and optimal display
quality.
SSD2123 can be operated down to 1.6V and provide different power save modes. It is suitable for any portable
battery-driven applications requiring long operation period with compact size.
2
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
480 x 272 RGB single chip controller driver IC for 16.7M/262k/8 color amorphous TFT LCD
RGB color filter arrangement at Gate
Power Supply
- VDDIO = 1.6V – 3.6V (I/O Interface)
- VCI = 2.5V – 3.6V (power supply for internal analog circuit)
Output Voltages
- Gate Driver:
ƒ VGH-GND = 6V ~ 18V
ƒ VGL-GND = -6V ~ -15V
ƒ VGH-VGL = 32Vp-p
- Source Driver:
ƒ Source = VSS + 0.1 ~ AVDD - 0.1V
ƒ Typical Source Output Voltage variation: ±30 mV
- VCOM drive:
ƒ VCOMH = 2.5V ~ 6.0V
ƒ VCOML = 0V ~ -3.0V
ƒ VCOM amplitude = 6V (max)
ƒ VCOMH in ~10mV resolution steps
System Interface
- Serial Peripheral Interface (SPI), 3 wire (9bit), 4 wire and SPID 24 bit interface
Video interface
- 24-bit RGB interface (DEN, DOTCLK, HSYNC, VSYNC, RR[7:0], BB[7:0], GG[7:0])
- 18-bit RGB interface (DEN, DOTCLK, HSYNC, VSYNC, RR[7:2], BB[7:2], GG[7:2])
- 8-bit serial RGB interface
- 6-bit serial RGB interface
Support low power consumption:
- Low voltage supply
- Low current sleep mode
- 8-color display mode for power saving
- Charge sharing function for switching circuits
- Software settable for Shut and 8 color modes.
Internal power supply circuit
- Voltage generator
- DC-DC converter up to +18/-12 or +15/-15 (VGH - VGL < 32V)
- AVDD generator of 2x, 2.5x or 3x of VCI
Support separate RGB gamma control
Support line / frame inversion
TFT storage capacitance: Cs on common
Support source and gate scan direction control
Built-in Non Volatile Memory (OTP) for VCOM calibration
SSD2123
Rev 0.30
P 5/66
Jan 2008
Solomon Systech
3
ORDERING INFORMATION
Table 3-1 : Ordering Information
Ordering Part Number
SSD2123Z
4
Package Form
COG
BLOCK DIAGRAM
Figure 4-1 : Block Diagram
G0 to G815
VCOM
S0 to S479
VCORE/VREGC/VDDIO
Source driver
Regulator
Circuit
SHUT
CM
VCI/VCIP
CXN
CXP
C11N
C11P
C12N
C12P
C13N
C13P
C1N
C1P
C2N
C2P
C3N
C3P
Booster
Circuit
Gamma /
Grayscale
Voltage
Generator
Switches Network
Data Latches
Regulator
Circuit
VLCD
Shift Registers
VGH
VGL
Gate Driver
Shift Registers
Data Control
Serial Interface
SSD2123
Rev 0.30
P 6/66
Jan 2008
X400
STYPE[1,0]
REV
BGR
SRGB
RL
VSYNC
HSYNC
DOTCLK
DEN
RR[7:0]
GG[7:0]
BB[7:0]
SDO
SDI
SCL
CS
RES
TB
VSS/VSSRC/
AVSS/VCHS
Solomon Systech
5
DIE PAD FLOOR PLAN
Die Information:
Pin 1627
Pin 1
23820 x 780 μm
304 ± 25μm
15 μm (Typ.)
≤ 2 μm within die
2
50 x 80 μm (IO pad, Pad 1-320)
70 μm
2
50 x 100 μm (Dummy pad, Pad 321322, 1626-1627)
53 μm
2
17 x 100 μm (G/S pad, Pad 323-1625)
18 μm
Pad Pitch 2:
Bump Size 3:
Pad Pitch 3:
Output Pad Pitch:
19
G10
36
G8
G4
G0
100
Dummy
25
G2
100
Dummy
67 18
G6
53
Die Center (0,0)
15
15
y
10
10
x
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
2
Die Size:
Die Thickness:
Bump Height:
Bump Co-planarity:
Bump Size 1:
Pad Pitch 1:
Bump Size 2:
25
25
25
25
Center: (-11785, 25)
2
Size:
75 x 75 μm
25
25
Center: (11785, 25)
2
Size:
75 x 75 μm
50
Pin 320
Pin 321
Rev 0.30
50
Center: (11785, -299)
2
Size:
50 x 50 μm
Figure 5-1 - Die Floor Plan (Bump face up)
* Diagram is not to scale
SSD2123
50
Center: (-11785, -299)
2
Size:
50 x 50 μm
P 7/66
Jan 2008
Solomon Systech
Table 5-1: SSD2123 Bump Die Pad Coordinates (Bump Centre)
Pad #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Signal
X-pos Y-pos Pad # Signal
X-pos
Y-pos Pad #
Signal
X-pos Y-pos Pad #
NC
-11620
-299
65 VGH
-7140
-299
129 C12N
-2660
-299 193
NC
-11550
-299
66 VGH
-7070
-299
130 C12N
-2590
-299 194
NC
-11480
-299
67 VGH
-7000
-299
131 C12N
-2520
-299 195
NC
-11410
-299
68 VGH
-6930
-299
132 C12N
-2450
-299 196
VSS
-11340
-299
69 VGH
-6860
-299
133 C12N
-2380
-299 197
VSS
-11270
-299
70 VCHS
-6790
-299
134 C13P
-2310
-299 198
VLCD255
-11200
-299
71 VCHS
-6720
-299
135 C13P
-2240
-299 199
VLCD255
-11130
-299
72 VCHS
-6650
-299
136 C13P
-2170
-299 200
VLCD255
-11060
-299
73 VCHS
-6580
-299
137 C13P
-2100
-299 201
VLCD255
-10990
-299
74 VCHS
-6510
-299
138 C13N
-2030
-299 202
VSSRC
-10920
-299
75 VCHS
-6440
-299
139 C13N
-1960
-299 203
VSSRC
-10850
-299
76 VCHS
-6370
-299
140 C13N
-1890
-299 204
VCIP
-10780
-299
77 VCHS
-6300
-299
141 C13N
-1820
-299 205
VCIP
-10710
-299
78 VCHS
-6230
-299
142 CXP
-1750
-299 206
TESTA
-10640
-299
79 VCHS
-6160
-299
143 CXP
-1680
-299 207
TESTB
-10570
-299
80 VCHS
-6090
-299
144 CXP
-1610
-299 208
VSS
-10500
-299
81 VCHS
-6020
-299
145 CXP
-1540
-299 209
NC
-10430
-299
82 VCHS
-5950
-299
146 CXN
-1470
-299 210
NC
-10360
-299
83 AVDDJ
-5880
-299
147 CXN
-1400
-299 211
NC
-10290
-299
84 AVDDJ
-5810
-299
148 CXN
-1330
-299 212
NC
-10220
-299
85 AVDDJ
-5740
-299
149 CXN
-1260
-299 213
NC
-10150
-299
86 AVDDJ
-5670
-299
150 VCIM
-1190
-299 214
NC
-10080
-299
87 AVDDG
-5600
-299
151 VCIM
-1120
-299 215
AVSS
-10010
-299
88 AVDDG
-5530
-299
152 VCIM
-1050
-299 216
AVSS
-9940
-299
89 AVDDG
-5460
-299
153 VCIM
-980
-299 217
AVSS
-9870
-299
90 AVDDG
-5390
-299
154 VCOM
-910
-299 218
AVSS
-9800
-299
91 AVDD
-299
155 VCOM
-840
-299 219
-5320
VGL
-9730
-299
92 AVDD
-299
156 VCOM
-770
-299 220
-5250
VGL
-9660
-299
93 AVDD
-299
157 VCOM
-700
-299 221
-5180
VGL
-9590
-299
94 AVDD
-299
158 VCOM
-630
-299 222
-5110
VGL
-9520
-299
95 AVDD
-299
159 VCOM
-560
-299 223
-5040
VGL
-9450
-299
96 AVDD
-299
160 VCOM
-490
-299 224
-4970
VGL
-9380
-299
97 AVDD
-299
161 VCOM
-420
-299 225
-4900
C3P
-9310
-299
98 AVDD
-299
162 CSSRC
-350
-299 226
-4830
C3P
-9240
-299
99 AVDD
-299
163 CSSRC
-280
-299 227
-4760
C3P
-9170
-299
100 C11P
-4690
-299
164 CSSRC
-210
-299 228
C3P
-9100
-299
101 C11P
-4620
-299
165 CSSRC
-140
-299 229
C3P
-9030
-299
102 C11P
-4550
-299
166 CSSRC
-70
-299 230
C3N
-8960
-299
103 C11P
-4480
-299
167 CSSRC
0
-299 231
C3N
-8890
-299
104 C11P
-4410
-299
168 VCHS
70
-299 232
C3N
-8820
-299
105 C11P
-4340
-299
169 VCHS
140
-299 233
C3N
-8750
-299
106 C11N
-4270
-299
170 VCHS
210
-299 234
C3N
-8680
-299
107 C11N
-4200
-299
171 VCHS
280
-299 235
C2P
-8610
-299
108 C11N
-4130
-299
172 VCHS
350
-299 236
C2P
-8540
-299
109 C11N
-4060
-299
173 VCHS
420
-299 237
C2P
-8470
-299
110 C11N
-3990
-299
174 VCOML
490
-299 238
C2P
-8400
-299
111 C11N
-3920
-299
175 VCOML
560
-299 239
C2N
-8330
-299
112 VCI
-3850
-299
176 VCOML
630
-299 240
C2N
-8260
-299
113 VCI
-3780
-299
177 VCOML
700
-299 241
C2N
-8190
-299
114 VCI
-3710
-299
178 VCOML
770
-299 242
C2N
-8120
-299
115 VCI
-3640
-299
179 VCOML
840
-299 243
C1P
-8050
-299
116 VCI
-3570
-299
180 VCOML
910
-299 244
C1P
-7980
-299
117 VCI
-3500
-299
181 VCOML
980
-299 245
C1P
-7910
-299
118 VCI
-3430
-299
182 VCOML
1050
-299 246
C1P
-7840
-299
119 VCI
-3360
-299
183 VCOML
1120
-299 247
C1N
-7770
-299
120 VCI
-3290
-299
184 VCOML
1190
-299 248
C1N
-7700
-299
121 VCI
-3220
-299
185 VCOMH
1260
-299 249
C1N
-7630
-299
122 C12P
-3150
-299
186 VCOMH
1330
-299 250
C1N
-7560
-299
123 C12P
-3080
-299
187 VCOMH
1400
-299 251
VGH
-7490
-299
124 C12P
-3010
-299
188 VCOMH
1470
-299 252
VGH
-7420
-299
125 C12P
-2940
-299
189 VCOMH
1540
-299 253
VGH
-7350
-299
126 C12P
-2870
-299
190 VCOMH
1610
-299 254
VGH
-7280
-299
127 C12P
-2800
-299
191 VCOMH
1680
-299 255
VGH
-7210
-299
128 C12N
-2730
-299
192 VCOMH
1750
-299 256
SSD2123
Rev 0.30
P 8/66
Jan 2008
Signal
VCOMH
VCOMH
VCOMH
NC
AVSS
AVSS
AVSS
AVSS
VSS
NC
NC
NC
NC
NC
NC
VSS
NC
NC
NC
NC
NC
VSS
CSSRC
CSSRC
CSSRC
AVSS
AVSS
VCI
VCI
VCI
VCORE
VCORE
VCORE
VCORE
VREGC
VREGC
VREGC
VREGC
VSS
VSS
VSS
VDDIO
VDDIO
VDDIO
VDDIO
B7
B6
B5
B4
B3
B2
B1
B0
VSS
G7
G6
G5
G4
G3
G2
G1
G0
VSS
R7
X-pos Y-pos
1820
-299
1890
-299
1960
-299
2030
-299
2100
-299
2170
-299
2240
-299
2310
-299
2380
-299
2450
-299
2520
-299
2590
-299
2660
-299
2730
-299
2800
-299
2870
-299
2940
-299
3010
-299
3080
-299
3150
-299
3220
-299
3290
-299
3360
-299
3430
-299
3500
-299
3570
-299
3640
-299
3710
-299
3780
-299
3850
-299
3920
-299
3990
-299
4060
-299
4130
-299
4200
-299
4270
-299
4340
-299
4410
-299
4480
-299
4550
-299
4620
-299
4690
-299
4760
-299
4830
-299
4900
-299
4970
-299
5040
-299
5110
-299
5180
-299
5250
-299
5320
-299
5390
-299
5460
-299
5530
-299
5600
-299
5670
-299
5740
-299
5810
-299
5880
-299
5950
-299
6020
-299
6090
-299
6160
-299
6230
-299
Solomon Systech
Pad #
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
Signal
X-pos Y-pos Pad #
R6
6300
-299
321
R5
6370
-299
322
R4
6440
-299
323
R3
6510
-299
324
R2
6580
-299
325
R1
6650
-299
326
R0
6720
-299
327
VSS
6790
-299
328
DOTCLK
6860
-299
329
DOTCLK
6930
-299
330
VDDIO
7000
-299
331
HSYNC
7070
-299
332
VSS
7140
-299
333
VSYNC
7210
-299
334
VDDIO
7280
-299
335
DEN
7350
-299
336
VSS
7420
-299
337
SDC
7490
-299
338
SDI
7560
-299
339
SCK
7630
-299
340
CSB
7700
-299
341
SDO
7770
-299
342
VDDIO
7840
-299
343
GPI3
7910
-299
344
GPI2
7980
-299
345
GPI1
8050
-299
346
GPI0
8120
-299
347
STYPE1
8190
-299
348
STYPE0
8260
-299
349
CM
8330
-299
350
RESB
8400
-299
351
SPID
8470
-299
352
REV
8540
-299
353
BGR
8610
-299
354
TB
8680
-299
355
RL
8750
-299
356
SHUT
8820
-299
357
GAMAS
8890
-299
358
NC
8960
-299
359
SRGB
9030
-299
360
DENMODE
9100
-299
361
X400
9170
-299
362
VDDIO
9240
-299
363
AVSS
9310
-299
364
AVSS
9380
-299
365
AVSS
9450
-299
366
AVSS
9520
-299
367
VCI
9590
-299
368
VCI
9660
-299
369
VCI
9730
-299
370
VCI
9800
-299
371
NC
9870
-299
372
NC
9940
-299
373
NC
10010
-299
374
NC
10080
-299
375
NC
10150
-299
376
NC
10220
-299
377
NC
10290
-299
378
NC
10360
-299
379
NC
10430
-299
380
NC
10500
-299
381
NC
10570
-299
382
NC
10640
-299
383
NC
10710
-299
384
SSD2123
Rev 0.30
P 9/66
Signal
X-pos
Y-pos Pad #
Signal
NC
11821.5
157
385 G<125>
NC
11768.5
282
386 G<127>
G<1>
11718
157
387 G<129>
G<3>
11700
282
388 G<131>
G<5>
11682
157
389 G<133>
G<7>
11664
282
390 G<135>
G<9>
11646
157
391 G<137>
G<11>
11628
282
392 G<139>
G<13>
11610
157
393 G<141>
G<15>
11592
282
394 G<143>
G<17>
11574
157
395 G<145>
G<19>
11556
282
396 G<147>
G<21>
11538
157
397 G<149>
G<23>
11520
282
398 G<151>
G<25>
11502
157
399 G<153>
G<27>
11484
282
400 G<155>
G<29>
11466
157
401 G<157>
G<31>
11448
282
402 G<159>
G<33>
11430
157
403 G<161>
G<35>
11412
282
404 G<163>
G<37>
11394
157
405 G<165>
G<39>
11376
282
406 G<167>
G<41>
11358
157
407 G<169>
G<43>
11340
282
408 G<171>
G<45>
11322
157
409 G<173>
G<47>
11304
282
410 G<175>
G<49>
11286
157
411 G<177>
G<51>
11268
282
412 G<179>
G<53>
11250
157
413 G<181>
G<55>
11232
282
414 G<183>
G<57>
11214
157
415 G<185>
G<59>
11196
282
416 G<187>
G<61>
11178
157
417 G<189>
G<63>
11160
282
418 G<191>
G<65>
11142
157
419 G<193>
G<67>
11124
282
420 G<195>
G<69>
11106
157
421 G<197>
G<71>
11088
282
422 G<199>
G<73>
11070
157
423 G<201>
G<75>
11052
282
424 G<203>
G<77>
11034
157
425 G<205>
G<79>
11016
282
426 G<207>
G<81>
10998
157
427 G<209>
G<83>
10980
282
428 G<211>
G<85>
10962
157
429 G<213>
G<87>
10944
282
430 G<215>
G<89>
10926
157
431 G<217>
G<91>
10908
282
432 G<219>
G<93>
10890
157
433 G<221>
G<95>
10872
282
434 G<223>
G<97>
10854
157
435 G<225>
G<99>
10836
282
436 G<227>
G<101>
10818
157
437 G<229>
G<103>
10800
282
438 G<231>
G<105>
10782
157
439 G<233>
G<107>
10764
282
440 G<235>
G<109>
10746
157
441 G<237>
G<111>
10728
282
442 G<239>
G<113>
10710
157
443 G<241>
G<115>
10692
282
444 G<243>
G<117>
10674
157
445 G<245>
G<119>
10656
282
446 G<247>
G<121>
10638
157
447 G<249>
G<123>
10620
282
448 G<251>
Jan 2008
X-pos Y-pos Pad #
10602
157 449
10584
282 450
10566
157 451
10548
282 452
10530
157 453
10512
282 454
10494
157 455
10476
282 456
10458
157 457
10440
282 458
10422
157 459
10404
282 460
10386
157 461
10368
282 462
10350
157 463
10332
282 464
10314
157 465
10296
282 466
10278
157 467
10260
282 468
10242
157 469
10224
282 470
10206
157 471
10188
282 472
10170
157 473
10152
282 474
10134
157 475
10116
282 476
10098
157 477
10080
282 478
10062
157 479
10044
282 480
10026
157 481
10008
282 482
9990
157 483
9972
282 484
9954
157 485
9936
282 486
9918
157 487
9900
282 488
9882
157 489
9864
282 490
9846
157 491
9828
282 492
9810
157 493
9792
282 494
9774
157 495
9756
282 496
9738
157 497
9720
282 498
9702
157 499
9684
282 500
9666
157 501
9648
282 502
9630
157 503
9612
282 504
9594
157 505
9576
282 506
9558
157 507
9540
282 508
9522
157 509
9504
282 510
9486
157 511
9468
282 512
Signal
G<253>
G<255>
G<257>
G<259>
G<261>
G<263>
G<265>
G<267>
G<269>
G<271>
G<273>
G<275>
G<277>
G<279>
G<281>
G<283>
G<285>
G<287>
G<289>
G<291>
G<293>
G<295>
G<297>
G<299>
G<301>
G<303>
G<305>
G<307>
G<309>
G<311>
G<313>
G<315>
G<317>
G<319>
G<321>
G<323>
G<325>
G<327>
G<329>
G<331>
G<333>
G<335>
G<337>
G<339>
G<341>
G<343>
G<345>
G<347>
G<349>
G<351>
G<353>
G<355>
G<357>
G<359>
G<361>
G<363>
G<365>
G<367>
G<369>
G<371>
G<373>
G<375>
G<377>
G<379>
X-pos Y-pos
9450
157
9432
282
9414
157
9396
282
9378
157
9360
282
9342
157
9324
282
9306
157
9288
282
9270
157
9252
282
9234
157
9216
282
9198
157
9180
282
9162
157
9144
282
9126
157
9108
282
9090
157
9072
282
9054
157
9036
282
9018
157
9000
282
8982
157
8964
282
8946
157
8928
282
8910
157
8892
282
8874
157
8856
282
8838
157
8820
282
8802
157
8784
282
8766
157
8748
282
8730
157
8712
282
8694
157
8676
282
8658
157
8640
282
8622
157
8604
282
8586
157
8568
282
8550
157
8532
282
8514
157
8496
282
8478
157
8460
282
8442
157
8424
282
8406
157
8388
282
8370
157
8352
282
8334
157
8316
282
Solomon Systech
Pad #
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
Signal
G<381>
G<383>
G<385>
G<387>
G<389>
G<391>
G<393>
G<395>
G<397>
G<399>
G<401>
G<403>
G<405>
G<407>
G<409>
G<411>
G<413>
G<415>
G<417>
G<419>
G<421>
G<423>
G<425>
G<427>
G<429>
G<431>
G<433>
G<435>
G<437>
G<439>
G<441>
G<443>
G<445>
G<447>
G<449>
G<451>
G<453>
G<455>
G<457>
G<459>
G<461>
G<463>
G<465>
G<467>
G<469>
G<471>
G<473>
G<475>
G<477>
G<479>
G<481>
G<483>
G<485>
G<487>
G<489>
G<491>
G<493>
G<495>
G<497>
G<499>
G<501>
G<503>
G<505>
G<507>
G<509>
SSD2123
X-pos Y-pos Pad #
8298
157
578
8280
282
579
8262
157
580
8244
282
581
8226
157
582
8208
282
583
8190
157
584
8172
282
585
8154
157
586
8136
282
587
8118
157
588
8100
282
589
8082
157
590
8064
282
591
8046
157
592
8028
282
593
8010
157
594
7992
282
595
7974
157
596
7956
282
597
7938
157
598
7920
282
599
7902
157
600
7884
282
601
7866
157
602
7848
282
603
7830
157
604
7812
282
605
7794
157
606
7776
282
607
7758
157
608
7740
282
609
7722
157
610
7704
282
611
7686
157
612
7668
282
613
7650
157
614
7632
282
615
7614
157
616
7596
282
617
7578
157
618
7560
282
619
7542
157
620
7524
282
621
7506
157
622
7488
282
623
7470
157
624
7452
282
625
7434
157
626
7416
282
627
7398
157
628
7380
282
629
7362
157
630
7344
282
631
7326
157
632
7308
282
633
7290
157
634
7272
282
635
7254
157
636
7236
282
637
7218
157
638
7200
282
639
7182
157
640
7164
282
641
7146
157
642
Rev 0.30
P 10/66
Signal
X-pos
Y-pos Pad #
Signal
G<511>
7128
282
643 G<641>
G<513>
7110
157
644 G<643>
G<515>
7092
282
645 G<645>
G<517>
7074
157
646 G<647>
G<519>
7056
282
647 G<649>
G<521>
7038
157
648 G<651>
G<523>
7020
282
649 G<653>
G<525>
7002
157
650 G<655>
G<527>
6984
282
651 G<657>
G<529>
6966
157
652 G<659>
G<531>
6948
282
653 G<661>
G<533>
6930
157
654 G<663>
G<535>
6912
282
655 G<665>
G<537>
6894
157
656 G<667>
G<539>
6876
282
657 G<669>
G<541>
6858
157
658 G<671>
G<543>
6840
282
659 G<673>
G<545>
6822
157
660 G<675>
G<547>
6804
282
661 G<677>
G<549>
6786
157
662 G<679>
G<551>
6768
282
663 G<681>
G<553>
6750
157
664 G<683>
G<555>
6732
282
665 G<685>
G<557>
6714
157
666 G<687>
G<559>
6696
282
667 G<689>
G<561>
6678
157
668 G<691>
G<563>
6660
282
669 G<693>
G<565>
6642
157
670 G<695>
G<567>
6624
282
671 G<697>
G<569>
6606
157
672 G<699>
G<571>
6588
282
673 G<701>
G<573>
6570
157
674 G<703>
G<575>
6552
282
675 G<705>
G<577>
6534
157
676 G<707>
G<579>
6516
282
677 G<709>
G<581>
6498
157
678 G<711>
G<583>
6480
282
679 G<713>
G<585>
6462
157
680 G<715>
G<587>
6444
282
681 G<717>
G<589>
6426
157
682 G<719>
G<591>
6408
282
683 G<721>
G<593>
6390
157
684 G<723>
G<595>
6372
282
685 G<725>
G<597>
6354
157
686 G<727>
G<599>
6336
282
687 G<729>
G<601>
6318
157
688 G<731>
G<603>
6300
282
689 G<733>
G<605>
6282
157
690 G<735>
G<607>
6264
282
691 G<737>
G<609>
6246
157
692 G<739>
G<611>
6228
282
693 G<741>
G<613>
6210
157
694 G<743>
G<615>
6192
282
695 G<745>
G<617>
6174
157
696 G<747>
G<619>
6156
282
697 G<749>
G<621>
6138
157
698 G<751>
G<623>
6120
282
699 G<753>
G<625>
6102
157
700 G<755>
G<627>
6084
282
701 G<757>
G<629>
6066
157
702 G<759>
G<631>
6048
282
703 G<761>
G<633>
6030
157
704 G<763>
G<635>
6012
282
705 G<765>
G<637>
5994
157
706 G<767>
G<639>
5976
282
707 G<769>
Jan 2008
X-pos Y-pos Pad #
5958
157 708
5940
282 709
5922
157 710
5904
282 711
5886
157 712
5868
282 713
5850
157 714
5832
282 715
5814
157 716
5796
282 717
5778
157 718
5760
282 719
5742
157 720
5724
282 721
5706
157 722
5688
282 723
5670
157 724
5652
282 725
5634
157 726
5616
282 727
5598
157 728
5580
282 729
5562
157 730
5544
282 731
5526
157 732
5508
282 733
5490
157 734
5472
282 735
5454
157 736
5436
282 737
5418
157 738
5400
282 739
5382
157 740
5364
282 741
5346
157 742
5328
282 743
5310
157 744
5292
282 745
5274
157 746
5256
282 747
5238
157 748
5220
282 749
5202
157 750
5184
282 751
5166
157 752
5148
282 753
5130
157 754
5112
282 755
5094
157 756
5076
282 757
5058
157 758
5040
282 759
5022
157 760
5004
282 761
4986
157 762
4968
282 763
4950
157 764
4932
282 765
4914
157 766
4896
282 767
4878
157 768
4860
282 769
4842
157 770
4824
282 771
4806
157 772
Signal
G<771>
G<773>
G<775>
G<777>
G<779>
G<781>
G<783>
G<785>
G<787>
G<789>
G<791>
G<793>
G<795>
G<797>
G<799>
G<801>
G<803>
G<805>
G<807>
G<809>
G<811>
G<813>
G<815>
DUMMY
DUMMY
DUMMY
S<479>
S<478>
S<477>
S<476>
S<475>
S<474>
S<473>
S<472>
S<471>
S<470>
S<469>
S<468>
S<467>
S<466>
S<465>
S<464>
S<463>
S<462>
S<461>
S<460>
S<459>
S<458>
S<457>
S<456>
S<455>
S<454>
S<453>
S<452>
S<451>
S<450>
S<449>
S<448>
S<447>
S<446>
S<445>
S<444>
S<443>
S<442>
S<441>
X-pos Y-pos
4788
282
4770
157
4752
282
4734
157
4716
282
4698
157
4680
282
4662
157
4644
282
4626
157
4608
282
4590
157
4572
282
4554
157
4536
282
4518
157
4500
282
4482
157
4464
282
4446
157
4428
282
4410
157
4392
282
4374
157
4356
282
4338
157
4320
282
4302
157
4284
282
4266
157
4248
282
4230
157
4212
282
4194
157
4176
282
4158
157
4140
282
4122
157
4104
282
4086
157
4068
282
4050
157
4032
282
4014
157
3996
282
3978
157
3960
282
3942
157
3924
282
3906
157
3888
282
3870
157
3852
282
3834
157
3816
282
3798
157
3780
282
3762
157
3744
282
3726
157
3708
282
3690
157
3672
282
3654
157
3636
282
Solomon Systech
Pad #
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
Signal
S<440>
S<439>
S<438>
S<437>
S<436>
S<435>
S<434>
S<433>
S<432>
S<431>
S<430>
S<429>
S<428>
S<427>
S<426>
S<425>
S<424>
S<423>
S<422>
S<421>
S<420>
S<419>
S<418>
S<417>
S<416>
S<415>
S<414>
S<413>
S<412>
S<411>
S<410>
S<409>
S<408>
S<407>
S<406>
S<405>
S<404>
S<403>
S<402>
S<401>
S<400>
S<399>
S<398>
S<397>
S<396>
S<395>
S<394>
S<393>
S<392>
S<391>
S<390>
S<389>
S<388>
S<387>
S<386>
S<385>
S<384>
S<383>
S<382>
S<381>
S<380>
S<379>
S<378>
S<377>
S<376>
SSD2123
X-pos Y-pos Pad #
3618
157
838
3600
282
839
3582
157
840
3564
282
841
3546
157
842
3528
282
843
3510
157
844
3492
282
845
3474
157
846
3456
282
847
3438
157
848
3420
282
849
3402
157
850
3384
282
851
3366
157
852
3348
282
853
3330
157
854
3312
282
855
3294
157
856
3276
282
857
3258
157
858
3240
282
859
3222
157
860
3204
282
861
3186
157
862
3168
282
863
3150
157
864
3132
282
865
3114
157
866
3096
282
867
3078
157
868
3060
282
869
3042
157
870
3024
282
871
3006
157
872
2988
282
873
2970
157
874
2952
282
875
2934
157
876
2916
282
877
2898
157
878
2880
282
879
2862
157
880
2844
282
881
2826
157
882
2808
282
883
2790
157
884
2772
282
885
2754
157
886
2736
282
887
2718
157
888
2700
282
889
2682
157
890
2664
282
891
2646
157
892
2628
282
893
2610
157
894
2592
282
895
2574
157
896
2556
282
897
2538
157
898
2520
282
899
2502
157
900
2484
282
901
2466
157
902
Rev 0.30
P 11/66
Signal
X-pos
Y-pos Pad #
Signal
S<375>
2448
282
903 S<310>
S<374>
2430
157
904 S<309>
S<373>
2412
282
905 S<308>
S<372>
2394
157
906 S<307>
S<371>
2376
282
907 S<306>
S<370>
2358
157
908 S<305>
S<369>
2340
282
909 S<304>
S<368>
2322
157
910 S<303>
S<367>
2304
282
911 S<302>
S<366>
2286
157
912 S<301>
S<365>
2268
282
913 S<300>
S<364>
2250
157
914 S<299>
S<363>
2232
282
915 S<298>
S<362>
2214
157
916 S<297>
S<361>
2196
282
917 S<296>
S<360>
2178
157
918 S<295>
S<359>
2160
282
919 S<294>
S<358>
2142
157
920 S<293>
S<357>
2124
282
921 S<292>
S<356>
2106
157
922 S<291>
S<355>
2088
282
923 S<290>
S<354>
2070
157
924 S<289>
S<353>
2052
282
925 S<288>
S<352>
2034
157
926 S<287>
S<351>
2016
282
927 S<286>
S<350>
1998
157
928 S<285>
S<349>
1980
282
929 S<284>
S<348>
1962
157
930 S<283>
S<347>
1944
282
931 S<282>
S<346>
1926
157
932 S<281>
S<345>
1908
282
933 S<280>
S<344>
1890
157
934 S<279>
S<343>
1872
282
935 S<278>
S<342>
1854
157
936 S<277>
S<341>
1836
282
937 S<276>
S<340>
1818
157
938 S<275>
S<339>
1800
282
939 S<274>
S<338>
1782
157
940 S<273>
S<337>
1764
282
941 S<272>
S<336>
1746
157
942 S<271>
S<335>
1728
282
943 S<270>
S<334>
1710
157
944 S<269>
S<333>
1692
282
945 S<268>
S<332>
1674
157
946 S<267>
S<331>
1656
282
947 S<266>
S<330>
1638
157
948 S<265>
S<329>
1620
282
949 S<264>
S<328>
1602
157
950 S<263>
S<327>
1584
282
951 S<262>
S<326>
1566
157
952 S<261>
S<325>
1548
282
953 S<260>
S<324>
1530
157
954 S<259>
S<323>
1512
282
955 S<258>
S<322>
1494
157
956 S<257>
S<321>
1476
282
957 S<256>
S<320>
1458
157
958 S<255>
S<319>
1440
282
959 S<254>
S<318>
1422
157
960 S<253>
S<317>
1404
282
961 S<252>
S<316>
1386
157
962 S<251>
S<315>
1368
282
963 S<250>
S<314>
1350
157
964 S<249>
S<313>
1332
282
965 S<248>
S<312>
1314
157
966 S<247>
S<311>
1296
282
967 S<246>
Jan 2008
X-pos Y-pos
1278
157
1260
282
1242
157
1224
282
1206
157
1188
282
1170
157
1152
282
1134
157
1116
282
1098
157
1080
282
1062
157
1044
282
1026
157
1008
282
990
157
972
282
954
157
936
282
918
157
900
282
882
157
864
282
846
157
828
282
810
157
792
282
774
157
756
282
738
157
720
282
702
157
684
282
666
157
648
282
630
157
612
282
594
157
576
282
558
157
540
282
522
157
504
282
486
157
468
282
450
157
432
282
414
157
396
282
378
157
360
282
342
157
324
282
306
157
288
282
270
157
252
282
234
157
216
282
198
157
180
282
162
157
144
282
126
157
Pad #
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
Signal
S<245>
S<244>
S<243>
S<242>
S<241>
S<240>
DUMMY
S<239>
S<238>
S<237>
S<236>
S<235>
S<234>
S<233>
S<232>
S<231>
S<230>
S<229>
S<228>
S<227>
S<226>
S<225>
S<224>
S<223>
S<222>
S<221>
S<220>
S<219>
S<218>
S<217>
S<216>
S<215>
S<214>
S<213>
S<212>
S<211>
S<210>
S<209>
S<208>
S<207>
S<206>
S<205>
S<204>
S<203>
S<202>
S<201>
S<200>
S<199>
S<198>
S<197>
S<196>
S<195>
S<194>
S<193>
S<192>
S<191>
S<190>
S<189>
S<188>
S<187>
S<186>
S<185>
S<184>
S<183>
S<182>
X-pos Y-pos
108
282
90
157
72
282
54
157
36
282
18
157
0
282
-18
157
-36
282
-54
157
-72
282
-90
157
-108
282
-126
157
-144
282
-162
157
-180
282
-198
157
-216
282
-234
157
-252
282
-270
157
-288
282
-306
157
-324
282
-342
157
-360
282
-378
157
-396
282
-414
157
-432
282
-450
157
-468
282
-486
157
-504
282
-522
157
-540
282
-558
157
-576
282
-594
157
-612
282
-630
157
-648
282
-666
157
-684
282
-702
157
-720
282
-738
157
-756
282
-774
157
-792
282
-810
157
-828
282
-846
157
-864
282
-882
157
-900
282
-918
157
-936
282
-954
157
-972
282
-990
157
-1008
282
-1026
157
-1044
282
Solomon Systech
Pad #
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
Signal
S<181>
S<180>
S<179>
S<178>
S<177>
S<176>
S<175>
S<174>
S<173>
S<172>
S<171>
S<170>
S<169>
S<168>
S<167>
S<166>
S<165>
S<164>
S<163>
S<162>
S<161>
S<160>
S<159>
S<158>
S<157>
S<156>
S<155>
S<154>
S<153>
S<152>
S<151>
S<150>
S<149>
S<148>
S<147>
S<146>
S<145>
S<144>
S<143>
S<142>
S<141>
S<140>
S<139>
S<138>
S<137>
S<136>
S<135>
S<134>
S<133>
S<132>
S<131>
S<130>
S<129>
S<128>
S<127>
S<126>
S<125>
S<124>
S<123>
S<122>
S<121>
S<120>
S<119>
S<118>
S<117>
SSD2123
X-pos Y-pos Pad #
-1062
157 1098
-1080
282 1099
-1098
157 1100
-1116
282 1101
-1134
157 1102
-1152
282 1103
-1170
157 1104
-1188
282 1105
-1206
157 1106
-1224
282 1107
-1242
157 1108
-1260
282 1109
-1278
157 1110
-1296
282 1111
-1314
157 1112
-1332
282 1113
-1350
157 1114
-1368
282 1115
-1386
157 1116
-1404
282 1117
-1422
157 1118
-1440
282 1119
-1458
157 1120
-1476
282 1121
-1494
157 1122
-1512
282 1123
-1530
157 1124
-1548
282 1125
-1566
157 1126
-1584
282 1127
-1602
157 1128
-1620
282 1129
-1638
157 1130
-1656
282 1131
-1674
157 1132
-1692
282 1133
-1710
157 1134
-1728
282 1135
-1746
157 1136
-1764
282 1137
-1782
157 1138
-1800
282 1139
-1818
157 1140
-1836
282 1141
-1854
157 1142
-1872
282 1143
-1890
157 1144
-1908
282 1145
-1926
157 1146
-1944
282 1147
-1962
157 1148
-1980
282 1149
-1998
157 1150
-2016
282 1151
-2034
157 1152
-2052
282 1153
-2070
157 1154
-2088
282 1155
-2106
157 1156
-2124
282 1157
-2142
157 1158
-2160
282 1159
-2178
157 1160
-2196
282 1161
-2214
157 1162
Rev 0.30
P 12/66
Signal
X-pos
Y-pos Pad #
Signal
X-pos Y-pos
S<116>
-2232
282
1163 S<51>
-3402
157
S<115>
-2250
157
1164 S<50>
-3420
282
S<114>
-2268
282
1165 S<49>
-3438
157
S<113>
-2286
157
1166 S<48>
-3456
282
S<112>
-2304
282
1167 S<47>
-3474
157
S<111>
-2322
157
1168 S<46>
-3492
282
S<110>
-2340
282
1169 S<45>
-3510
157
S<109>
-2358
157
1170 S<44>
-3528
282
S<108>
-2376
282
1171 S<43>
-3546
157
S<107>
-2394
157
1172 S<42>
-3564
282
S<106>
-2412
282
1173 S<41>
-3582
157
S<105>
-2430
157
1174 S<40>
-3600
282
S<104>
-2448
282
1175 S<39>
-3618
157
S<103>
-2466
157
1176 S<38>
-3636
282
S<102>
-2484
282
1177 S<37>
-3654
157
S<101>
-2502
157
1178 S<36>
-3672
282
S<100>
-2520
282
1179 S<35>
-3690
157
S<99>
-2538
157
1180 S<34>
-3708
282
S<98>
-2556
282
1181 S<33>
-3726
157
S<97>
-2574
157
1182 S<32>
-3744
282
S<96>
-2592
282
1183 S<31>
-3762
157
S<95>
-2610
157
1184 S<30>
-3780
282
S<94>
-2628
282
1185 S<29>
-3798
157
S<93>
-2646
157
1186 S<28>
-3816
282
S<92>
-2664
282
1187 S<27>
-3834
157
S<91>
-2682
157
1188 S<26>
-3852
282
S<90>
-2700
282
1189 S<25>
-3870
157
S<89>
-2718
157
1190 S<24>
-3888
282
S<88>
-2736
282
1191 S<23>
-3906
157
S<87>
-2754
157
1192 S<22>
-3924
282
S<86>
-2772
282
1193 S<21>
-3942
157
S<85>
-2790
157
1194 S<20>
-3960
282
S<84>
-2808
282
1195 S<19>
-3978
157
S<83>
-2826
157
1196 S<18>
-3996
282
S<82>
-2844
282
1197 S<17>
-4014
157
S<81>
-2862
157
1198 S<16>
-4032
282
S<80>
-2880
282
1199 S<15>
-4050
157
S<79>
-2898
157
1200 S<14>
-4068
282
S<78>
-2916
282
1201 S<13>
-4086
157
S<77>
-2934
157
1202 S<12>
-4104
282
S<76>
-2952
282
1203 S<11>
-4122
157
S<75>
-2970
157
1204 S<10>
-4140
282
S<74>
-2988
282
1205 S<9>
-4158
157
S<73>
-3006
157
1206 S<8>
-4176
282
S<72>
-3024
282
1207 S<7>
-4194
157
S<71>
-3042
157
1208 S<6>
-4212
282
S<70>
-3060
282
1209 S<5>
-4230
157
S<69>
-3078
157
1210 S<4>
-4248
282
S<68>
-3096
282
1211 S<3>
-4266
157
S<67>
-3114
157
1212 S<2>
-4284
282
S<66>
-3132
282
1213 S<1>
-4302
157
S<65>
-3150
157
1214 S<0>
-4320
282
S<64>
-3168
282
1215 DUMMY -4338
157
S<63>
-3186
157
1216 DUMMY -4356
282
S<62>
-3204
282
1217 DUMMY -4374
157
S<61>
-3222
157
1218 G<814>
-4392
282
S<60>
-3240
282
1219 G<812>
-4410
157
S<59>
-3258
157
1220 G<810>
-4428
282
S<58>
-3276
282
1221 G<808>
-4446
157
S<57>
-3294
157
1222 G<806>
-4464
282
S<56>
-3312
282
1223 G<804>
-4482
157
S<55>
-3330
157
1224 G<802>
-4500
282
S<54>
-3348
282
1225 G<800>
-4518
157
S<53>
-3366
157
1226 G<798>
-4536
282
S<52>
-3384
282
1227 G<796>
-4554
157
Jan 2008
Pad #
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
Signal
G<794>
G<792>
G<790>
G<788>
G<786>
G<784>
G<782>
G<780>
G<778>
G<776>
G<774>
G<772>
G<770>
G<768>
G<766>
G<764>
G<762>
G<760>
G<758>
G<756>
G<754>
G<752>
G<750>
G<748>
G<746>
G<744>
G<742>
G<740>
G<738>
G<736>
G<734>
G<732>
G<730>
G<728>
G<726>
G<724>
G<722>
G<720>
G<718>
G<716>
G<714>
G<712>
G<710>
G<708>
G<706>
G<704>
G<702>
G<700>
G<698>
G<696>
G<694>
G<692>
G<690>
G<688>
G<686>
G<684>
G<682>
G<680>
G<678>
G<676>
G<674>
G<672>
G<670>
G<668>
G<666>
X-pos Y-pos
-4572
282
-4590
157
-4608
282
-4626
157
-4644
282
-4662
157
-4680
282
-4698
157
-4716
282
-4734
157
-4752
282
-4770
157
-4788
282
-4806
157
-4824
282
-4842
157
-4860
282
-4878
157
-4896
282
-4914
157
-4932
282
-4950
157
-4968
282
-4986
157
-5004
282
-5022
157
-5040
282
-5058
157
-5076
282
-5094
157
-5112
282
-5130
157
-5148
282
-5166
157
-5184
282
-5202
157
-5220
282
-5238
157
-5256
282
-5274
157
-5292
282
-5310
157
-5328
282
-5346
157
-5364
282
-5382
157
-5400
282
-5418
157
-5436
282
-5454
157
-5472
282
-5490
157
-5508
282
-5526
157
-5544
282
-5562
157
-5580
282
-5598
157
-5616
282
-5634
157
-5652
282
-5670
157
-5688
282
-5706
157
-5724
282
Solomon Systech
Pad #
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
Signal
G<664>
G<662>
G<660>
G<658>
G<656>
G<654>
G<652>
G<650>
G<648>
G<646>
G<644>
G<642>
G<640>
G<638>
G<636>
G<634>
G<632>
G<630>
G<628>
G<626>
G<624>
G<622>
G<620>
G<618>
G<616>
G<614>
G<612>
G<610>
G<608>
G<606>
G<604>
G<602>
G<600>
G<598>
G<596>
G<594>
G<592>
G<590>
G<588>
G<586>
G<584>
G<582>
G<580>
G<578>
G<576>
G<574>
G<572>
G<570>
G<568>
G<566>
G<564>
G<562>
G<560>
G<558>
G<556>
G<554>
G<552>
G<550>
G<548>
G<546>
G<544>
G<542>
G<540>
G<538>
G<536>
SSD2123
X-pos Y-pos Pad #
-5742
157 1358
-5760
282 1359
-5778
157 1360
-5796
282 1361
-5814
157 1362
-5832
282 1363
-5850
157 1364
-5868
282 1365
-5886
157 1366
-5904
282 1367
-5922
157 1368
-5940
282 1369
-5958
157 1370
-5976
282 1371
-5994
157 1372
-6012
282 1373
-6030
157 1374
-6048
282 1375
-6066
157 1376
-6084
282 1377
-6102
157 1378
-6120
282 1379
-6138
157 1380
-6156
282 1381
-6174
157 1382
-6192
282 1383
-6210
157 1384
-6228
282 1385
-6246
157 1386
-6264
282 1387
-6282
157 1388
-6300
282 1389
-6318
157 1390
-6336
282 1391
-6354
157 1392
-6372
282 1393
-6390
157 1394
-6408
282 1395
-6426
157 1396
-6444
282 1397
-6462
157 1398
-6480
282 1399
-6498
157 1400
-6516
282 1401
-6534
157 1402
-6552
282 1403
-6570
157 1404
-6588
282 1405
-6606
157 1406
-6624
282 1407
-6642
157 1408
-6660
282 1409
-6678
157 1410
-6696
282 1411
-6714
157 1412
-6732
282 1413
-6750
157 1414
-6768
282 1415
-6786
157 1416
-6804
282 1417
-6822
157 1418
-6840
282 1419
-6858
157 1420
-6876
282 1421
-6894
157 1422
Rev 0.30
P 13/66
Signal
X-pos
Y-pos Pad #
Signal
G<534>
-6912
282
1423 G<404>
G<532>
-6930
157
1424 G<402>
G<530>
-6948
282
1425 G<400>
G<528>
-6966
157
1426 G<398>
G<526>
-6984
282
1427 G<396>
G<524>
-7002
157
1428 G<394>
G<522>
-7020
282
1429 G<392>
G<520>
-7038
157
1430 G<390>
G<518>
-7056
282
1431 G<388>
G<516>
-7074
157
1432 G<386>
G<514>
-7092
282
1433 G<384>
G<512>
-7110
157
1434 G<382>
G<510>
-7128
282
1435 G<380>
G<508>
-7146
157
1436 G<378>
G<506>
-7164
282
1437 G<376>
G<504>
-7182
157
1438 G<374>
G<502>
-7200
282
1439 G<372>
G<500>
-7218
157
1440 G<370>
G<498>
-7236
282
1441 G<368>
G<496>
-7254
157
1442 G<366>
G<494>
-7272
282
1443 G<364>
G<492>
-7290
157
1444 G<362>
G<490>
-7308
282
1445 G<360>
G<488>
-7326
157
1446 G<358>
G<486>
-7344
282
1447 G<356>
G<484>
-7362
157
1448 G<354>
G<482>
-7380
282
1449 G<352>
G<480>
-7398
157
1450 G<350>
G<478>
-7416
282
1451 G<348>
G<476>
-7434
157
1452 G<346>
G<474>
-7452
282
1453 G<344>
G<472>
-7470
157
1454 G<342>
G<470>
-7488
282
1455 G<340>
G<468>
-7506
157
1456 G<338>
G<466>
-7524
282
1457 G<336>
G<464>
-7542
157
1458 G<334>
G<462>
-7560
282
1459 G<332>
G<460>
-7578
157
1460 G<330>
G<458>
-7596
282
1461 G<328>
G<456>
-7614
157
1462 G<326>
G<454>
-7632
282
1463 G<324>
G<452>
-7650
157
1464 G<322>
G<450>
-7668
282
1465 G<320>
G<448>
-7686
157
1466 G<318>
G<446>
-7704
282
1467 G<316>
G<444>
-7722
157
1468 G<314>
G<442>
-7740
282
1469 G<312>
G<440>
-7758
157
1470 G<310>
G<438>
-7776
282
1471 G<308>
G<436>
-7794
157
1472 G<306>
G<434>
-7812
282
1473 G<304>
G<432>
-7830
157
1474 G<302>
G<430>
-7848
282
1475 G<300>
G<428>
-7866
157
1476 G<298>
G<426>
-7884
282
1477 G<296>
G<424>
-7902
157
1478 G<294>
G<422>
-7920
282
1479 G<292>
G<420>
-7938
157
1480 G<290>
G<418>
-7956
282
1481 G<288>
G<416>
-7974
157
1482 G<286>
G<414>
-7992
282
1483 G<284>
G<412>
-8010
157
1484 G<282>
G<410>
-8028
282
1485 G<280>
G<408>
-8046
157
1486 G<278>
G<406>
-8064
282
1487 G<276>
Jan 2008
X-pos Y-pos
-8082
157
-8100
282
-8118
157
-8136
282
-8154
157
-8172
282
-8190
157
-8208
282
-8226
157
-8244
282
-8262
157
-8280
282
-8298
157
-8316
282
-8334
157
-8352
282
-8370
157
-8388
282
-8406
157
-8424
282
-8442
157
-8460
282
-8478
157
-8496
282
-8514
157
-8532
282
-8550
157
-8568
282
-8586
157
-8604
282
-8622
157
-8640
282
-8658
157
-8676
282
-8694
157
-8712
282
-8730
157
-8748
282
-8766
157
-8784
282
-8802
157
-8820
282
-8838
157
-8856
282
-8874
157
-8892
282
-8910
157
-8928
282
-8946
157
-8964
282
-8982
157
-9000
282
-9018
157
-9036
282
-9054
157
-9072
282
-9090
157
-9108
282
-9126
157
-9144
282
-9162
157
-9180
282
-9198
157
-9216
282
-9234
157
Pad #
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
Signal
G<274>
G<272>
G<270>
G<268>
G<266>
G<264>
G<262>
G<260>
G<258>
G<256>
G<254>
G<252>
G<250>
G<248>
G<246>
G<244>
G<242>
G<240>
G<238>
G<236>
G<234>
G<232>
G<230>
G<228>
G<226>
G<224>
G<222>
G<220>
G<218>
G<216>
G<214>
G<212>
G<210>
G<208>
G<206>
G<204>
G<202>
G<200>
G<198>
G<196>
G<194>
G<192>
G<190>
G<188>
G<186>
G<184>
G<182>
G<180>
G<178>
G<176>
G<174>
G<172>
G<170>
G<168>
G<166>
G<164>
G<162>
G<160>
G<158>
G<156>
G<154>
G<152>
G<150>
G<148>
G<146>
X-pos
Y-pos
-9252
282
-9270
157
-9288
282
-9306
157
-9324
282
-9342
157
-9360
282
-9378
157
-9396
282
-9414
157
-9432
282
-9450
157
-9468
282
-9486
157
-9504
282
-9522
157
-9540
282
-9558
157
-9576
282
-9594
157
-9612
282
-9630
157
-9648
282
-9666
157
-9684
282
-9702
157
-9720
282
-9738
157
-9756
282
-9774
157
-9792
282
-9810
157
-9828
282
-9846
157
-9864
282
-9882
157
-9900
282
-9918
157
-9936
282
-9954
157
-9972
282
-9990
157
-10008
282
-10026
157
-10044
282
-10062
157
-10080
282
-10098
157
-10116
282
-10134
157
-10152
282
-10170
157
-10188
282
-10206
157
-10224
282
-10242
157
-10260
282
-10278
157
-10296
282
-10314
157
-10332
282
-10350
157
-10368
282
-10386
157
-10404
282
Solomon Systech
Pad #
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
Signal
G<144>
G<142>
G<140>
G<138>
G<136>
G<134>
G<132>
G<130>
G<128>
G<126>
G<124>
G<122>
G<120>
G<118>
G<116>
G<114>
G<112>
G<110>
G<108>
G<106>
G<104>
G<102>
G<100>
G<98>
G<96>
G<94>
G<92>
G<90>
G<88>
G<86>
G<84>
G<82>
G<80>
G<78>
G<76>
G<74>
G<72>
G<70>
G<68>
G<66>
G<64>
G<62>
G<60>
G<58>
G<56>
G<54>
G<52>
G<50>
G<48>
G<46>
G<44>
G<42>
G<40>
G<38>
G<36>
G<34>
G<32>
G<30>
G<28>
G<26>
G<24>
G<22>
G<20>
G<18>
G<16>
X-pos Y-pos Pad #
-10422
157 1618
-10440
282 1619
-10458
157 1620
-10476
282 1621
-10494
157 1622
-10512
282 1623
-10530
157 1624
-10548
282 1625
-10566
157 1626
-10584
282 1627
-10602
157
-10620
282
-10638
157
-10656
282
-10674
157
-10692
282
-10710
157
-10728
282
-10746
157
-10764
282
-10782
157
-10800
282
-10818
157
-10836
282
-10854
157
-10872
282
-10890
157
-10908
282
-10926
157
-10944
282
-10962
157
-10980
282
-10998
157
-11016
282
-11034
157
-11052
282
-11070
157
-11088
282
-11106
157
-11124
282
-11142
157
-11160
282
-11178
157
-11196
282
-11214
157
-11232
282
-11250
157
-11268
282
-11286
157
-11304
282
-11322
157
-11340
282
-11358
157
-11376
282
-11394
157
-11412
282
-11430
157
-11448
282
-11466
157
-11484
282
-11502
157
-11520
282
-11538
157
-11556
282
-11574
157
Signal
G<14>
G<12>
G<10>
G<8>
G<6>
G<4>
G<2>
G<0>
NC
NC
X-pos
Y-pos Pad #
-11592
282
-11610
157
-11628
282
-11646
157
-11664
282
-11682
157
-11700
282
-11718
157
-11768.5
282
-11821.5
157
Signal
X-pos Y-pos Pad # Signal
X-pos Y-pos
Note: IC material Temperature expansion factor should take into account during panel design.
SSD2123
Rev 0.30
P 14/66
Jan 2008
Solomon Systech
6
Pin Description
SSD2123 Pin Function Description
Key:
I = Input
O =Output
I/O = Bi-directional (input/output)
P = Power pin
GND = System VSS
Table 6-1: Power Supply Pins
Name
Type
VSS
AVSS
VSSRC
P
Connect
to
GND
GND
GND
VCHS
GND
VCORE
VREGC
VDDEXT
System
VDD
P
VDDIO
System
VDD
VCI
Power
supply
P
VCIP
VCIM
VCI
O
AVDD
AVDDJ
O
AVDDG
VCOMH
O
VCOML
VLCD255
VGH
O
VGL
VCOMR
SSD2123
I
Stabilizing
capacitor
Stabilizing
capacitor
AVDD on
FPC
AVDD on
FPC
Stabilizing
capacitor
Stabilizing
capacitor
Stabilizing
capacitor
Function
P 15/66
When not
in use
-
System ground pin of the IC.
Grounding for analog circuit.
Ground of
Grounding for analog circuit. This pin requires a
Power
noise free path for providing accurate LCD driving Supply
voltages.
Grounding for booster circuit.
Power for
VDD for core use
Core
- Connect a capacitor for stabilization
Logic
Power for
Voltage input pin for internal logic.
Internal
Connect to System VDD
VCORE
(refer to power connection Figure 14-1)
Regulator
Power for
Voltage input pin for logic I/O.
Interface
Logic Pins
Booster input voltage pin.
Power for - Connect to voltage source between 2.5V to 3.6V
Analog
Voltage supply pin for analog circuit. This pin
Circuits
requires a noise free path for providing accurate LCD driving voltages.
Booster
Negative voltage of VCI
Output
Booster
Booster voltage and regulated between 5.1V to 6.1V.
Voltages
Controlled by command Power control 2 (R0Ch)
Voltage
power supply used by on chip analog blocks and
for analog VGH/VGL dcdc. Must connect AVDD together
Voltage
power supply used by on chip analog blocks and
for analog VGH/VGL dcdc. Must connect AVDD together
This pin indicates a HIGH level of VCOM generated
Voltages
in driving the VCOM alternation.
for VCOM
This pin indicates a LOW level of VCOM generated in
Signal
driving the VCOM alternation.
LCD
Stabilizing
Driving
capacitor
Voltages
Stabilizing
capacitor
External
voltage
External
source or Reference
Open
Rev 0.30
Description
Jan 2008
This pin is the maximum source driver voltage.
-
A positive power output pin for gate driver.
-
A negative power output pin for gate driver.
-
This pin provides voltage reference for internal
voltage regulator when register VDV[4:0] of Power Open
Control 4 is set to “01111”.
Solomon Systech
VREGC
CXP
CXN
C11P
C11N
C12P
C12N
C13P
C13N
C1P
C1N
C2P
C2N
C3P
C3N
CSSRC
SSD2123
P
P
Regulator
Stabilizing output for
logic
capacitor
circuits
Booster
capacitor
Booster
capacitor
Booster
capacitor
Booster
Booster
and
capacitor
Stabilizati
Booster
on
capacitor
Capacitors
Booster
capacitor
Booster
capacitor
Charge
Sharing
Rev 0.30
P 16/66
Jan 2008
Regulator output for VCORE use
-
- Connect a capacitor to CXN
- Connect a capacitor to CXP
- Connect a capacitor to C11N
- Connect a capacitor to C11P
- Connect a capacitor to C12N
- Connect a capacitor to C12P
- Connect a capacitor to C13N
- Connect a capacitor to C13P
- Connect a capacitor to C1N
- Connect a capacitor to C1P
- Connect a capacitor to C2N
- Connect a capacitor to C2P
- Connect a capacitor to C3N
- Connect a capacitor to C3P
-
- Connect a capacitor to VSS
Open
-
Solomon Systech
Table 6-2: Interface Logic Pins
Name
SPID
CSB
SDI
SDC
SCK
SDO
SHUT
Typ
Connect to Function Description
e
ID selection pin for the SPI serial interface. When sending
serial data, the “ID” bit must match with the logic stage of
VDDIO
or
this pin.
VSS
(Refer to Serial Interface block description on Page XX
Serial
for details)
I
Interface
MPU
Chip select pin of serial interface.
MPU
Data input pin in serial mode.
MPU
Data/Command pin of serial interface.
MPU
Clock input pin in serial mode.
Serial
O
MPU
Data output pin in serial mode.
Interface
Display shut down pin to put the driver into sleep mode. A
sharp falling edge must be provided to such pin when IC
VDDIO
or Logic
power on.
I
Control
VSS
- Connect to VDDIO for sleep mode
- Connect to VSS for normal operating mode
Note: Software can override the setting
When not in
use
VDDIO
VSS
VSS
VSS
Open
VDDIO or VSS
Frame synchronization signal. Fixed to VDDIO or VSS if not
used.
VSYNC
I
MPU
HSYNC
I
MPU
DOTCLK
I
MPU
DEN
I
MPU
Display enable pin from controller.
VDDIO
MPU
Graphic
Display
Data
- RR[7:0] :
- RR[7:2] :
- GG[7:0] :
- GG[7:2] :
- BB[7:0] :
- BB[7:2] :
VDDIO or VSS
System
reset
RGB
Interface
Display
Timing
Signals
RR[7:0]
GG[7:0]
I
BB[7:0]
RESB
I
MPU
SRGB
I
VDDIO
VSS
or
X400
I
VDDIO
VSS
or
DENMODE I
VDDIO
VSS
or
SSD2123
Rev 0.30
RGB
interface
selection
RGB
interface
selection
RGB
interface
selection
P 17/66
Line synchronization signal. Fixed to VDDIO or VSS if not
used
Dot-clock signal and oscillator source. External clock
must be provided to that pin even at front or black porch non-display period.
Red Data – 24bit parallel/8bit serial
Red Data –18bit parallel/6bit serial
Green Data –24bit parallel
Green Data –18bit parallel
Blue Data –24bit parallel
Blue Data –18bit parallel
System reset pin. Initialization occurs once this pin is
pulled Low, the minimum pulse length is 1ms. A low
pulse must be applied after power-on. Connect this pin to
VDDIO when not used.
Determine data input for SSD2123.
- Connect to VSS for the operation of parallel RGB mode
18/24 bits.
- Connect to VDDIO for the operation of serial RGB mode
6/8 bits.
Note: Software can override the setting
Determine data input for SSD2123.
- Connect to VSS for the operation of using full 480
sources
- Connect to VDDIO for the operation of using 400 sources
at center. First data will appear at S40.
Note: Software can override the setting
Determine data input for SSD2123.
- Connect to VSS for the operation of SYNC mode
- Connect to VDDIO for the operation of DEN mode
Note: Software can override the setting
Jan 2008
VDDIO
-
-
-
Solomon Systech
GPI[3:0]
I
User define
GAMAS
I
VDDIO
VSS
or Logic
Control
General propose pins defined by user
Open
(GPIP=VSS)
GAMAS controls the default register values
VDDIO or VSS
Table 6-3: Interface Logic Pins
Name
Type
STYPE0
I
STYPE1
I
BGR
I
Connect to Function
Description
VDDIO
VSS
VDDIO
VSS
or
STYPE[1:0] = 0x ; SPID type 3 wires SPI
STYPE[1:0] = 10 ; standard 3 wires SPI
STYPE[1:0] = 11 ; standard 4 wires SPI
VDDIO
VSS
or
Serial
Interface
or
Selection
I
VDDIO
VSS
or
RL
I
VDDIO
VSS
or Panel
Mapping
controls
TB
I
VDDIO
VSS
or
SSD2123
I
VDDIO
VSS
Rev 0.30
-
Input pin to select the display reversion.
- Connect to VDDIO mapping data “0” to maximum
pixel voltage for normal white panel
- Connect to VSS mapping data “0” to minimum pixel
voltage for normal black panel
Note: Software can override the setting
Select the Source driver data shift direction.
- Connect to VDDIO for display first pixel data at S0
- Connect to VSS for display first pixel data at S479
Note: Software can override the setting
Select the Gate driver scan direction.
Note: Software can override the setting
Jan 2008
or
VDDIO
VSS
or
VDDIO
VSS
or
VDDIO
VSS
or
Input pin to select 16.7M-color or 8-color display
mode. After entered 8-color display mode, the driver
will switch to Frame-Inversion-Mode, and only MSB
VDDIO
of the data Red, Green and Blue will be considered.
VSS
- Connect to VDDIO for 8-color display mode
- Connect to VSS for 16.7M-color display mode
Note: Software can override the setting
or
P 18/66
-
Color mapping selection pin. Refer to G0-G815 pin
VDDIO
description.
VSS
Note: Software can override the setting
REV
CM
When not
in use
or
Solomon Systech
Table 6-4: Driver Output Pins
Name
Type
VCOM
G0-G815
O
Description
LCD
A power supply for the TFT-display common electrode.
Gate driver output pins. These pins output VGH or VGL
level.
Color filter arrangement depends on BGR pin.
Open
G(3n): Display Red if BGR = Low, Blue if BGR = High.
G(3n+1): Display Green.
G(3n+2): Display Blue if BGR = Low, Red if BGR = High.
Source driver output pins.
Open
LCD
S0-S479
When not
in use
Open
Connect to Function
LCD
Driving
Signals
LCD
Table 6-5: Miscellaneous Pins
Name
Type
Connect to Function
NC
-
-
DUMMY
-
-
TESTA/B/C I/O
SSD2123
FPC
Rev 0.30
Description
When not
in use
These pins must be left open and cannot be connected
Open
together
Floating pins and no connection inside the IC. These pins
Open
can be shorted together or connect to any signal.
Test pin of the internal circuit.
IC Testing
- Leave this pin open and optional to insert test point in FPC Open
Signal
for evaluation.
-
P 19/66
Jan 2008
Solomon Systech
7
COMMAND TABLE
Table 7-1: Command Table and POR (Power On Reset) values
Reg#
Register
Index
R
R01h
Driver output control
([XXXX][X0X1]0Fh
)
R02h
LCD-DrivingWaveform Control
(0C02h)
R/W D/C IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
0
0
*
*
*
*
*
*
*
*
*
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0
1
X400
RL
REV
CAD
BGR
SM
TB
1
0
0
1
1
1
1
1
1
X
X
X
X
X
0
X
1
0
0
1
1
1
1
1
1
0
0
0
B/C
EOR
NW9
NW8
NW7
NW6
NW5
NW4
NW3
NW2
NW1
NW0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
R03h
Power control (1)
(E4E2h)
0
1
DCT3
DCT2
DCT1
DCT0
BT3
BT2
BT1
BT0
DC3
DC2
DC1
DC0
AP2
AP1
AP0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
0
1
0
R04h
Separate Gamma(1)
(0400h)
0
0
0
0
0
0
OLO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
R0Bh
Frame cycle control
(DC00h)
0
NO1
NO0
SDT1
SDT0
EQ1
EQ0
0
0
EQ2
0
0
0
BTP1
BTP0
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VRC2
VRC1
VRC0
1
1
Power control (2)
R0Ch
(0005h)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
Power control (3)
R0Dh
(0002h)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
VRH3
VRH2
VRH1
VRH0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Power control (4)
R0Eh
(2900h)
0
1
0
0
VCOMG
VDV4
VDV3
VDV2
VDV1
VDV0
0
0
0
0
0
0
0
VCOMAS
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCN8
SCN7
SCN6
SCN5
SCN4
SCN3
SCN2
SCN1
SCN0
R0Fh
Gate scan starting
Position
(0000h)
R16h
R17h
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pixel per line
(EF8Eh) x400=0
(C786h) x400=1
0
1
XL8
XL7
XL6
XL5
XL4
XL3
XL2
XL1
XL0
HBP6
HBP5
HBP4
HBP3
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
Vertical Porch
(0003h)
0
1
0
0
0
0
0
0
0
0
VBP7
VBP6
VBP5
VBP4
VBP3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
nOTP
0
VCM7
VCM6
VCM5
VCM4
VCM3
VCM2
VCM1
VCM0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
PKP
12
PKP
11
PKP
10
0
0
0
0
0
PKP
02
PKP
01
PKP
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
PKP
32
PKP
31
PKP
30
0
0
0
0
0
PKP
22
PKP
21
PKP
20
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
PKP
51
PKP
50
PKP
42
PKP
41
PKP
40
Power control (5)
R1Eh
(0029h)
R30h
R31h
R32h
R33h
R34h
R35h
R36h
R37h
R3Ah
R3Bh
R28h
γ control (1)
(0000h)
γ control (1)
(0707h)
γ control (1)
0
1
(0003h)
γ control (1)
0
1
0
VBP2
VBP1
VBP0
0
0
0
0
0
PKP
52
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
PRP
12
PRP
11
PRP
10
0
0
0
0
0
PRP
02
PRP
01
PRP
00
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
PKN
12
PKN
11
PKN
10
0
0
0
0
0
PKN
02
PKN
01
PKN
00
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
PKN
31
PKN
30
PKN
22
PKN
21
PKN
20
0
1
0
0
0
0
0
PKN
32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PKN
52
PKN
51
PKN
50
0
0
0
0
0
PKN
42
PKN
41
PKN
40
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
PRN
12
PRN
11
PRN
10
0
0
0
0
0
PRN
02
PRN
01
PRN
00
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
VRP
13
VRP
12
VRP
11
VRP
10
VRP
03
VRP
02
VRP
01
VRP
00
(0204h)
γ control (2)
1
1
0
(0707h)
γ control (1)
1
0
(0000h)
γ control (1)
0
HBP0
1
(0307h)
γ control (1)
0
HBP1
0
(0401h)
γ control (1)
0
HBP2
0
1
(0D0Bh)
0
0
0
VRP
14
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
0
1
1
0
0
VRN
14
VRN
13
VRN
12
VRN
11
VRN
10
0
0
0
0
VRN
03
VRN
02
VRN
01
VRN
00
γ control (2)
0
1
0
(0D0Bh)
VCOM OTP
(0000h)
0
0
0
0
1
1
0
1
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
CCB3
CCB2
CCB1
CCB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note: X means hardware defining default setting
SSD2123
Rev 0.30
P 20/66
Jan 2008
Solomon Systech
Table 7-2 – Gamma Registers POR value
Command
R30h-R3Bh
PKP0
PKP1
PKP2
PKP3
PKP4
PKP5
PRP0
PRP1
VRP0
VRP1
PKN0
PKN1
PKN2
PKN3
PKN4
PKN5
PRN0
PRN1
VRN0
VRN1
SSD2123
Rev 0.30
P 21/66
Jan 2008
GAMAS=0
GAMAS=1
000
000
111
111
011
000
001
100
1011
01101
111
011
000
000
111
111
100
010
1011
01101
000
000
000
010
001
000
000
111
0000
00111
101
100
010
010
111
111
110
000
0011
00000
Solomon Systech
Table 7-3: Registers POR value at GAMAS = 0
Reg#
R03h
R0Ch
R0Dh
R0Eh
R1Eh
Register
Power control (1)
Power control (2)
Power control (3)
Power control (4)
Power control (5)
Hex
code
E4E2
0005
0002
2900
0029
IB15 IB14 IB13 IB12 IB11 IB10 IB9
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
IB8
0
0
0
1
0
IB7 IB6
1
0
0
0
0
1
0
0
0
0
IB5
1
0
0
0
1
IB4 IB3
0
0
0
0
0
0
0
0
0
1
IB2
0
1
0
0
0
IB1 IB0
1
0
1
0
0
0
1
0
0
1
Table 7-4: Registers POR value at GAMAS = 1
Reg#
R03h
R0Ch
R0Dh
R0Eh
R1Eh
Register
Power control (1)
Power control (2)
Power control (3)
Power control (4)
Power control (5)
SSD2123
Rev 0.30
Hex
code
E4E2
0005
000F
3100
0034
IB15 IB14 IB13 IB12 IB11 IB10 IB9
P 22/66
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
Jan 2008
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
IB8
0
0
0
1
0
IB7 IB6
1
0
0
0
0
1
0
0
0
0
IB5
1
0
0
0
1
IB4 IB3
0
0
0
0
1
0
0
1
0
0
IB2
0
1
1
0
1
IB1 IB0
1
0
1
0
0
0
1
1
0
0
Solomon Systech
8
COMMAND DESCRIPTION
Index (IR)
R/W
W
DC
0
IB15
∗
IB14
∗
IB13
∗
IB12
∗
IB11
∗
IB10
∗
IB9
∗
IB8
∗
IB7
∗
IB6
ID6
IB5
ID5
IB4
ID4
IB3
ID3
IB2
ID2
IB1
ID1
IB0
ID0
The index instruction specifies the RAM control indexes (R00h to R7Fh). It sets the register number in the range of
0000000 to 1111111 in binary form. But do not access to Index register and instruction bits which do not have it’s own
index register.
Driver Output Control (R01h) (POR = [XXXX][X0X1]0Fh)
R/W
DC
W
1
POR
IB15
X400
X
IB14
RL
X
IB13
REV
X
IB12
CAD
X
IB11
BGR
X
IB10
SM
0
IB9
TB
X
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
MUX8 MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0
1
0
0
0
0
1
1
1
1
X400: When X400=”0”, full 480 sources are in operation When X400=”1”, only 400 sources at the center are in
operation. First data will appear at S40.
X400 = 0
X400 = 1
G0
G2
G4
G1
G3
G5
G717
G719
G716
G718
S479
G0
G2
G4
G1
G3
G5
G717
G719
S0
G716
G718
S439
S40
RL: For MOD = “0”, selects the output shift direction of the source driver of stripe type. When RL = “1”, S0 shifts to
S480 and 1st pixel color is assigned from S1. When RL = “0”, S480 shifts to S0 and 1st pixel color is assigned from S480.
Set RL bit and BGR bit when changing the dot order of R, G and B.
REV: Displays all character and graphics display sections with reversal when REV = “1”. Since the grayscale level can
be reversed, display of the same data is enabled on normally white and normally black panels. Source output level is
indicated below.
REV
RGB data
000000B
:
111111B
000000B
:
111111B
1
0
Source Output level
VCOM = ”H”
V63
:
V0
V0
:
V63
VCOM = ”L”
V0
:
V63
V63
:
V0
CAD: Set up based on the retention capacitor configuration of the TFT panel.
CAD
0
1
Retention capacitor configuration
Cs on Common
Cs on Gate
BGR: For MOD = “0”, selects the <R><G><B> arrangement. When BGR = “0” <R><G><B> color is assigned from
G0. When BGR = “1” <B><G><R> color is assigned from G0.
SSD2123
Rev 0.30
P 23/66
Jan 2008
Solomon Systech
SM: For MOD = “0”, change the division of gate driver. When SM = “0”, odd/even division (interlace mode) is selected.
When SM = “1”, upper/lower division is selected. Select the division mode according to the mounting method.
TB: For MOD = “0”, selects the output shift direction of the gate driver. When TB = “1”, G0 shifts to G815. When TB =
“0”, G815 shifts to G0.
Note:
The default setting of register bits X400, RL, REV, BGR and TB are defined by the logic stage of corresponding hardware pins.
These bits will override the hardware setting once software command was sent to set the bits.
SSD2123
Rev 0.30
P 24/66
Jan 2008
Solomon Systech
SM = 0
SM = 1
G0
G2
G4
G1
G3
G5
G812
G814
TB = 1
RL = 0
G1
G3
G812
G814
G813
G815
S479
TB = 0
RL = 0
G0
G2
G813
G815
S0
S479
S0
G0
G2
G0
G2
G4
G1
G3
G5
G812
G814
G1
G3
G812
G814
G813
G815
S479
TB = 1
RL = 1
G813
G815
S479
S0
S0
G0
G2
G0
G2
G4
G1
G3
G5
G812
G814
G1
G3
G812
G814
G813
G815
S479
TB = 0
RL = 1
G813
G815
S479
S0
S0
G0
G2
G4
G1
G3
G5
G0
G2
G812
G814
G1
G3
G812
G814
G813
G815
S479
SSD2123
Rev 0.30
S0
P 25/66
Jan 2008
G813
G815
S479
S0
Solomon Systech
LCD-Driving-Waveform Control (R02h) (POR = 0C02h)
R/W DC
W
1
POR
IB15
0
0
IB14
0
0
IB13
0
0
IB12
0
0
IB11
B/C
1
IB10
EOR
1
IB9
IB8
IB7
NW9 NW8 NW7
0
0
0
IB6
NW6
0
IB5
NW5
0
IB4
NW4
0
IB3
NW3
0
IB2
NW2
0
IB1
NW1
1
IB0
NW0
0
B/C: Select the liquid crystal drive waveform VCOM.
When B/C = 0, frame inversion of the LCD driving signal is enabled.
When B/C = 1, a N-line inversion waveform is generated and alternates in a N-line equals to NW[9:0]+1.
EOR: When B/C = 1 and EOR = 1, the odd/even frame-select signals and the N-line inversion signals are EORed for
alternating drive. EOR is used when the LCD is not alternated by combining the set values of the lines of the LCD driven
and the N-lines.
NW9-0: Specify the number of lines that will alternate at the N-line inversion setting (B/C = 1). NW9-0 alternate for
every set value + 1 lines.
Figure 8-1: Line Inversion AC Driver
N Frame
Back porch
1
2
3
N+1 Frame
Front porch
4
820 821
5
822
823
Back porch
824
1
2
3
4
Front porch
5
820 821
822
823 824
Frame Inversion
816 line drive
N Frame
Back porch
1
2
3
N+1 Frame
Front porch
4
820 821
5
822
823
Back porch
824
1
2
3
4
Front porch
5
820 821
822
823
Line Inversion
816 line drive
SSD2123
Rev 0.30
P 26/66
Jan 2008
Solomon Systech
Power control 1 (R03h) (POR = E3E2h)
R/W DC
W
1
POR
IB15 IB14 IB13 IB12 IB11
DCT3 DCT2 DCT1 DCT0 BT3
1
1
1
0
0
IB10
BT2
0
IB9
BT1
1
IB8
BT0
1
IB7
DC3
1
IB6
DC2
1
IB5
DC1
1
IB4
DC0
0
IB3
AP2
0
IB2
AP1
0
IB1
AP0
1
IB0
0
0
DCT3-0: Set the step-up cycle of the step-up circuit for 8-color mode (CM = VDDIO). When the cycle is accelerated, the
driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into
account the display quality and power consumption.
For 512 dotclk per line
DCT3 DCT2 DCT1 DCT0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
1
1
Step-up cycle
Fline × 8
Fline × 6
Fline × 5
Fline × 4
Fline × 2
Fline × 1
fosc / 1
fosc / 2
fosc / 4
fosc / 8
For 416 dotclk per line
DCT3 DCT2 DCT1 DCT0
Step-up cycle
0
0
0
1
Fline × 8
0
0
1
1
Fline × 6
0
1
0
1
Fline × 5
0
1
1
1
Fline × 4
1
0
0
1
Fline × 2
1
0
1
1
Fline × 1
1
0
0
fosc / 1
1
1
1
0
1
fosc / 2
1
1
1
0
fosc / 4
1
1
1
1
fosc / 8
Note: Fline = Horizontal frequency (fH Typ. TBDkHz)
fosc = DOTCLK frequency (fDOTCLK Typ. TBDMHz)
BT3-0: Control the step-up factor of the step-up circuit. Adjust the step-up factor according to the power-supply voltage
to be used.
BT3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SSD2123
BT2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BT1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Rev 0.30
BT0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
P 27/66
VGH output
VGL output
AVDD x 3
-(VGH - VCI)
AVDD x 3
-(VGH - AVDD)
AVDD x 3
-(AVDD x 3)
AVDD x 2 + VCI
-(VGH)
AVDD x 2 + VCI
-(VGH - VCI)
AVDD x 2 + VCI
-(VGH - AVDD x 2)
AVDD x 2
-(VGH)
AVDD x 2
-(VGH - VCI)
Reserved
Reserved
AVDD x 3
-(AVDD)
Reserved
Reserved
Reserved
Reserved
Reserved
Jan 2008
VGH booster ratio
VGL booster ratio
+6
-5
+6
-4
+6
-6
+5
-5
+5
-4
+5
-3
+4
-4
+4
-3
Reserved
Reserved
+6
-2
Reserved
Reserved
Reserved
Reserved
Reserved
Solomon Systech
DC3-0: Set the step-up cycle of the step-up circuit for 16.7M-color mode (CM = VSS). When the cycle is accelerated, the
driving ability of the step-up circuit increases, but its current consumption increases too. Adjust the cycle taking into
account the display quality and power consumption.
For 512 dotclk per line
DC3
0
DC2
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
DC1
0
1
0
1
0
1
0
0
1
1
DC0
0
0
0
0
0
1
0
1
0
1
Step-up cycle
Fline × 8
Fline × 6
Fline × 5
Fline × 4
Fline × 2
Fline × 1
fosc / 1
fosc / 2
fosc / 4
fosc / 8
For 416 dotclk per line
DC3
0
0
0
0
1
1
DC2 DC1
DC0
Step-up cycle
0
0
1
Fline × 8
0
1
1
Fline × 6
1
0
1
Fline × 5
1
1
1
Fline × 4
0
0
1
Fline × 2
0
1
1
Fline × 1
1
0
0
fosc / 1
1
0
1
fosc / 2
1
1
0
fosc / 4
1
1
1
fosc / 8
Fline = Horizontal frequency (fH Typ. TBDkHz)
fosc = DOTCLK frequency (fDOTCLK Typ. TBDMHz)
1
1
1
1
Note:
AP2-0: Adjust the amount of current from the stable-current source in the internal operational amplifier circuit. When
the amount of current becomes large, the driving ability of the operational-amplifier circuits increase. Adjust the current
taking into account the power consumption. While there is no display, such as the system is in a sleep mode, AP2-0 can
be set to (0,0,0) and shutting down the operational amplifier can reduce the power consumption.
AP2
0
0
0
0
1
1
1
1
AP1
0
0
1
1
0
0
1
1
AP0
0
1
0
1
0
1
0
1
Op-amp power
Least
Small
Small to medium
Medium
Medium to large
Large
Large to Maximum
Maximum
Seperate Gamma (R04h) (POR = 0400h)
R/W DC
W
1
POR
IB15
0
0
IB14
0
0
IB13
0
0
IB12
0
0
IB11
0
0
IB10
OLO
1
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
0
0
IB2
0
0
IB1
0
0
IB0
0
0
OLO: When OLO = “1”, all R,G and B gamma registers are set by one set of gamma control, R30h to R3Bh.
When OLO = “0”, R, G and B gamma registers are set separately by registers R30h to R3Bh, R40h to R4Bh and
R50h to R5Bh.
SSD2123
Rev 0.30
P 28/66
Jan 2008
Solomon Systech
Frame Cycle Control (R0Bh) (POR = D800h)
R/W
DC
W
1
POR
IB15
NO1
1
IB14 IB13 IB12 IB11
NO0 SDT1 SDT0 EQ1
1
0
1
1
IB10
EQ0
0
IB9
0
0
IB8
0
0
IB7
EQ2
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
IB2
BTP1 BTP0
0
0
IB1
0
0
IB0
0
0
NO1-0: Sets amount of non-overlap of the gate output.
NO1
0
0
1
1
NO0
0
Amount of non-overlap
HSYNC_falling + 100 DOTCLK
HSYNC _falling + 60 DOTCLK
HSYNC _falling + 30 DOTCLK
6 DOTCLK after Source On
1
0
1
1 Line period
1 Line period
Gn
Non-overlap period
Gn+1
SDT1-0: Set delay amount from the gate output signal falling edge of the source outputs.
SDT1
0
0
1
1
SDT0
0
Delay amount of the source output
HSYNC_falling – 3 DOTCLK
HSYNC_falling – 7 DOTCLK
HSYNC_falling – 11 DOTCLK
HSYNC_falling – 15 DOTCLK
1
0
1
EQ2-0: Sets the equalizing period on source
EQ2
0
0
0
0
1
1
1
1
EQ1
0
0
1
1
0
0
1
1
EQ0
0
1
0
1
0
1
0
1
1 Line period
EQ period
No EQ
16 clock cycle
32 clock cycle
Reserved
48 clock cycle
64 clock cycle
80 clock cycle
96 clock cycle
1 Line period
Gn
Sn
EQ
Delay amount of
the source output
Equalizing
period
BTP1-0: Set the Primary booster ratio.
BTP1
0
0
1
1
SSD2123
Rev 0.30
P 29/66
BTP0
0
1
0
1
Jan 2008
Primary booster ratio
2X
2.5X
3X
2X
Solomon Systech
Power Control 2 (R0Ch) (POR = 0005h)
R/W DC
W
1
POR
IB15
0
0
IB14
0
0
IB13
0
0
IB12
0
0
IB11
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
0
0
IB2
IB1
IB0
VRC2 VRC1 VRC0
1
0
1
VRC[2:0]: Adjust AVDD output voltage. The adjusted level is indicated in the chart below VRC2-0 setting.
VRC2
0
0
VRC1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
Note:
VRC0
0
1
AVDD voltage
5.1V
5.3V
5.5V
5.7V
5.9V
6.1V
Reserved
Reserved
0
1
0
1
0
1
VCI=3.3V and without panel loading
Figures on the above table are target AVDD output, actual AVDD voltage depends on VCI, booster efficiency and panel loading
Power Control 3 (R0Dh) (POR = 000Ch)
R/W DC
W
1
POR
IB15 IB14 IB13 IB12
0
0
0
0
0
0
0
0
IB11
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
IB2
IB1
IB0
VRH3 VRH2 VRH1 VRH0
1
1
0
0
VRH3-0: Set amplitude magnification of VLCD255. These bits amplify the VLCD255 voltage 1.78 to 3.00 times the Vref
voltage set by VRH3-0.
VRH3
VRH2 VRH1
VRH0
VLCD255 Voltage
0
0
0
0
Vref x 2.815
0
0
0
1
Vref x 2.905
0
0
0
Vref x 3.000
1
0
0
1
Vref x 1.780
1
0
1
0
Vref x 1.850
0
0
1
1
Vref x 1.930
0
0
1
0
Vref x 2.020
1
0
1
1
Vref x 2.090
1
1
0
0
Vref x 2.165
0
1
0
1
Vref x 2.245
0
1
0
0
Vref x 2.335
1
1
0
1
Vref x 2.400
1
1
1
0
Vref x 2.500
0
1
1
1
Vref x 2.570
0
1
1
1
0
Vref x 2.645
1
1
1
1
Vref x 2.725
Note:
Vref is the internal reference voltage equals to 2.0V.
SSD2123
Rev 0.30
P 30/66
Jan 2008
Solomon Systech
Power Control 4 (R0Eh) (POR = 3200h)
R/W DC
W
1
POR
IB15 IB14
IB13
IB12 IB11 IB10
IB9
IB8 IB7
0
0 VCOMG VDV4 VDV3 VDV2 VDV1 VDV0 0
0
0
1
1
0
0
1
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
0
0
IB2
0
0
IB1
IB0
0 VCOMAS
0
0
VCOMG: When VCOMG = “1”, it is possible to set output voltage of VCOML to any level, and the instruction (VDV4-0)
becomes available. When VCOMG = “0”, VCOML output is fixed to Hi-z level, VCI2 output for VCOML power supply stops,
and the instruction (VDV4-0) becomes unavailable. Set VCOMG according to the sequence of power supply setting flow
as it relates with power supply operating sequence.
VDV4-0: Set the alternating amplitudes of VCOM at the VCOM alternating drive. These bits amplify VCOM amplitude
0.6 to 1.23 times the VLCD255 voltage. When VCOMG = “0”, the settings become invalid.
VDV4
0
0
0
VDV3
0
0
0
VDV1
0
0
1
1
VDV2
0
0
0
:
:
:
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
:
:
:
1
1
1
∗
0
0
0
1
VLCD255 x 1.05
VLCD255x 1.08
1
0
1
∗
:
Step = 0.03
:
VLCD255 x 1.20
VLCD255 x 1.23
Reserved
Reserved
1
1
1
1
Note1:
Note2:
Note3:
1
0
0
0
0
1
0
1
1
∗
VCOMA < 6.0V
VCOMH – VCOML < 6.0V
|VCOML| < VCI
VCOMAS: Set the equation of VCOML.
VCOML =
α
VCOMAS
0
1
SSD2123
Rev 0.30
P 31/66
Jan 2008
VDV0
0
1
0
VCOMA
VLCD255 x 0.60
VLCD255 x 0.63
VLCD255 x 0.66
:
Step = 0.03
:
VLCD255 x 0.99
VLCD255 x 1.02
External Voltage
Reference
x VCOMH - VCOMA
α
1.0
0.667
Solomon Systech
Pixel per line (R16h) (POR = 8F8Eh when x400=0, POR = C786h when x400=1
R/W DC IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
W
1
XL8 XL7 XL6 XL5 XL4
XL3
XL2 XL1 XL0 HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0
POR(x400=0) 1
1
1
0
1
1
1
1
1
0
0
0
1
1
1
0
POR(x400=1) 1
1
0
0
0
1
1
1
1
0
0
0
1
1
1
0
Note:
Number of dotclk for hsync active low period must be smaller than that of HBP
Only for 24-bit, 18-bit parallel and 8-bit, 6-bit serial interface.
XL8-0: Set the number of valid pixel per line.
XL8
0
0
0
XL7
0
0
0
XL6
0
0
0
XL5
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
XL4
0
0
0
:
:
:
0
0
:
:
:
1
1
∗
XL3
0
0
0
XL2
0
0
0
XL1
0
0
1
XL0
0
1
0
1
1
1
1
1
1
0
1
1
1
∗
1
1
∗
1
1
∗
0
1
∗
No. of pixel per line
1
2
3
:
Step = 1
:
399
400 (por if x400=1)
:
Step = 1
:
479
480 (por if x400=0)
Reserved
HBP6-0: Set the delay period from falling edge of HSYNC signal to first valid data.
No. of clock cycle of DOTCLK
HBP6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HBP5
HBP4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HBP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
HBP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
HBP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
HBP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
:
:
:
1
1
SSD2123
1
1
Rev 0.30
1
1
1
P 32/66
1
1
Jan 2008
1
1
0
1
24-bit RGB
8-bit RGB
(without dummy)
2
6
3
4
5
6
7
8 (por if x400=1)
9
10
11
12
13
14
15
16 (por if x400=0)
9
12
15
18
21
24
27
30
33
36
39
42
45
48
:
Step = 1
:
:Step = 3
128
129
384
387
Solomon Systech
Example for 24-bit RGB interface:
Cycle time of HYSYNC
Set by HBP6-0
Set by XL8-0
HYSNC
Pixel
Data
HFP
Default 480 pixels per line
Dummy
D0
D1
D2
Dummy
D477 D478 D479
DOTCLK
8 clock cycles of DOTCLK
HBP6-0 = 000110
Example for 8-bit RGB interface (without dummy):
Cycle time of HYSYNC
Set by HBP5-0
Set by XL8-0
HYSNC
Pixel
Data
HFP
Default 480 pixels per line
Dummy
D0
D479
Dummy
DOTCLK
24 clock cycles of DOTCLK
HBP5-0 = 000110
SSD2123
Rev 0.30
P 33/66
Jan 2008
Solomon Systech
Vertical Porch (R17h) (POR = 0003h)
R/W DC
W
1
POR
IB15 IB14 IB13 IB12 IB11
0
0
0
0
0
0
0
0
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
VBP7 VBP6 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0
0
0
0
0
0
0
1
1
VBP7-0: Set the delay period from falling edge of VSYNC to first valid line. The line data within this delay period will
be treated as dummy line.
VBP7 VBP6 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
:
:
:
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
*
*
*
*
No. of clock cycle of HSYNC
0
1
2
3
4
:
Step = 1
:
224
225
Reserved
Example for 24-bit RGB interface:
Cycle time of VSYNC
Set by VBP7-0
VSYNC
272Lines
HSYNC
Dummy Lines
SSD2123
Rev 0.30
st
1 Line
P 34/66
Jan 2008
Last Line
VFP
Solomon Systech
Power Control 5 (R1Eh) (POR = 0029h)
R/W DC
W
1
POR
IB15 IB14 IB13 IB12 IB11
0
0
0
0
0
0
0
0
0
0
IB10
0
0
IB9
nOTP
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
0
VCM7 VCM6 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0
0
0
0
1
0
1
0
0
1
nOTP: nOTP equals to “0” after power on reset and VCOMH voltage equals to programmed OTP value. When nOTP set
to “1”, setting of VCM7-0 becomes valid and voltage of VCOMH can be adjusted.
VCM7-0: Set the VCOMH voltage if nOTP = “1”. These bits amplify the VCOMH voltage 0.503 to 0.999 times the VLCD255
voltage.
VCM7
0
0
VCM6
0
0
VCM5
0
0
VCM4
0
0
VCM3
0
0
VCM2
0
0
VCM1
0
0
VCM0
0
1
1
1
1
1
1
1
0
1
:
:
:
1
1
SSD2123
1
1
1
1
1
1
Note: VCI < VCOMH < AVDD
Rev 0.30
P 35/66
Jan 2008
VCOMH
VLCD255 x 0.503
VLCD255 x 0.505
:
Step = 1/512
:
VLCD255 x 0.997
VLCD255 x 0.999
Solomon Systech
9
EXTENDED COMMAND DESCRIPTION
Reminder – In order to activate extended command, user is required to send R28h-0006 prioir to the extended command
in application. See below for further description on the R28h register.
VCOM OTP (R28h) (POR = 0000h)
R/W
DC
W
1
POR
IB15
0
0
IB14
0
0
IB13
0
0
IB12
0
0
IB11
0
0
IB10
0
0
IB9
0
0
IB8
0
0
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
IB2
IB1
IB0
CCB3 CCB2 CCB1 CCB0
0
0
0
0
CCB3-0: Command Control Bit, the master control of the internal command decoder. This register provides function of
software reset and OTP programming.
CCB3
0
0
CCB2
0
1
CCB1
0
0
CCB0
0
1
0
1
1
0
1
1
SSD2123
0
1
1
1
All other setting
Rev 0.30
P 36/66
0
0
Jan 2008
Usage
Release Reset or no action
Driver initialization
Enable extended test command/
Enable for OTP Programming
Fire OTP
Reset all command bits to default
Reserved
Solomon Systech
10 MTP PROGRAMMING/ ERASE
MTP Programming sequence
Remark: * The application setup should be synchronized.
Note1: nMTP must set to “0” to activate the MTP effect.
Note2: VCI is suggested to be larger than 3.3V during fire MTP.
Precaution:
1. All capacitors on MTP machine should be discharged completely before placing the LCD module.
2. The MTP programming voltage should not be applied when placing and removing the LCD module.
3. The MTP programming voltage should not be applied before VDDIO/VDDEXT/VCI.
4. After MTP is finished, the capacitors at VGH and VCIX2 must be discharged completely before removing the
LCD module.
Figure 10-1: MTP programming circuitry
Apply voltage at Step (4)
SSD2123
VGH
+
C
-
Note: C = 1uF
(built-in on the module)
14.5V ±0.1V
GND
SSD2123
Rev 0.30
P 37/66
Jan 2008
Solomon Systech
Figure 10-2: MTP Programming Flowchart
MTP Sequence
Power up the module as application
[e.g. VCI = 3.3V, VDDIO = 1.8V]*
Turn on the display as normal mode to 65k/262k color with a
testing pattern if any
Set nMTP = “1” in R1Eh
Not optimum value
Adjust VCOMH by
VCM[7:0] in R1Eh
Optimized VCOMH value
Toggle reset pin – Reset SSD2123
Connect a power supply to the module
[VCI = VDDEXT = VDDIO = 3.3V]*
Write commands for MTP initialization:
Register
Value
R28h
0006h
R29h
80C0h
R2Dh
7F50h
Wait 200ms for activation
Connect VGH with 14.5V power supply (Figure 10-3)
Write the optimum value to VCM [7:0] in R1Eh and
set nMTP = “1”.
Write command for firing MTP:
Register
Value
R28h
000Ah
Wait 500ms for the process
Power down the module and remove 14.5V power supply
MTP completed
SSD2123
Rev 0.30
P 38/66
Jan 2008
Solomon Systech
MTP Erase sequence
Remark: * The application setup should be synchronized.
Precaution:
1.
All capacitors on MTP machine should be discharged completely before placing the LCD
module.
2.
The MTP erase voltage should not be applied when placing and removing the LCD module.
3.
The MTP erase voltage should not be applied before VDDIO/VDDEXT/VCI.
4.
After Erasing MTP is finished, the capacitors at VGH and VCIX2 must be discharged
completely before removing the LCD module.
Figure 10-3: MTP Erase circuitry
SSD2123
+
-
VGH
Note:
GND
C = 1uF
(built-in on the module)
9V
GND
MTP Re-Write cycle
Table 10-1: MTP Re-write cycle
Characteristics
Re-write Cycle
Power Supply voltage for programming
Power Supply voltage for erase
Program time
Erase time
SSD2123
Rev 0.30
P 39/66
Jan 2008
Symbol
Min
Typ
Max
Units
N
VGH
VGH
Tprog
Terase
-
14.5
9
0.5
1
5
-
Cycle
V
V
s
s
Solomon Systech
Figure 10-4: MTP Erase Flowchart
MTP Erase Sequence
Turn off and Power down the module
Connect a power supply to the module
[e.g. VCI = 3.3V, VDDEXT = VDDIO = 3.3V, REGVDD =High]*
Toggle reset pin to reset the module
Write commands for erase MTP initialization:
Register
Value
R28h
0006h
R29h
80C0h
R2Dh
7F50h
R0Fh
013Fh
Wait 200ms for activation
Connect VGH with 9V power supply (Figure
10-3)
Write command for erasing MTP:
Register
Value
R28h
0008h
Wait 1s for the process
Write command for disable erasing MTP:
Register
Value
R28h
0000h
Power down the module and remove 9V power supply
MTP Erase completed
SSD2123
Rev 0.30
P 40/66
Jan 2008
Solomon Systech
11 GAMMA ADJUSTMENT FUNCTION
The SSD2123 incorporates gamma adjustment function for the 16M-color display. Gamma adjustment is implemented
by deciding the 8-grayscale levels with angle adjustment and micro adjustment register. Also, angle adjustment and
micro adjustment is fixed for each of the internal positive and negative polarity. Set up by the liquid crystal panel’s
specification.
RGB Interface
Display Data
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 G7 G6 G5 G4 G3 G2 G1 G0
PKP02 PKP01 PKP00
PKP12 PKP11 PKP10
PKP22 PKP21 PKP20
Positive
polarity
register
V0
PKP32 PKP31 PKP30
PKP42 PKP41 PKP40
8-levels
PRP12 PRP11 PRP10
8-bits
8-bits
64 levels
PKP52 PKP51 PKP50
PRP02 PRP01 PRP00
8-bits
Grayscale
amplifier
VRP03 VRP02 VRP01 VRP00
VRP14 VRP13 VRP12 VRP11 VRP10
256 grayscale
Control <R>
256 grayscale
Control <G>
256 grayscale
Control <B>
LCD Driver
LCD Driver
LCD Driver
G
B
V255
PKN02 PKN01 PKN00
PKN12 PKN11 PKN10
PKN22 PKN21 PKN20
Negative
polarity
register
PKN32 PKN31 PKN30
R
PKN42 PKN41 PKN40
PKN52 PKN51 PKN50
PRN02 PRN01 PRN00
LCD
PRN12 PRN11 PRN10
VRN03 VRN02 VRN01 VRN00
VRN14 VRN13 VRN12 VRN11 VRN10
SSD2123
Rev 0.30
P 41/66
Jan 2008
Solomon Systech
11.1 Structure of Grayscale Amplifier
Below figure indicates the structure of the grayscale amplifier. It determines 8 levels (VIN0-VIN7) by the gradient
adjuster and the micro adjustment register. Also, dividing these levels with ladder resistors generates V0 to V255.
Gradient
adjustment register
VLCD255
PRP0
3
PRP1
Amplitude
adjustment register
Micro adjustment register
PKP0
3
3
PKP1
PKP2
PKP3
3
3
3
PKP4
3
PKP5
VRP0
3
4
VRP1
5
VINP0
V0
VINP1
8 to 1
selector
V4
:
V18
VINP2
8 to 1
selector
VINP3
VINP4
8 to 1
selector
Grayscale Amplifier
:
8 to 1
selector
Ladder resistor
V32
V56
V80
:
V118
V156
:
V190
VINP5
8 to 1
selector
V224
:
V238
8 to 1
selector
VINP6
V252
V253
VINP7
*
GND
SSD2123
Rev 0.30
V255
Individual ladder resistors are used for positive and
negative polarity.
P 42/66
Jan 2008
Solomon Systech
Ladder resistor for negative polarity
Ladder resistor for positive polarity
VLCD255
5R
4R
0 to 28R
VRHP
1R
5R
RP1
RP2
RP3
RP4
RP5
RP6
RP7
1R
16R
RP23
1R
RP24
RP25
RP26
RP27
RP28
RP29
RP30
1R
0 to 28R
VRLP
4R
5R
0 to 31R
VRP1 8R
PKP0[2:0]
KVP1
KVP2
KVP3
KVP4
KVP5 8 to 1
KVP6 selector
KVP7
KVP8
PRP0[2:0]
KVP9
RP8
KVP10
RP9
KVP11
RP10 KVP12
RP11 KVP13 8 to 1
RP12 KVP14 selector
RP13 KVP15
RP14 KVP16
RP15
RP31
RP32
RP33
RP34
RP35
RP36
RP37
RP38
VINP1
PKP1[2:0]
VINP2
PKP2[2:0]
KVP17
KVP18
KVP19
KVP20
KVP21 8 to 1
KVP22 selector
KVP23
KVP24
VINP3
PKP3[2:0]
KVP25
KVP26
KVP27
KVP28
KVP29 8 to 1
KVP30 selector
KVP31
KVP32
VINP4
PKP4[2:0]
KVP33
KVP34
KVP35
KVP36
KVP37 8 to 1
KVP38 selector
KVP39
KVP40
PRP1[2:0]
KVP41
RP39 KVP42
RP40 KVP43
RP41 KVP44
RP42 KVP45 8 to 1
RP43 KVP46 selector
RP44 KVP47
RP45 KVP48
RP46
VRN0[3:0]
VRN0
KVP0
RP0
RP16
RP17
RP18
RP19
RP20
RP21
RP22
5R
VINP0
VRP0[3:0]
0 to 30R
VRP0
VINP5
PKP5[2:0]
VINP6
VINP7
5R
4R
0 to 28R
VRHN
1R
5R
RP47
RN1
RN2
RN3
RN4
RN5
RN6
RN7
RN15
1R
16R
RN23
1R
RN24
RN25
RN26
RN27
RN28
RN29
RN30
5R
1R
0 to 28R
VRLN
4R
5R
KVN1
KVN2
KVN3
KVN4
KVN5 8 to 1
KVN6 selector
KVN7
KVN8
PRN0[2:0]
KVN9
RN8 KVN10
RN9 KVN11
RN10 KVN12
RN11 KVN13 8 to 1
RN12 KVN14 selector
RN13 KVN15
RN14 KVN16
RN16
RN17
RN18
RN19
RN20
RN21
RN22
0 to 31R
VRN1 8R
VRP1[4:0]
KVN0
RN0
RN31
RN32
RN33
RN34
RN35
RN36
RN37
RN38
VINN0
PKN0[2:0]
VINN1
PKN1[2:0]
VINN2
PKN2[2:0]
KVN17
KVN18
KVN19
KVN20
KVN21 8 to 1
KVN22 selector
KVN23
KVN24
VINN3
PKN3[2:0]
KVN25
KVN26
KVN27
KVN28
KVN29 8 to 1
KVN30 selector
KVN31
KVN32
VINN4
PKN4[2:0]
KVN33
KVN34
KVN35
KVN36
KVN37 8 to 1
KVN38 selector
KVN39
KVN40
PRN1[2:0]
KVN41
RN39 KVN42
RN40 KVN43
RN41 KVN44
RN42 KVN45 8 to 1
RN43 KVN46 selector
RN44 KVN47
RN45 KVN48
RN46
VINN5
PKN5[2:0]
VINN6
VINN7
VRN1[4:0]
RN47
GND
SSD2123
Rev 0.30
P 43/66
Jan 2008
Solomon Systech
11.2 Gamma Adjustment Register
This block is the register to set up the grayscale voltage adjusting to the gamma specification of the LCD panel. This
register can independent set up to positive/negative polarities and there are three types of register groups to adjust
gradient, amplitude, and micro-adjustment on number of the grayscale, characteristics of the grayscale voltage. (Using
the same setting for Reference-value and R.G.B.) Following graphics indicates the operation of each adjusting register.
Grayscale Number
11.2.1
Micro adjustment
Grayscale Voltage
Amplitude adjustment
Grayscale Voltage
Grayscale Voltage
Gradient adjustment
Grayscale Number
Grayscale Number
Gradient adjusting register
The gradient-adjusting resistor is to adjust around middle gradient, specification of the grayscale number and the
grayscale voltage without changing the dynamic range. To accomplish the adjustment, it controls the variable resistors in
the middle of the ladder resistor by registers (PRP(N)0 / PRP(N)1) for the grayscale voltage generator. Also, there is an
independent resistor on the positive/negative polarities in order for corresponding to asymmetry drive.
11.2.2
Amplitude adjusting register
The amplitude-adjusting resistor is to adjust amplitude of the grayscale voltage. To accomplish the adjustment, it
controls the variable resistors in the boundary of the ladder resistor by registers (VRP(N)0 / VRP(N)1) for the grayscale
voltage generator. Also, there is an independent resistor on the positive/negative polarities as well as the gradientadjusting resistor.
11.2.3
Micro adjusting register
The micro-adjusting register is to make subtle adjustment of the grayscale voltage level. To accomplish the adjustment, it
controls each reference voltage level by the 8 to 1 selector towards the 8-level reference voltage generated from the
ladder resistor. Also, there is an independent resistor on the positive/negative polarities as well as other adjusting
resistors.
SSD2123
Rev 0.30
P 44/66
Jan 2008
Solomon Systech
11.3
Ladder Resistor / 8 to 1 selector
This block outputs the reference voltage of the grayscale voltage. There are two ladder resistors including the variable
resistor and the 8 to 1 selector selecting voltage generated by the ladder resistor. The gamma registers control the
variable resistors and 8 to 1 selector resistors.
Variable Resistor
There are 3 types of the variable resistors that are for the gradient and amplitude adjustment. The resistance is set by the
resistor (PRP(N)0 / PRP(N)1) and (VRP(N)0 / VRP(N)1) as below.
PRP(N)[0:1]
000
001
010
011
100
101
110
111
Resistance
0R
4R
8R
12R
16R
20R
24R
28R
VRP(N)0
0000
0001
0010
Resistance
0R
2R
4R
VRP(N)1
00000
00001
00010
:
Step = 2R
:
1110
1111
Resistance
0R
1R
2R
:
Step = 1R
:
28R
30R
11110
11111
30R
31R
8 to 1 selecter
In the 8 to 1 selector, a reference voltage VIN can be selected from the levels which are generated by the ladder resistors.
There are six types of reference voltage (VIN1 to VIN6) and totally 48 divided voltages can be selected in one ladder
resistor. Following figure explains the relationship between the micro-adjusting register and the selecting voltage.
Registor
PKP[2:0]
000
001
010
011
100
101
110
111
SSD2123
VINP1
KVP1
KVP2
KVP3
KVP4
KVP5
KVP6
KVP7
KVP8
Postive polarity
Selected voltage
VINP2 VINP3 VINP4
KVP9 KVP17 KVP25
KVP10 KVP18 KVP26
KVP11 KVP19 KVP27
KVP12 KVP20 KVP28
KVP13 KVP21 KVP29
KVP14 KVP22 KVP30
KVP15 KVP23 KVP31
KVP16 KVP24 KVP32
Rev 0.30
P 45/66
VINP5
KVP33
KVP34
KVP35
KVP36
KVP37
KVP38
KVP39
KVP40
Jan 2008
VINP6
KVP41
KVP42
KVP43
KVP44
KVP45
KVP46
KVP47
KVP48
Registor
PKN[2:0]
000
001
010
011
100
101
110
111
Negative polarity
Selected voltage
VINN1 VINN2 VINN3 VINN4
KVN1 KVN9 KVN17 KVN25
KVN2 KVN10 KVN18 KVN26
KVN3 KVN11 KVN19 KVN27
KVN4 KVN12 KVN20 KVN28
KVN5 KVN13 KVN21 KVN29
KVN6 KVN14 KVN22 KVN30
KVN7 KVN15 KVN23 KVN31
KVN8 KVN16 KVN24 KVN32
VINN5
KVN33
KVN34
KVN35
KVN36
KVN37
KVN38
KVN39
KVN40
VINN6
KVN41
KVN42
KVN43
KVN44
KVN45
KVN46
KVN47
KVN48
Solomon Systech
Grayscale
voltage
V0
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
V32
V33
V34
V35
V36
V37
V38
V39
V40
V41
V42
SSD2123
Formula
VINP(N)0
(V0-V4)*(30/40)+V4
(V0-V4)*(20/40)+V4
(V0-V4)*(10/40)+V4
VINP(N)1
(V4-V32)*(174/192)+V32
(V4-V32)*(156/192)+V32
(V4-V32)*(138/192)+V32
(V4-V32)*(120/192)+V32
(V4-V32)*(113/192)+V32
(V4-V32)*(106/192)+V32
(V4-V32)*(99/192)+V32
(V4-V32)*(92/192)+V32
(V4-V32)*(85/192)+V32
(V4-V32)*(78/192)+V32
(V4-V32)*(71/192)+V32
(V4-V32)*(64/192)+V32
(V4-V32)*(60/192)+V32
(V4-V32)*(56/192)+V32
(V4-V32)*(52/192)+V32
(V4-V32)*(48/192)+V32
(V4-V32)*(44/192)+V32
(V4-V32)*(40/192)+V32
(V4-V32)*(36/192)+V32
(V4-V32)*(32/192)+V32
(V4-V32)*(28/192)+V32
(V4-V32)*(24/192)+V32
(V4-V32)*(20/192)+V32
(V4-V32)*(16/192)+V32
(V4-V32)*(12/192)+V32
(V4-V32)*(8/192)+V32
(V4-V32)*(4/192)+V32
VINP(N)2
(V32-V80)*(47/48)+V80
(V32-V80)*(46/48)+V80
(V32-V80)*(45/48)+V80
(V32-V80)*(44/48)+V80
(V32-V80)*(43/48)+V80
(V32-V80)*(42/48)+V80
(V32-V80)*(41/48)+V80
(V32-V80)*(40/48)+V80
(V32-V80)*(39/48)+V80
(V32-V80)*(38/48)+V80
Rev 0.30
P 46/66
Grayscale
voltage
V43
V44
V45
V46
V47
V48
V49
V50
V51
V52
V53
V54
V55
V56
V57
V58
V59
V60
V61
V62
V63
V64
V65
V66
V67
V68
V69
V70
V71
V72
V73
V74
V75
V76
V77
V78
V79
V80
V81
V82
V83
V84
V85
Jan 2008
Formula
(V32-V80)*(37/48)+V80
(V32-V80)*(36/48)+V80
(V32-V80)*(35/48)+V80
(V32-V80)*(34/48)+V80
(V32-V80)*(33/48)+V80
(V32-V80)*(32/48)+V80
(V32-V80)*(31/48)+V80
(V32-V80)*(30/48)+V80
(V32-V80)*(29/48)+V80
(V32-V80)*(28/48)+V80
(V32-V80)*(27/48)+V80
(V32-V80)*(26/48)+V80
(V32-V80)*(25/48)+V80
(V32-V80)*(24/48)+V80
(V32-V80)*(23/48)+V80
(V32-V80)*(22/48)+V80
(V32-V80)*(21/48)+V80
(V32-V80)*(20/48)+V80
(V32-V80)*(19/48)+V80
(V32-V80)*(18/48)+V80
(V32-V80)*(17/48)+V80
(V32-V80)*(16/48)+V80
(V32-V80)*(15/48)+V80
(V32-V80)*(14/48)+V80
(V32-V80)*(13/48)+V80
(V32-V80)*(12/48)+V80
(V32-V80)*(11/48)+V80
(V32-V80)*(10/48)+V80
(V32-V80)*(9/48)+V80
(V32-V80)*(8/48)+V80
(V32-V80)*(7/48)+V80
(V32-V80)*(6/48)+V80
(V32-V80)*(5/48)+V80
(V32-V80)*(4/48)+V80
(V32-V80)*(3/48)+V80
(V32-V80)*(2/48)+V80
(V32-V80)*(1/48)+V80
VINP(N)3
(V80-V176)*(95/96)+V176
(V80-V176)*(94/96)+V176
(V80-V176)*(93/96)+V176
(V80-V176)*(92/96)+V176
(V80-V176)*(91/96)+V176
Grayscale
voltage
V86
V87
V88
V89
V90
V91
V92
V93
V94
V95
V96
V97
V98
V99
V100
V101
V102
V103
V104
V105
V106
V107
V108
V109
V110
V111
V112
V113
V114
V115
V116
V117
V118
V119
V120
V121
V122
V123
V124
V125
V126
V127
V128
Formula
(V80-V176)*(90/96)+V176
(V80-V176)*(89/96)+V176
(V80-V176)*(88/96)+V176
(V80-V176)*(87/96)+V176
(V80-V176)*(86/96)+V176
(V80-V176)*(85/96)+V176
(V80-V176)*(84/96)+V176
(V80-V176)*(83/96)+V176
(V80-V176)*(82/96)+V176
(V80-V176)*(81/96)+V176
(V80-V176)*(80/96)+V176
(V80-V176)*(79/96)+V176
(V80-V176)*(78/96)+V176
(V80-V176)*(77/96)+V176
(V80-V176)*(76/96)+V176
(V80-V176)*(75/96)+V176
(V80-V176)*(74/96)+V176
(V80-V176)*(73/96)+V176
(V80-V176)*(72/96)+V176
(V80-V176)*(71/96)+V176
(V80-V176)*(70/96)+V176
(V80-V176)*(69/96)+V176
(V80-V176)*(68/96)+V176
(V80-V176)*(67/96)+V176
(V80-V176)*(66/96)+V176
(V80-V176)*(65/96)+V176
(V80-V176)*(64/96)+V176
(V80-V176)*(63/96)+V176
(V80-V176)*(62/96)+V176
(V80-V176)*(61/96)+V176
(V80-V176)*(60/96)+V176
(V80-V176)*(59/96)+V176
(V80-V176)*(58/96)+V176
(V80-V176)*(57/96)+V176
(V80-V176)*(56/96)+V176
(V80-V176)*(55/96)+V176
(V80-V176)*(54/96)+V176
(V80-V176)*(53/96)+V176
(V80-V176)*(52/96)+V176
(V80-V176)*(51/96)+V176
(V80-V176)*(50/96)+V176
(V80-V176)*(49/96)+V176
(V80-V176)*(48/96)+V176
Solomon Systech
Grayscale
voltage
V129
V130
V131
V132
V133
V134
V135
V136
V137
V138
V139
V140
V141
V142
V143
V144
V145
V146
V147
V148
V149
V150
V151
V152
V153
V154
V155
V156
V157
V158
V159
V160
V161
V162
V163
V164
V165
V166
V167
V168
V169
V170
V171
SSD2123
Formula
(V80-V176)*(47/96)+V176
(V80-V176)*(46/96)+V176
(V80-V176)*(45/96)+V176
(V80-V176)*(44/96)+V176
(V80-V176)*(43/96)+V176
(V80-V176)*(42/96)+V176
(V80-V176)*(41/96)+V176
(V80-V176)*(40/96)+V176
(V80-V176)*(39/96)+V176
(V80-V176)*(38/96)+V176
(V80-V176)*(37/96)+V176
(V80-V176)*(36/96)+V176
(V80-V176)*(35/96)+V176
(V80-V176)*(34/96)+V176
(V80-V176)*(33/96)+V176
(V80-V176)*(32/96)+V176
(V80-V176)*(31/96)+V176
(V80-V176)*(30/96)+V176
(V80-V176)*(29/96)+V176
(V80-V176)*(28/96)+V176
(V80-V176)*(27/96)+V176
(V80-V176)*(26/96)+V176
(V80-V176)*(25/96)+V176
(V80-V176)*(24/96)+V176
(V80-V176)*(23/96)+V176
(V80-V176)*(22/96)+V176
(V80-V176)*(21/96)+V176
(V80-V176)*(20/96)+V176
(V80-V176)*(19/96)+V176
(V80-V176)*(18/96)+V176
(V80-V176)*(17/96)+V176
(V80-V176)*(16/96)+V176
(V80-V176)*(15/96)+V176
(V80-V176)*(14/96)+V176
(V80-V176)*(13/96)+V176
(V80-V176)*(12/96)+V176
(V80-V176)*(11/96)+V176
(V80-V176)*(10/96)+V176
(V80-V176)*(9/96)+V176
(V80-V176)*(8/96)+V176
(V80-V176)*(7/96)+V176
(V80-V176)*(6/96)+V176
(V80-V176)*(5/96)+V176
Rev 0.30
P 47/66
Grayscale
voltage
V172
V173
V174
V175
V176
V177
V178
V179
V180
V181
V182
V183
V184
V185
V186
V187
V188
V189
V190
V191
V192
V193
V194
V195
V196
V197
V198
V199
V200
V201
V202
V203
V204
V205
V206
V207
V208
V209
V210
V211
V212
V213
V214
Jan 2008
Formula
(V80-V176)*(4/96)+V176
(V80-V176)*(3/96)+V176
(V80-V176)*(2/96)+V176
(V80-V176)*(1/96)+V176
VINP(N)4
(V176-V224)*(47/48)+V224
(V176-V224)*(46/48)+V224
(V176-V224)*(45/48)+V224
(V176-V224)*(44/48)+V224
(V176-V224)*(43/48)+V224
(V176-V224)*(42/48)+V224
(V176-V224)*(41/48)+V224
(V176-V224)*(40/48)+V224
(V176-V224)*(39/48)+V224
(V176-V224)*(38/48)+V224
(V176-V224)*(37/48)+V224
(V176-V224)*(36/48)+V224
(V176-V224)*(35/48)+V224
(V176-V224)*(34/48)+V224
(V176-V224)*(33/48)+V224
(V176-V224)*(32/48)+V224
(V176-V224)*(31/48)+V224
(V176-V224)*(30/48)+V224
(V176-V224)*(29/48)+V224
(V176-V224)*(28/48)+V224
(V176-V224)*(27/48)+V224
(V176-V224)*(26/48)+V224
(V176-V224)*(25/48)+V224
(V176-V224)*(24/48)+V224
(V176-V224)*(23/48)+V224
(V176-V224)*(22/48)+V224
(V176-V224)*(21/48)+V224
(V176-V224)*(20/48)+V224
(V176-V224)*(19/48)+V224
(V176-V224)*(18/48)+V224
(V176-V224)*(17/48)+V224
(V176-V224)*(16/48)+V224
(V176-V224)*(15/48)+V224
(V176-V224)*(14/48)+V224
(V176-V224)*(13/48)+V224
(V176-V224)*(12/48)+V224
(V176-V224)*(11/48)+V224
(V176-V224)*(10/48)+V224
Grayscale
voltage
V215
V216
V217
V218
V219
V220
V221
V222
V223
V224
V225
V226
V227
V228
V229
V230
V231
V232
V233
V234
V235
V236
V237
V238
V239
V240
V241
V242
V243
V244
V245
V246
V247
V248
V249
V250
V251
V252
V253
V254
V255
Formula
(V176-V224)*(9/48)+V224
(V176-V224)*(8/48)+V224
(V176-V224)*(7/48)+V224
(V176-V224)*(6/48)+V224
(V176-V224)*(5/48)+V224
(V176-V224)*(4/48)+V224
(V176-V224)*(3/48)+V224
(V176-V224)*(2/48)+V224
(V176-V224)*(1/48)+V224
VINP(N)5
(V224-V252)*(188/192)+V252
(V224-V252)*(184/192)+V252
(V224-V252)*(180/192)+V252
(V224-V252)*(176/192)+V252
(V224-V252)*(172/192)+V252
(V224-V252)*(168/192)+V252
(V224-V252)*(164/192)+V252
(V224-V252)*(160/192)+V252
(V224-V252)*(156/192)+V252
(V224-V252)*(152/192)+V252
(V224-V252)*(148/192)+V252
(V224-V252)*(144/192)+V252
(V224-V252)*(140/192)+V252
(V224-V252)*(136/192)+V252
(V224-V252)*(132/192)+V252
(V224-V252)*(128/192)+V252
(V224-V252)*(121/192)+V252
(V224-V252)*(114/192)+V252
(V224-V252)*(107/192)+V252
(V224-V252)*(100/192)+V252
(V224-V252)*(93/192)+V252
(V224-V252)*(86/192)+V252
(V224-V252)*(79/192)+V252
(V224-V252)*(72/192)+V252
(V224-V252)*(54/192)+V252
(V224-V252)*(36/192)+V252
(V224-V252)*(18/192)+V252
VINP(N)6
(V252-V255)*(20/30)+V255
(V252-V255)*(10/30)+V255
VINP(N)7
Solomon Systech
Reference voltage of positive polarity:
Micr0-adjusting
rgister
-KVP0
VLCD255 - ΔV x VRP0 / SUMRP
PKP0[2:0] = “000”
KVP1
VLCD255 - ΔV x (VRP0 + 5R) / SUMRP
PKP0[2:0] = “001”
KVP2
VLCD255 - ΔV x (VRP0 + 9R) / SUMRP
PKP0[2:0] = “010”
KVP3
VLCD255 - ΔV x (VRP0 + 13R) / SUMRP
PKP0[2:0] = “011”
KVP4
VLCD255 - ΔV x (VRP0 + 17R) / SUMRP
PKP0[2:0] = “100”
KVP5
VLCD255 - ΔV x (VRP0 + 21R) / SUMRP
PKP0[2:0] = “101”
VLCD255 - ΔV x (VRP0 + 25R) / SUMRP
KVP6
PKP0[2:0] = “110”
KVP7
VLCD255 - ΔV x (VRP0 + 29R) / SUMRP
PKP0[2:0] = “111”
KVP8
VLCD255 - ΔV x (VRP0 + 33R) / SUMRP
PKP1[2:0] = “000”
KVP9
VLCD255 - ΔV x (VRP0 + 33R + VRHP) / SUMRP
PKP1[2:0] = “001”
KVP10
VLCD255 - ΔV x (VRP0 + 34R + VRHP) / SUMRP
PKP1[2:0] = “010”
KVP11
VLCD255 - ΔV x (VRP0 + 35R + VRHP) / SUMRP
PKP1[2:0] = “011”
KVP12
VLCD255 - ΔV x (VRP0 + 36R + VRHP) / SUMRP
PKP1[2:0] = “100”
KVP13
VLCD255 - ΔV x (VRP0 + 37R + VRHP) / SUMRP
PKP1[2:0] = “101”
KVP14
VLCD255 - ΔV x (VRP0 + 38R + VRHP) / SUMRP
PKP1[2:0] = “110”
KVP15
VLCD255 - ΔV x (VRP0 + 39R + VRHP) / SUMRP
PKP1[2:0] = “111”
KVP16
VLCD255 - ΔV x (VRP0 + 40R + VRHP) / SUMRP
PKP2[2:0] = “000”
KVP17
VLCD255 - ΔV x (VRP0 + 45R + VRHP) / SUMRP
PKP2[2:0] = “001”
KVP18
VLCD255 - ΔV x (VRP0 + 46R + VRHP) / SUMRP
PKP2[2:0] = “010”
KVP19
VLCD255 - ΔV x (VRP0 + 47R + VRHP) / SUMRP
PKP2[2:0] = “011”
KVP20
VLCD255 - ΔV x (VRP0 + 48R + VRHP) / SUMRP
PKP2[2:0] = “100”
KVP21
VLCD255 - ΔV x (VRP0 + 49R + VRHP) / SUMRP
PKP2[2:0] = “101”
KVP22
VLCD255 - ΔV x (VRP0 + 50R + VRHP) / SUMRP
PKP2[2:0] = “110”
KVP23
VLCD255 - ΔV x (VRP0 + 51R + VRHP) / SUMRP
PKP2[2:0] = “111”
KVP24
VLCD255 - ΔV x (VRP0 + 52R + VRHP) / SUMRP
PKP3[2:0] = “000”
KVP25
VLCD255 - ΔV x (VRP0 + 68R + VRHP) / SUMRP
PKP3[2:0] = “001”
KVP26
VLCD255 - ΔV x (VRP0 + 69R + VRHP) / SUMRP
PKP3[2:0] = “010”
KVP27
VLCD255 - ΔV x (VRP0 + 70R + VRHP) / SUMRP
PKP3[2:0] = “011”
KVP28
VLCD255 - ΔV x (VRP0 + 71R + VRHP) / SUMRP
PKP3[2:0] = “100”
KVP29
VLCD255 - ΔV x (VRP0 + 72R + VRHP) / SUMRP
PKP3[2:0] = “101”
KVP30
VLCD255 - ΔV x (VRP0 + 73R + VRHP) / SUMRP
PKP3[2:0] = “110”
KVP31
VLCD255 - ΔV x (VRP0 + 74R + VRHP) / SUMRP
PKP3[2:0] = “111”
KVP32
VLCD255 - ΔV x (VRP0 + 75R + VRHP) / SUMRP
PKP4[2:0] = “000”
KVP33
VLCD255 - ΔV x (VRP0 + 80R + VRHP) / SUMRP
PKP4[2:0] = “001”
KVP34
VLCD255 - ΔV x (VRP0 + 81R + VRHP) / SUMRP
PKP4[2:0] = “010”
KVP35
VLCD255 - ΔV x (VRP0 + 82R + VRHP) / SUMRP
PKP4[2:0] = “011”
KVP36
VLCD255 - ΔV x (VRP0 + 83R + VRHP) / SUMRP
PKP4[2:0] = “100”
KVP37
VLCD255 - ΔV x (VRP0 + 84R + VRHP) / SUMRP
PKP4[2:0] = “101”
KVP38
VLCD255 - ΔV x (VRP0 + 85R + VRHP) / SUMRP
PKP4[2:0] = “110”
KVP39
VLCD255 - ΔV x (VRP0 + 86R + VRHP) / SUMRP
PKP4[2:0] = “111”
KVP40
VLCD255 - ΔV x (VRP0 + 87R + VRHP) / SUMRP
PKP5[2:0] = “000”
KVP41
VLCD255 - ΔV x (VRP0 + 87R + VRHP + VRLP) / SUMRP
PKP5[2:0] = “001”
KVP42
VLCD255 - ΔV x (VRP0 + 91R + VRHP + VRLP) / SUMRP
PKP5[2:0] = “010”
KVP43
VLCD255 - ΔV x (VRP0 + 91R + VRHP + VRLP) / SUMRP
PKP5[2:0] = “011”
KVP44
VLCD255 - ΔV x (VRP0 + 99R + VRHP + VRLP) / SUMRP
PKP5[2:0] = “100”
KVP45
VLCD255 - ΔV x (VRP0 + 103R + VRHP + VRLP) / SUMRP
PKP5[2:0] = “101”
KVP46
VLCD255 - ΔV x (VRP0 + 107R + VRHP + VRLP) / SUMRP
PKP5[2:0] = “110”
KVP47
VLCD255 - ΔV x (VRP0 + 111R + VRHP + VRLP) / SUMRP
PKP5[2:0] = “111”
KVP48
VLCD255 - ΔV x (VRP0 + 115R + VRHP + VRLP) / SUMRP
-KVP49
VLCD255 - ΔV x (VRP0 + 120R + VRHP + VRLP) / SUMRP
SUMRP: Total of the positive polarity ladder resistance = 128R + VRHP + VRLP + VRP0 + VRP1
ΔV: Voltage difference between VLCD255 and of GND.
Reference
SSD2123
Formula
Rev 0.30
P 48/66
Jan 2008
Reference voltage
VINP0
VINP1
VINP2
VINP3
VINP4
VINP5
VINP6
VINP7
Solomon Systech
Reference voltage of negative polarity:
Reference
KVN0
KVN1
KVN2
KVN3
KVN4
KVN5
KVN6
KVN7
KVN8
KVN9
KVN10
KVN11
KVN12
KVN13
KVN14
KVN15
KVN16
KVN17
KVN18
KVN19
KVN20
KVN21
KVN22
KVN23
KVN24
KVN25
KVN26
KVN27
KVN28
KVN29
KVN30
KVN31
KVN32
KVN33
KVN34
KVN35
KVN36
KVN37
KVN38
KVN39
KVN40
KVN41
KVN42
KVN43
KVN44
KVN45
KVN46
KVN47
KVN48
KVN49
Formula
VLCD255 - ΔV x VRN0 / SUMRN
VLCD255 - ΔV x (VRN0 + 5R) / SUMRN
VLCD255 - ΔV x (VRN0 + 9R) / SUMRN
VLCD255 - ΔV x (VRN0 + 13R) / SUMRN
VLCD255 - ΔV x (VRN0 + 17R) / SUMRN
VLCD255 - ΔV x (VRN0 + 21R) / SUMRN
VLCD255 - ΔV x (VRN0 + 25R) / SUMRN
VLCD255 - ΔV x (VRN0 + 29R) / SUMRN
VLCD255 - ΔV x (VRN0 + 33R) / SUMRN
VLCD255 - ΔV x (VRN0 + 33R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 34R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 35R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 36R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 37R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 38R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 39R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 40R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 45R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 46R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 47R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 48R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 49R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 50R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 51R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 52R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 68R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 69R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 70R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 71R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 72R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 73R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 74R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 75R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 80R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 81R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 82R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 83R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 84R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 85R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 86R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 87R + VRHN) / SUMRN
VLCD255 - ΔV x (VRN0 + 87R + VRHN + VRLN) / SUMRN
VLCD255 - ΔV x (VRN0 + 91R + VRHN + VRLN) / SUMRN
VLCD255 - ΔV x (VRN0 + 95R + VRHN + VRLN) / SUMRN
VLCD255 - ΔV x (VRN0 + 99R + VRHN + VRLN) / SUMRN
VLCD255 - ΔV x (VRN0 + 103R + VRHN + VRLN) / SUMRN
VLCD255 - ΔV x (VRN0 + 107R + VRHN + VRLN) / SUMRN
VLCD255-ΔV x (VRN0 + 111R + VRHN + VRLN) / SUMRN
VLCD255 - ΔV x (VRN0 + 115R + VRHN + VRLN) / SUMRN
VLCD255 - ΔV x (VRN0 + 120R + VRHN + VRLN) / SUMRN
Micr0-adjusting rgister
-PKN0[2:0] = “000”
PKN0[2:0] = “001”
PKN0[2:0] = “010”
PKN0[2:0] = “011”
PKN0[2:0] = “100”
PKN0[2:0] = “101”
PKN0[2:0] = “110”
PKN0[2:0] = “111”
PKN1[2:0] = “000”
PKN1[2:0] = “001”
PKN1[2:0] = “010”
PKN1[2:0] = “011”
PKN1[2:0] = “100”
PKN1[2:0] = “101”
PKN1[2:0] = “110”
PKN1[2:0] = “111”
PKN2[2:0] = “000”
PKN2[2:0] = “001”
PKN2[2:0] = “010”
PKN2[2:0] = “011”
PKN2[2:0] = “100”
PKN2[2:0] = “101”
PKN2[2:0] = “110”
PKN2[2:0] = “111”
PKN3[2:0] = “000”
PKN3[2:0] = “001”
PKN3[2:0] = “010”
PKN3[2:0] = “011”
PKN3[2:0] = “100”
PKN3[2:0] = “101”
PKN3[2:0] = “110”
PKN3[2:0] = “111”
PKN4[2:0] = “000”
PKN4[2:0] = “001”
PKN4[2:0] = “010”
PKN4[2:0] = “011”
PKN4[2:0] = “100”
PKN4[2:0] = “101”
PKN4[2:0] = “110”
PKN4[2:0] = “111”
PKN5[2:0] = “000”
PKN5[2:0] = “001”
PKN5[2:0] = “010”
PKN5[2:0] = “011”
PKN5[2:0] = “100”
PKN5[2:0] = “101”
PKN5[2:0] = “110”
PKN5[2:0] = “111”
--
Reference voltage
VINN0
VINN1
VINN2
VINN3
VINN4
VINN5
VINN6
VINN7
SUMRN: Total of the negative polarity ladder resistance = 128R + VRHN + VRLN + VRN0 + VRN1
ΔV: Voltage difference between VLCD255 and of GND.
SSD2123
Rev 0.30
P 49/66
Jan 2008
Solomon Systech
12 Block Function Description
Serial Interface
Serial Interface – 4-wires (8 bits)
The clock synchronized serial peripheral interface (SPI) using the chip select line (CSB), serial transfer clock line (SCK),
serial input data (SDI). The serial data transfer starts at the falling edge of CSB input and ends at the rising edge of
CSB.SDC determinate the data of SDI which is register or data.
Transfer starts
Transfer ends
Transfer starts
Transfer ends Transfer starts
Transfer ends
CSB
SDC
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SCK
LSB
MSB
DB DB
6
7
SDI
DB DB DB DB
4
2
5
3
LSB
MSB
Register
LSB
MSB
DB DB DB DB DB DB DB DB
8
9
15 14 13 12 11 10
DB DB
0
1
DB DB DB DB DB DB DB DB
0
6
5
4
3
2
1
7
Data
Data
Example of 4-wires (8 bits)
Frame 1 (Command 10h)
Transfer starts
Frame 2 (Data 5Ah)
Transfer ends
Transfer starts
CSB
CSB
SDC
SDC
SCK
1
2
3
4
5
6
7
SCK
8
1
Transfer ends
2
3
4
5
6
7
8
SDI
SDI
Frame 3 (Data 78h)
Transfer starts
Transfer ends
CSB
SDC
SCK
1
2
3
4
5
6
7
8
SDI
SSD2123
Rev 0.30
P 50/66
Jan 2008
Solomon Systech
Serial Interface – 3-wires (9 bits)
The clock synchronized serial peripheral interface (SPI) using the chip select line (CSB), serial transfer clock line (SCK),
serial input data (SDI). The serial data transfer starts at the falling edge of CSB input and ends at the rising edge of CSB.
DC bit determinate the data of SDI which is register or data.
Transfer starts
Transfer ends
Transfer starts
Transfer ends
Transfer starts
Transfer ends
CSB
1
2
3
SCK
4
5
6
7
8
1
LSB
MSB
2
3
4
5
D
Register
6
7
8
9
1
LSB
MSB
DB DB DB DB DB DB DB DB
0
6
4
2
5
3
1
7
C
SDI
9
2
3
4
5
6
D
8
9
LSB
MSB
DB DB DB DB DB DB DB DB
8
9
15 14 13 12 11 10
7
DB
7
DB DB DB DB DB DB DB
0
6
5
4
3
2
1
Data
Data
Example of 3-wires (9 bits)
Frame 1 (Command 10h)
Transfer starts
Frame 2 (Data 5Ah)
Transfer ends
CSB
Transfer starts
Transfer ends
CSB
1
2
3
4
5
6
7
8
1
9
SCK
SCK
SDI
SDI
2
3
4
5
6
7
8
9
Frame 3 (Data 78h)
Transfer starts
Transfer ends
CSB
1
2
3
4
5
6
7
8
9
SCK
SDI
SSD2123
Rev 0.30
P 51/66
Jan 2008
Solomon Systech
Serial Interface – 3-wires (24 bits)
The clock synchronized serial peripheral interface (SPI) using the chip select line (CSB), serial transfer clock line (SCK),
serial input data (SDI), and serial output data (SDO). The serial data transfer starts at the falling edge of CSB input and
ends at the rising edge of CSB. DC bit determinate the data of SDI which is register or data. RW bit determinate the read
/ write operation.
Write
Transfer starts
Transfer ends
CSB
SCK
SDI
1
2
3
4
5
6
7
8
“0”
“1”
“1”
“1”
“0”
ID
ID
DC
RW
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
LSB
MSB
DB
15
24
DB
0
DC RW
Device ID
code
Index register setting / Instruction,
Start byte
Read
st
1 step read
- Index register
Transfer starts
CSB
SCK
Transfer
1
2
3
4
5
6
7
8
“0”
“1”
“1”
“1”
“0”
ID
ID
C
R
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
LSB
MSB
SDI
DB
15
24
DB
0
DC RW
Device ID
code
Index register setting / Instruction,
Start byte
SDO
Transfer starts
Transfer
CSB
1
2
3
4
5
6
7
8
“0”
“1”
“1”
“1”
“0”
ID
ID
D
R
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
DB
3
DB
2
DB
1
DB
0
SCK
2nd step read
- Data at SDO
LSB
MSB
SDI
Device ID
code
DB
15
DC RW
Index register setting / Instruction,
Start byte
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
SDO
Status read
SSD2123
Rev 0.30
P 52/66
Jan 2008
Solomon Systech
Data Control
The display data and frame position information from the controller is synchronized with the Gate Drive circuit and shift
registered for the Source Driver circuit.
Booster and Regulator Circuit
These two functional blocks generate the voltage of VGH, VGL, VCOM and VLCD255 which are necessary for operating a
TFT LCD.
Shift Register
The shift registers control the direction of line scanning of source and gate.
Data Latches
This block is a series of latches carrying the display signal information. These latches hold the data, which will be fed to
the Source Driver to output the required voltage level.
Reset Circuit
This block is integrated into the Interface Logic which includes Power On Reset circuitry and the hardware reset pin,
RES . Both of these having the same reset function. Once the RES pin receives a negative reset pulse, all internal
circuitry will start to initialize. The minimum pulse width for completing the reset sequence is 10us. The status of the
chip after reset is given in Command Table:
SSD2123
Rev 0.30
P 53/66
Jan 2008
Solomon Systech
13 DC CHARACTERISTICS
DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, TA = -40 to 85oC)
Symbol
Parameter
VDDIO
Power supply pin of IO pins
Isleep1
Isleep2
Booster Reference Supply Voltage
Range (3)
Sleep mode current (VCI pin)
Sleep mode current (VDDIO)
Idp
Operating mode current
VCIM
Negative VCI Output Voltage
VCI
AVDD
VGH
VGL
VCOMH
VCOML
VCOMA
VLCD255
ΔVLCD255
VOH1
VOL1
VIH1
VIL1
IOH
IOL
IOZ
IIL/IIH
CIN
RSON
RGON
RCON
TC
Note1:
Note2:
Note3:
Test Condition
Recommend Operating Voltage
Possible Operating Voltage
Recommend Operating Voltage
Possible Operating Voltage
VDDEXT=VDDIO=1.875V, VCI=2.775V
1
AVDD x 2 primary booster efficiency
Gate driver High Output Voltage
Booster efficiency2
Gate driver Low Output Voltage
VCOM High Output Voltage
VCOM Low Output Voltage
VCOMA
VCOMH - VCOML
VLCD255 Output Voltage3
Max. Source Voltage Variation
Logic High Output Voltage
Logic Low Output Voltage
Logic High Input voltage
Logic Low Input voltage
Logic High Output Current Source
Logic Low Output Current Drain
Logic Output Tri-state Current Drain
Source
Logic Input Current
Logic Pins Input Capacitance
Source drivers output resistance
Gate drivers output resistance
VCOM output resistance
Temperature Coefficient
100pF loading at Source output
VDDEXT=VDDIO=1.875V, VCI=2.775V
No panel loading
No panel loading, ITO for CYP, CYN, AVDD,
VCI and VCHS = 10 Ohm
No panel loading; 4x booster; ITO for CYP,
CYN, AVDD, VCI and VCHS = 10 Ohm
No panel loading; 5x booster; ITO for CYP,
CYN, AVDD, VCI and VCHS = 10 Ohm
No panel loading; 6x booster; ITO for CYP,
CYN, AVDD, VCI and VCHS = 10 Ohm
Iout=-100A
Iout=100A
Vout = VDDIO-0.4V
Vout = 0.4V
Min
Typ
1.6
-
Max
Unit
3.6
V
2.5 or VDDIO
-
3.6
V
-
TBA
TBA
TBA
TBA
uA
uA
-
TBA
TBA
mA
-VCI
-
91
-
6.1
V
%
V
TBA
89.5
-
%
TBA
88.5
-
%
TBA
80
-
%
- 15.0
VCIM+0.5
-2
0.9 * VDDIO
0
0.8 * VDDIO
0
TBA
-
-
-
- 6.0
6.0
6.0
6.0
6.0
2
VDDIO
0.1 * VDDIO
VDDIO
0.2 * VDDIO
TBA
V
V
V
V
V
V
%
V
V
V
V
μA
μA
TBA
-
TBA
μA
TBA
-
5
1
500
200
-0.01
TBA
7.5
-
μA
pF
kΩ
Ω
Ω
%
AVDDX2 efficiency = AVDD /(2 x VCI) x 100%
VGH efficiency = VGH/(VCI x n) x 100%
(where n = booster factor)
AVDD – VLCD255 ≥ 0.1V
SSD2123
Rev 0.30
P 54/66
Jan 2008
Solomon Systech
14 AC CHARACTERISTICS
14.1 Display signal output timing
1 Frame
Row 0 Row 1
Row 271
Row 0 Row 1
VSYNC
HSYNC
Polarity
+ + + - - -
- - -
+ + +
GR0
GG0
GB0
GR1
GG1
GB1
.
.
.
GRn
GGn
GBn
Sm
(All black
pattern)
tvbp
tvfp
tHSYN
tSm
tVSYNC
Figure 14-1: Gate and source output timing (Line inversion)
Symbol
Parameter
tVSYNC
tHSYNC
tSm
tvbp
tvfp
1 / Frame Frequency
1 / Line Frequency
1 / Source Frequency
Delay time between each field
Delay time between each field
SSD2123
Rev 0.30
P 55/66
Jan 2008
Min
Typ
Max
Unit
-
16.7
61.3
20.4
TBD
TBD
-
ms
us
us
us
us
Solomon Systech
Figure 14-2- Example of color filter arrangement
GR0
GG0
GB0
GR1
GG1
GB1
GR2
GG2
GB2
GR3
GG3
GB3
GR268
GG268
GB268
GR269
GG269
GB269
GR270
GG270
GB270
SSD2123
Rev 0.30
P 56/66
Jan 2008
S479
S478
S477
S476
S475
S474
S473
S472
S471
S470
S469
S468
S467
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
GR271
GG271
GB271
Solomon Systech
14.2 SPI Timing
AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDDIO = 1.875V, TA = -40 to 85oC)
Serial Peripheral Interface (SPI)
tvsys
VSYNC
tvsyh
thsys
thsyh
HSYNC
thv
tDOTCLK
DOTCLK
tCKL
tds
tr
tCKH
tdh
Pixel
Data
tr / tf
Figure 14-3- Pixel Clock Timing
Characteristics
DOTCLK Frequency
DOTCLK Period
Vertical Sync Setup Time
Vertical Sync Hold Time
Horizontal Sync Setup Time
Horizontal Sync Hold Time
Phase difference of Sync Signal Falling
Edge
DOTCLK Low Period
DOTCLK High Period
Data Setup Time
Data hold Time
Reset pulse width
Rise / Fall time
Note:
SSD2123
Symbol
fDOTCLK
tDOTCLK
tvsys
tvsyh
thsys
thsyh
Min
-
thv
TBD
Max
TBD
-
-
Units
MHz
nSec
nSec
nSec
nSec
nSec
-
TBD
tDOTCLK
TBD
TBD
TBD
TBD
TBD
TBD
TBD
External clock source must be provided to DOTCLK pin of SSD2123Z. The driver will not operate
if absent of the clocking signal.
Rev 0.30
P 57/66
tCKL
tCKH
tds
tdh
tRES
tr / tf
TBD
TBD
TBD
TBD
TBD
Typ
TBD
TBD
Jan 2008
nSec
nSec
nSec
nSec
uSec
nSec
Solomon Systech
CM
HSYNC
VSYNC
Color
Mode
16.7M color mode
8 color mode
16.7M color mode
Figure 14-4 Color Mode Conversion Timing
Note:
SSD2123
The color mode conversion starts at the first falling edge of VSYNC after stage change of CM.
Rev 0.30
P 58/66
Jan 2008
Solomon Systech
VDDIO
VDDEXT
VCI
RES
SHUT
>1ns
10 us
>1us
DOTCLK
>1 CLK
VGH
< 10 frames
< 10 frames
< 10 frames
VGH
Output
~Vci
Figure 14-5 VGH Output against SHUT & RESB
Note1:
The minimum cycle time of SHUT is 10 + 2 frames.
Note2:
DOTCLK must be provided for boosting of VGH. The above timing diagram assumed voltages and DOTCLK are continuous
supplied after power on.
Note3:
VGH will be forced to VCI at the low stage of RES .
Note4:
The minimum pulse width of RESET is 10us.
SSD2123
Rev 0.30
P 59/66
Jan 2008
Solomon Systech
VCI
VDDIO
VDDEXT
>0ms
RESB
>1ns
SHUT
tp-shut
DOTCLK
tclkHSYNC
1st
10th
VSYNC
tshut-
Display
High
Voltage
tshut-on
Display
ON
Figure 14-6 - Power Up Sequence
Characteristics
VDDEXT / VDDIO on to falling edge of SHUT
DOTCLK
Falling edge of SHUT to LCD power on
Falling edge of SHUT to display start
-- 1 line: 336 clk
-- 1 frame: 244 line
-- DOTCLK = 5.0MHz
SSD2123
Symbol
tp-shut
tclk-shut
tshut-lcd
tshut-on
Min
Max
-
-
Typ
-
TBD
TBD
Units
μsec
clk
msec
frame
-
TBD
-
msec
TBD
TBD
Note1:
It is necessary to input DOTCLK before the falling edge of SHUT.
Note2:
Display starts at 10th falling edge of VSTNC after the falling edge of SHUT.
Rev 0.30
P 60/66
Jan 2008
Solomon Systech
VDD
VDDIO
toff>1us
VCI
>1ns
RES
SHUT
DOTCLK
HSYNC
1st
2nd
VSYNC
tshut-offt
Display
High
Voltage
Display
ON
OFF
Figure 14-7 - Power Down Sequence
Characteristics
Rising edge of SHUT to display off
-- 1 line: 336 clk
-- 1 frame: 244 line
-- DOTCLK = 5.0 MHz
Input-signal-off to VDDEXT / VDDIO off
SSD2123
Symbol
Min
Typ
Max
Units
TBD
-
-
frame
TBD
-
-
msec
TBD
-
-
μsec
tshut-off
toff-vdd
Note1:
DOTCLK must be maintained at lease 2 frames after the rising edge of SHUT.
Note2:
Display become off at the 2nd falling edge of VSTNC after the falling edge of SHUT.
Note3:
If RESET signal is necessary for power down, provide it after the 2-frames-cycle of the SHUT period.
Rev 0.30
P 61/66
Jan 2008
Solomon Systech
First Transmission (Register)
CS
tcss
1
2
3
4
5
6
7
8
9
10
11
12
tcsh
13
14
15
16
17
18
19
20
21
22
23
24
“0”
“0”
“0”
“0”
“0”
“0”
“1”
“0”
“1”
“0”
“0”
“0”
SCL
tsl
SDI
“0”
“1”
“1”
“1”
“0”
ID
DC
tsh
RW
“0”
“0”
“0”
“0”
Second Transmission (Data)
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
“0”
“1”
“1”
“1”
“0”
ID
DC
RW
“0”
“0”
“0”
“1”
“0”
“0”
“1”
“0”
“0”
“1”
“1”
“0”
“0”
“1”
“0”
“0”
tcsd
SCL
SDI
tds
tdh
Figure 14-8 - SPI Interface Timing Diagram & Transaction Example
Characteristics
Serial Clock Frequency
Serial Clock Cycle Time
Clock Low Width
Clock High Width
Chip Select Setup Time
Chip Select Hold Time
Chip Select High Delay Time
Data Setup Time
Data Hold Time
Note1:
SSD2123
Symbol
fclk
tclk
tsl
tsh
tcss
tcsh
tcsd
tds
tdh
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Typ
-
Max
TBD
-
Units
MHz
nsec
nsec
nsec
nsec
nsec
nsec
msec
nsec
SPID pin connected to VSS.
Rev 0.30
P 62/66
Jan 2008
Solomon Systech
14.3 8-bit Serial Interface
HV SYNC Mode
YSYNC
HSYNC
tDEN
DEN Mode
DEN
RR[7:0]
Line
1
Line
2
Line
3
Line
4
Line
5
Line
6
Line
7
Line
8
Line
9
Line
10
Line
11
Line
12
Line
13
Line
14
Line
15
Line
16
Line
n
tV
HV SYNC Mode
HSYNC
DOTCLK
tHBP
DEN Mode
DEN
Without Dummy
RR[7:0]
R0
Invalid Data
G0
B0
R1
G1
B1
R2
G2
B2
R3
G3
B3
R4
G4
B4
R5
G5
B5
R6
G6
B6
Figure 14-9 – 8-bit Serial Interface Timing Diagram & Transaction Example
Characteristics
Serial Clock Frequency
One Line Period
Active Data Period
Horizontal
Horizontal Back Porch
Horizontal Front Porch
One Field Period
Active Line period
Vertical
Vertical Back Porch
Vertical Front Porch
SSD2123
Rev 0.30
P 63/66
Jan 2008
Symbol
1/tDOTCLK
tH
tdata
tHBP
tHFP
tV
tAL
tVBP
tVFP
HV SYNC Mode
Without Dummy
25.62
1536
1440
48
48
278
272
4
2
Units
MHz
tDOTCLK
tDOTCLK
tDOTCLK
tDOTCLK
tH
tH
tH
tH
Solomon Systech
R7
14.4 24-bit RGB Interface
HV SYNC Mode
YSYNC
HSYNC
tDEN
DEN Mode
DEN
RR[7:0]
Line
1
Line
2
Line
3
Line
4
Line
5
Line
6
Line
7
Line
8
Line
9
Line
10
Line
11
Line
12
Line
13
Line
14
Line
15
Line
16
Line
n
GG[7:0]
Line
1
Line
2
Line
3
Line
4
Line
5
Line
6
Line
7
Line
8
Line
9
Line
10
Line
11
Line
12
Line
13
Line
14
Line
15
Line
16
Line
n
BB[7:0]
Line
1
Line
2
Line
3
Line
4
Line
5
Line
6
Line
7
Line
8
Line
9
Line
10
Line
11
Line
12
Line
13
Line
14
Line
15
Line
n
tV
HV SYNC Mode
HSYNC
DOTCLK
tHBP
DEN Mode
DEN
RR[7:0]
Invalid Data
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
GG[7:0]
Invalid Data
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
BB[7:0]
Invalid Data
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
R19
B19
R20
R21
R22
G20
G21
G22
B20
B21
B22
Figure 14-10 – 24-bit Serial Interface Timing Diagram & Transaction Example
Characteristics
Serial Clock Frequency
One Line Period
Active Data Period
Horizontal
Horizontal Back Porch
Horizontal Front Porch
One Field Period
Active Line period
Vertical
Vertical Back Porch
Vertical Front Porch
SSD2123
Rev 0.30
P 64/66
Jan 2008
Symbol
1/tDOTCLK
tH
tdata
tHBP
tHFP
tV
tAL
tVBP
tVFP
HV SYNC Mode
8.54
Units
MHz
512
480
16
16
278
272
4
2
tDOTCLK
tDOTCLK
tDOTCLK
tDOTCLK
tH
tH
tH
tH
Solomon Systech
15 SSD2123Z OUTPUT VOLTAGE RELATIONSHIP
Figure 15-1- LCD Driving Voltage Relationship
VGH
X3
AVDD
VLCD (AVDD – 0.1V max)
VCOMH
VCI
VCOM
Amplitude
VSS
VCOML
VCIM
VGL
Note:
SSD2123
The above voltages level assumed 100% efficiency of the internal booster. There has no voltage drop due to resistance
from ITO trace of the panel.
Rev 0.30
P 65/66
Jan 2008
Solomon Systech
Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including without
limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters,
including “Typical” must be validated for each customer application by the customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the
part.
All Solomon Systech Products complied with six (6) hazardous substances limitation requirement per European Union (EU) “Restriction of
Hazardous Substance (RoHS) Directive (2002/95/EC)” and China standard “电子信息产品污染控制标识要求 (SJ/T11364-2006)” with
control Marking Symbol
. Hazardous Substances test report is available upon requested.
http://www.solomon-systech.com
SSD2123
Rev 0.30
P 66/66
Jan 2008
Solomon Systech