SSM09N90CGW
N-channel Enhancement-mode Power MOSFET
PRODUCT SUMMARY
BVDSS
900V
R DS(ON)
1.4Ω
ID
7.6A
DESCRIPTION
The SSM09N90CGW acheives fast switching performance
with low gate charge without a complex drive circuit. It is
suitable for high voltage applications such as AC/DC
converters and offline power supplies.
The SSM09N90CGW is in a TO-247 (TO-3P) package,
which is widely used for commercial and industrial
applications, where the greater pin spacing is needed
to meet safety specifications. The through-hole package
is suitable for vertical mounting, where a small footprint
is required on the board, and/or an external heatsink is
to be attached.
Pb-free; RoHS-compliant TO-247
G
D
S
TO-247 (suffix W)
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Units
VDS
Drain-source voltage
900
V
VGS
Gate-source voltage
±30
V
ID
Continuous drain current, TC = 25°C
7.6
A
4.8
A
25
A
TC = 100°C
1
IDM
Pulsed drain current
PD
Total power dissipation, TC = 25°C
208
W
Linear derating factor
1.6
W/°C
120
mJ
6
A
3
EAS
Single pulse avalanche energy
IAS
Avalanche current
TSTG
Storage temperature range
-55 to 150
°C
TJ
Operating junction temperature range
-55 to 150
°C
THERMAL CHARACTERISTICS
Symbol
Parameter
Value
Units
RΘ JC
RΘ JA
Maximum thermal resistance, junction-case
0.6
°C/W
Maximum thermal resistance, junction-ambient
40
°C/W
Notes:
1. Pulse width must be limited to avoid exceeding the safe operating area.
2. Pulse width <300us, duty cycle <2%.
3. Starting Tj=25°C, VDD=50V , L=6.8mH , RG=25Ω , IAS=6A.
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SSM09N90CGW
ELECTRICAL CHARACTERISTICS
Symbol
(at Tj = 25°C, unless otherwise specified)
Parameter
Test Conditions
Min.
Typ.
Max. Units
900
-
-
V
BVDSS
Drain-source breakdown voltage
VGS=0V, ID=1mA
∆ BV DSS/∆ Tj
Breakdown voltage temperature coefficient
Reference to 25°C, ID=1mA
-
0.74
-
V/°C
RDS(ON)
Static drain-source on-resistance
VGS=10V, ID=3.6A
-
1.25
1.4
Ω
VGS(th)
Gate threshold voltage
VDS=VGS, ID=250uA
2
-
4
V
gfs
Forward transconductance
VDS=10V, ID=3.6A
-
3.6
-
S
IDSS
Drain-source leakage current
VDS=900V, VGS=0V
-
-
10
uA
VDS=720V ,VGS=0V, Tj = 125°C
-
-
100
uA
VGS=±30V
-
-
±100
nA
ID=7.2A
-
50.7
80
nC
IGSS
Gate-source leakage current
2
Qg
Total gate charge
Qgs
Gate-source charge
VDS=540V
-
12
-
nC
Qgd
Gate-drain ("Miller") charge
VGS=10V
-
16
-
nC
VDS=450V
-
20
-
ns
2
td(on)
Turn-on delay time
tr
Rise time
ID=7.2A
-
16
-
ns
td(off)
Turn-off delay time
RG=6.8Ω , VGS=10V
-
65
-
ns
tf
Fall time
RD=62.5Ω
-
27
-
ns
Ciss
Input capacitance
VGS=0V
-
3097 5000
pF
Coss
Output capacitance
VDS=15V
-
516
-
pF
Crss
Reverse transfer capacitance
f=1.0MHz
-
19
-
pF
Min.
Typ.
IS=7.2A, VGS=0V
-
-
1.5
V
Source-Drain Diode
Symbol
Parameter
2
Test Conditions
Max. Units
VSD
Forward voltage
trr
Reverse-recovery time
IS=7.2A, VGS=0V,
-
673
-
ns
Qrr
Reverse-recovery charge
dI/dt=100A/µs
-
9.6
-
µC
Notes:
1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C.
2.Pulse width <300us, duty cycle <2%.
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SSM09N90CGW
5
10
T C =25 o C
6
4.5V
4
V G =4.0V
2
10V
7.0V
5.0V
4.5V
4
ID , Drain Current (A)
8
ID , Drain Current (A)
T C =150 o C
10V
7.0V
5.0V
3
2
V G =4.0V
1
0
0
0
2
4
6
8
10
12
14
16
18
0
2
V DS , Drain-to-Source Voltage (V)
4
6
8
10
12
14
16
18
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.0
1.2
I D =3.6A
2.5
V G =10V
Normalized RDS(ON)
Normalized BVDSS (V)
1.1
1
2.0
1.5
1.0
0.9
0.5
0.8
0.0
-50
0
50
100
Junction Temperature (
o
-50
150
Fig 3. Normalized BVDSS vs. Junction
150
10
3
VGS(th) (V)
4
IS (A)
100
vs. Junction Temperature
100
T j = 25 o C
1
2
1
0.1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
8/28/2006 Rev.3.1
50
Fig 4. Normalized On-Resistance
Temperature
T j = 150 o C
0
T j , Junction Temperature ( o C)
C)
1.6
-50
0
50
100
150
T j , Junction Temperature ( o C)
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
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SSM09N90CGW
15
f=1.0MHz
10000
I D =7.2A
VGS , Gate to Source Voltage (V)
12
Ciss
V DS =180V
V DS =360V
V DS =540V
1000
C (pF)
9
Coss
6
100
3
Crss
10
0
0
20
40
60
1
80
5
9
Fig 7. Gate Charge Characteristics
17
21
25
29
Fig 8. Typical Capacitance Characteristics
1
Normalized Thermal Response (Rthjc)
100
10
10ms
ID (A)
13
V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
100ms
1
1s
DC
0.1
o
T c =25 C
Single Pulse
DUTY=0.5
0.2
0.1
0.1
0.05
PDM
t
0.02
T
0.01
Duty factor = t/T
Peak Tj = PDM x Rthjc + T C
Single Pulse
0.01
0.01
0.1
1
10
100
1000
10000
0.00001
0.0001
V DS , Drain-to-Source Voltage (V)
Fig 9. Maximum Safe Operating Area
0.001
0.01
0.1
1
10
t , Pulse Width (s)
Fig 10. Effective Transient Thermal Impedance
VG
VDS
90%
QG
10V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Fig 11. Switching Time Waveform
8/28/2006 Rev.3.1
Charge
Q
Fig 12. Gate Charge Waveform
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SSM09N90CGW
PHYSICAL DIMENSIONS - TO-247
E
A
Millimeters
SYMBOLS
φ
MIN
L1
c1
D
b1
L3
b2
A1
L
NOM
MAX
A
4.60
4.80
5.00
A1
1.20
1.40
1.60
b
b1
0.80
1.00
1.20
2.80
3.00
3.20
b2
1.80
2.00
2.20
c
c1
0.55
0.60
0.75
1.45
1.50
1.65
D
19.70
19.90
20.10
E
15.40
15.60
15.80
e
5.15
5.45
5.75
L
16.20
16.50
16.80
L1
3.60
3.80
4.00
L3
3.30
3.50
3.70
1. All dimensions are in millimeters.
2. Dimensions do not include mold protrusions.
c
b
e
PART MARKING - TO-247
PACKING:
Moisture sensitivity level MSL3
1000pcs in tubes packed inside a
moisture barrier bag (MBB).
09N90CGW
PART NUMBER: 09N90CGW = SSM09N90CGW
YWWSSS
DATE/LOT CODE:
Y = last digit of the year
WW = work week (01 -> 52)
SSS = lot code sequence
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
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responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
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