TOSHIBA THM72V2010AG/ATG-60/70 PRELIMINARY 2,097,152 WORDS X 72 BIT DYNAMIC RAM MODULE Description The THM72V2010AG/ATG is a 2,097,152 words by 72 bits dynamic RAM module which assembled 9 pcs of TC51V17800ANJ/ANT on the printed circuit board. This module is optimized for application to the systems which are required high density and large capacity such as main memory of the computers and as image memory systems, and to the others which are requested compact size. Features • 2,097,152 words by 72 bits organization • Fast access time and cycle time • Single power supply of 3.3V±5% • Low Power - 4,095mW MAX. Operating - (THMxxxxxx-60) - 3,470mW MAX. Operating - (THMxxxxxx-70) - 50.4mW MAX. Standby • Read-Modify-Write, CAS before RAS refresh, RAS-only refresh, Hidden refresh, and Fast Page Mode capability • All inputs and outputs TTL compatible • 2,048 refresh cycles/32ms • Package: 168pin Gold Contact THM72V2010AG-x SOJ type THM72V2010ATG-x TSOP type Key Parameters -60 -70 tRAC RAS Access Time 60ns 70ns tAA Column Address Access Time 35ns 40ns CAS Access Time 20ns tCAC -60 -70 PD0 “H” “H” PD1 “L” “L” PD2 “L” “L” PD3 “H” “H” PD4 “L” “L” 25ns PD5 “H” “L” PD6 “H” “H” tRC Cycle Time 110ns 130ns tPC Fast Page Mode Cycle Time 40ns 45ns PD7 “L” “L” ID0 VSS VSS ID1 VSS VSS Note “H”: High Level (buffered) “L”: Low Level (buffered) 1. This technical data may be controlled under U.S. Export Administration Regulations and may be subject to the approval of the U.S. Department of Commerce prior to export. Any export or re-export, directly or indirectly, in contravention of the U.S. Export Administration Regulations is strictly prohibited. 2. LIFE SUPPORT POLICY Toshiba products described in this document are not authorized for use as critical components in life support systems without the written consent of the appropriate officer of Toshiba America, Inc. Life support systems are either systems intended for surgical implant in the body or systems which sustain life. A critical component in any component of a life support system whose failure to perform may cause a malfunction of the life support system, or may affect its safety or effectiveness. 3. The information in this document has been carefully checked and is believed to be reliable; however no responsibility can be assumed for inaccuracies that may not have been caught. All information in this data book is subject to change without prior notice. Furthermore, Toshiba cannot assume responsibility for the use of any license under the patent rights of Toshiba or any third parties. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 1 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 Pin Name B0, A0 ~ 9, A10R Address Inputs DQ0 ~ 71 Data Input/Outputs RAS0, 2 Row Address Strobe CAS0, 4 Column Address Strobe WE0, 2 Write Enable OE0, 2 Output Enable VCC Power (+3.3V) VSS Ground PD0 ~ 7 Presence Detect Pin ID0, 1 ID bit NC No Connection Pin Connection (Top View) 2 1 VSS 85 VSS 18 2 DQ0 86 DQ36 3 DQ1 87 DQ37 4 DQ2 88 5 DQ3 89 6 VCC 7 DQ4 VCC 102 VCC 35 A4 119 A5 52 DQ18 136 DQ54 69 DQ28 153 DQ64 19 DQ14 103 DQ50 36 A6 120 A7 53 DQ19 137 DQ55 70 DQ29 154 DQ65 20 DQ15 104 DQ51 37 A8 121 A9 54 DQ38 21 DQ16 105 DQ52 38 A10R 122 DQ39 22 DQ17 106 DQ53 39 90 VCC 23 VSS 107 VSS 91 DQ40 24 NC 108 NC VSS 138 VSS 71 DQ30 155 DQ66 NC 55 DQ20 139 DQ56 72 DQ31 156 DQ67 NC 123 NC 56 DQ21 140 DQ57 73 40 VCC 124 VCC 57 DQ22 141 DQ58 74 DQ32 158 DQ68 41 NC 125 NC 58 DQ23 142 DQ59 75 DQ33 159 DQ69 VCC 143 VCC VCC 157 VCC 76 DQ34 160 DQ70 8 DQ5 92 DQ41 25 NC 109 NC 42 NC 126 B0 59 9 DQ6 93 DQ42 26 VCC 110 VCC 43 VSS 127 VSS 60 DQ24 144 DQ60 77 DQ35 161 DQ71 OE2 10 DQ7 94 DQ43 27 WE0 111 NC 44 128 NC 61 NC 145 NC 78 VSS 162 VSS 11 DQ8 95 DQ44 28 CAS0 112 NC 45 RAS2 129 NC 62 NC 146 NC 79 PD0 163 PD1 12 VSS 96 VSS 29 13 DQ9 97 DQ45 30 14 DQ10 98 DQ46 31 OE0 115 15 DQ11 99 DQ47 32 VSS 116 113 NC 46 CAS4 130 NC 63 NC 147 NC 80 PD2 164 PD3 RAS0 114 NC 47 NC 131 NC 64 NC 148 NC 81 PD4 165 PD5 NC 48 WE2 132 PDE 65 DQ25 149 DQ61 82 PD6 166 PD7 VSS 49 VCC 133 VCC 66 DQ26 150 DQ62 83 ID0 167 ID1 VCC 168 VCC NC 16 DQ12 100 DQ48 33 A0 117 A1 50 NC 134 NC 67 DQ27 151 DQ63 84 17 DQ13 101 DQ49 34 A2 118 A3 51 NC 135 NC 68 VSS 152 VSS TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM THM72V2010AG/ATG-60/70 Block Diagram PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 3 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 Absolute Maximum Ratings SYMBOL RATING UNIT NOTE Input Voltage -0.3 ~ VCC + 0.3 V 1 VOUT Output Voltage -0.3 ~ VCC + 0.3 V 1 VIN ITEM VCC Power Supply Voltage -0.5 ~ 4.6 V 1 TOPR Operating Temperature 0 ~ 70 °C 1 TSTG Storage Temperature -55 ~ 125 °C 1 Power Dissipation 3.9 W 1 Short Circuit Output Current 50 mA 1 PD IOUT Recommended DC Operating Conditions (Ta = 0 ~ 70°C) SYMBOL PARAMETER MIN TYP MAX UNIT NOTE VCC Supply Voltage 3.13 3.3 3.47 V 2 VIH Input High Voltage 2.2 - VCC + 0.3* V 2 VIL Input Low Voltage -0.3** - 0.8 V 2 *VCC + 1.2V at pulse width ≤ 20ns (pulse width is measured at VCC). **-1.2V at pulse width ≤ 20ns (pulse width is measured at VSS). 4 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM THM72V2010AG/ATG-60/70 DC Electrical Characteristics (VCC = 3.3V± 5%, Ta = 0 ~ 70°C) SYMBOL PARAMETER MIN MAX THMxxxxxx-60 - 1180 THMxxxxxx-70 - 1000 - 19 THMxxxxxx-60 - 1180 THMxxxxxx-70 - 1000 THMxxxxxx-60 - 685 THMxxxxxx-70 - 595 - 14.5 THMxxxxxx-60 - 1180 THMxxxxxx-70 - 1000 UNIT NOTE mA 3, 4 5 |CC1 OPERATING CURRENT Average Power Supply Operating Current (RAS, CS, Address Cycling: tRC=tRC MIN.) |CC2 STANDBY CURRENT Power Supply Standby Current (RAS=CAS=VIH) |CC3 RAS ONLY REFRESH CURRENT Average Power Supply Current, RAS Only Mode (RAS Cycling, CAS=VIH: tRC=tRC MIN.) |CC4 FAST PAGE MODE CURRENT Average Power Supply Current, Fast Page Mode (RAS=VIL, CAS, Address Cycling: tPC=tPC MIN.) |CC5 STANDBY CURRENT Power Supply Standby Current (RAS=CAS=VCC-0.2V) |CC6 CAS BEFORE RAS REFRESH CURRENT Average Power Supply Current, CAS Before RAS Mode (RAS, CAS Cycling: tRC=tRC MIN.) |I (L) INPUT LEAKAGE CURRENT Input Leakage Current, any input (0V≤VIN≤VCC, All Other Pins Not Under Test=0V) -10 10 µA |O (L) OUTPUT LEAKAGE CURRENT (DOUT is disabled, (0V≤VOUT≤VCC) -10 10 µA VOH OUTPUT LEVEL Output “H” Level Voltage (IOUT= -2mA) 2.4 - V VOL OUTPUT LEVEL Output “L” Level Voltage (IOUT=2mA) - 0.4 V mA mA 3, 5 mA 3, 4 5 mA mA 3, 5 Capacitance (VCC = 3.3V±5%, f = 1MHz, Ta = 0 ~ 70°C) SYMBOL PARAMETER MIN MAX CI1 Input Capacitance (B0, A0 ~ A9, A10R) - 13 CI2 Input Capacitance (WE0, 2) - 10 CI3 Input Capacitance (RAS0, 2) - 33 CI4 Input Capacitance (CAS0, 4) - 10 CI5 Input Capacitance (OE0, 2) - 10 CI6 Input Capacitance (PDE) - 13 CDQ I/O Capacitance (DQ0 ~ 71) - 30 PRELIMINARY UNIT PF TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 5 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 Electrical Characteristics and Recommended AC Operating Conditions (VCC = 3.3V±5%, Ta = 0 ~ 70°C) (Notes 6,7,8) THMxxxxxx-60 THMxxxxxx-70 MIN MAX MIN MAX Random Read or Write Cycle Time 110 - 130 - ns Read-Modify-Write Cycle Time 165 - 190 - ns Fast Page Mode Cycle Time 40 - 45 - ns Fast Page Mode Read-Modify-Write Cycle Time 95 - 105 - ns SYMBOL tRC tRMW tPC tPRMW UNIT NOTES tRAC Access Time from RAS - 60 - 70 ns 9, 14, 15 tCAC Access Time from CAS - 20 - 25 ns 9, 14 tAA Access Time from Column Address - 35 - 40 ns 9, 15 tCPA Access Time from CAS Precharge - 40 - 45 - 9 tCLZ CAS to Output in Low-Z 0 - 0 - ns 9 tOFF Output Buffer Turn-off Delay 0 20 0 20 ns 10 Transition Time (Rise and Fall) 3 50 3 50 ns 8 tT 6 PARAMETER tRP RAS Precharge Time 40 - 50 - ns tRAS RAS Pulse Width 60 10,000 70 10,000 ns tRASP RAS Pulse Width (Fast Page Mode) 60 200,000 70 200,000 ns tRSH RAS Hold Time 20 - 25 - ns tRHCP RAS Hold Time from CAS Precharge (Fast Page Mode) 40 - 45 - ns tCSH CAS Hold Time 60 - 70 - ns tCAS CAS Pulse Width 15 10,000 20 10,000 ns tRCD RAS to CAS Delay Time 20 40 20 45 ns 14 tRAD RAS to Column Address Delay Time 15 25 15 30 ns 15 tCRP CAS to RAS Precharge Time 10 - 10 - ns tCP CAS Precharge Time 10 - 10 - ns tASR Row Address Set-Up Time 0 - 0 - ns tRAH Row Address Hold Time 10 - 10 - ns ns tASC Column Address Set-Up Time 0 - 0 - tCAH Column Address Hold Time 10 - 15 - ns tRAL Column Address to RAS Lead Time 35 - 40 - ns tRCS Read Command Set-Up Time 0 - 0 - ns tRCH Read Command Hold Time 0 - 0 - ns 11 tRRH Read Command Hold Time referenced to RAS 10 - 10 - ns 11 tWCH Write Command Hold Time 10 - 15 - ns TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM THM72V2010AG/ATG-60/70 Electrical Characteristics and Recommended AC Operating Conditions (Cont) SYMBOL PARAMETER THMxxxxxx-60 THMxxxxxx-70 MIN MIN MAX MAX UNIT tWP Write Command Pulse Width 10 - 15 - ns tRWL Write Command to RAS Lead Time 20 - 25 - ns tCWL NOTES Write Command to CAS Lead Time 15 - 20 - ns tDS Data Set-Up Time 0 - 0 - ns 12 12 tDH Data Hold Time 15 - 20 - ns tREF Refresh Period - 32 - 32 ms tWCS Write Command Set-Up Time 0 - 0 - ns 13 tCWD CAS to WE Delay Time 50 - 55 - ns 13 tRWD RAS to WE Delay Time 90 - 100 - ns 13 tAWD Column Address to WE Delay Time 65 - 70 - ns 13 tCPWD CAS Precharge to WE Delay Time 70 - 75 - ns 13 tCSR CAS Set-Up Time (CAS before RAS Cycle) 10 - 10 - ns tCHR CAS Hold Time (CAS before RAS Cycle) 10 - 15 - ns tRPC RAS to CAS Precharge Time 5 - 5 - ns tCPT CAS Precharge Time (CAS before RAS Counter Test Cycle) 20 - 30 - ns tROH RAS Hold Time Referenced to OE 15 - 15 - ns tOEA OE Access Time - 20 - 25 ns tOED OE to Data Delay 20 - 20 - ns tOLZ OE to Output in Low-Z 0 - 0 - ns tOEZ Output buffer turn off Delay Time from OE 0 20 0 20 ns tOEH OE Command Hold Time 15 - 15 - ns tODS Output Disable Set-Up Time 0 - 0 - ns tWTS Write Command Set-Up Time (Test Mode In) 15 - 15 - ns tWTH Write Command Hold Time (Test Mode In) 10 - 10 - ns tWRP WE to RAS Precharge Time (CAS before RAS Cycle) 15 - 15 - ns tWRH WE to RAS Hold Time (CAS before RAS Cycle) tPD tPDOFF 10 - 10 - ns PDE to Presence Detect Data in Low-Z - 10 - 10 ns Presence Detect Data turn off Delay Time from PDE 1 - 1 - ns PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 10 7 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 Electrical Characteristics and Recommended AC Operating Conditions (VCC = 3.3V±5%, Ta = 0 ~ 70°C) (Notes 6,7,8) SYMBOL 8 THMxxxxxx-60 THMxxxxxx-70 MIN MAX MIN UNIT NOTES PARAMETER MAX ns tRC Random Read or Write Cycle Time 115 - 135 - ns tPC Fast Page Mode Cycle Time 45 - 50 - ns tRAC Access Time from RAS - 65 - 75 ns 9, 14, 15 tCAC Access Time from CAS - 25 - 30 ns 9, 14 tAA Access Time from Column Address - 40 - 45 ns 9, 15 tCPA Access Time from CAS Precharge - 45 - 50 ns 9 tRAS RAS Pulse Width 65 10,000 75 10,000 ns tRASP RAS Pulse Width (Fast Page Mode) 65 200,000 75 200,000 ns tRSH RAS Hold Time 25 - 30 - ns tCSH CAS Hold Time 65 - 75 - ns tRHCP CAS Precharge to RAS Hold 45 - 50 - ns tCAS CAS Pulse Width 20 10,000 25 10,000 ns tRAL Column Address to RAS Lead 40 - 45 - ns TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM THM72V2010AG/ATG-60/70 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. All voltages are referenced to VSS. ICC1, ICC3, ICC4, ICC6 depend on cycle rate. ICC1, ICC4 depend on output loading. Specified values are obtained with the output open. Address can be changed one or less while RAS=VIL. In case of ICC4, it can be changed once or less during a fast page mode cycle (tPC). An initial pause of 500µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. When the internal refresh counter is used, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh cycles are required. AC measurements assume tT=5ns. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. This parameter is measured with a load equivalent to 100pF and at VOH=2.0V (IOUT= -2mA), VOL=2.0V (IOUT=2mA). tOFF (max.) and tOEZ (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. Either tRCH or tRRH must be satisfied for a read cycle. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in Read-Modify-Write cycles. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥tWCS (min.), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) through the entire cycle; If tRWD≥tRWD (min.), tCWD≥tCWD (min.), tAWD≥tAWD (min.) and tCPWD≥tCPWD (min.) (Fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell: If neither of the above sets of conditions are satisfied, the condition of the data out (at access time) is indeterminate. Operation within the tRCD (max.) limit insures that tRAC can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA.27 PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 9 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 Timing Waveforms Read Cycle 10 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM THM72V2010AG/ATG-60/70 Write Cycle (Early Write) PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 11 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 Write Cycle (OE Controlled Write) 12 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM THM72V2010AG/ATG-60/70 Read-Modify-Write Cycle PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 13 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 Fast Page Mode Read Cycle 14 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM THM72V2010AG/ATG-60/70 Fast Page Mode Write Cycle (Early Write) PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 15 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 Fast Page Mode Read-Modify-Write Cycle 16 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM THM72V2010AG/ATG-60/70 RAS Only Refresh Cycle CAS Before RAS Refresh Cycle PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 17 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 Hidden Refresh Cycle (Read) 18 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM THM72V2010AG/ATG-60/70 Hidden Refresh Cycle (Write) PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 19 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 CAS Before RAS Refresh Counter Test Cycle 20 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM THM72V2010AG/ATG-60/70 WE, CAS Before RAS Refresh Cycle PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 21 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 Presence Detect Data Read Cycle 22 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM THM72V2010AG/ATG-60/70 Read Cycle in the Test Mode PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 23 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 Write Cycle (Early Write) in the Test Mode 24 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM THM72V2010AG/ATG-60/70 Fast Page Mode Read Cycle in the Test Mode PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 25 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 Fast Page Mode Write Cycle in the Test Mode 26 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM THM72V2010AG/ATG-60/70 Test Mode The TC51V17800ANJ/ANT is the RAM organized as 2,097,152 words by 8 bits, it is internally organized as 1,048,576 words by 16 bits. In “Test Mode”, data are written into 16 sectors in parallel by using only I/O1. A9C is not used. If, upon reading, 16 bits are equal (all “1”’s or “0”’s), the I/O8 pin indicates a “1”. If they were not equal, the I/O8 pin would indicate a “0”. Other I/O pins (I/O1 ~ 7) always indicate a “1” a during test mode read cycle. Figure 1 shows the block diagram of TC51V17800ANJ/ANT. In “Test Mode”, the 2Mx8 DRAM can be tested as if it were a 1Mx16 DRAM. “WE, CAS Before RAS Refresh Cycle” puts the device into “Test Mode”, and “CAS Before RAS Refresh Cycle” or “RAS Only Refresh Cycle” puts it back into “Normal Mode”. In the Test Mode, “WE, CAS Before RAS Refresh Cycle” performs the refresh operation with the internal refresh address counter. The “Test Mode” function reduces test times (1/2 in case of N test pattern). PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 27 THM72V2010AG/ATG-60/70 Standard DRAM DM16050295 Block Diagram in the Test Mode 28 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DM16050295 Standard DRAM Outline Drawing THM72V2010AG PRELIMINARY THM72V2010AG/ATG-60/70 Unit in mm TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 29 THM72V2010AG/ATG-60/70 Standard DRAM Outline Drawing THM72V2010ATG 30 DM16050295 Unit in mm TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY