THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 D D D D D DC Fan Drive Speed Control With No External Power Drive Stage Required 11% to 100% PWM Range Adjustable Via 0–2.5 V DC Control Voltage – Suited for Cooling Fan Applications Requiring Variable RPM to Reduce Noise and/or Increase MTBF Speed Control Capability With Either DC or PWM Input Signal for Greater System-Level Flexibility Sleep-State Mode to Eliminate External Fan ON/OFF Power Device – Suited for Cooling Fans in Instantly Available PCs Thermal Shutdown Protection D D D D D High Impedance VPWM Input for Speed Control of Multiple Fans With a Single Signal Locked Rotor Protection (THMC40, THMC41) With Open-Drain Output Indication (THMC41) Open-Drain Tachometer Signal Valid Over Entire RPM Range (THMC40) Noise Immune Signal Conditioning to Allow Use of Low-Cost Hall Effect Position Sensor Patented High Efficiency Drive Topology With Integrated Low RDS(ON) LDMOS Output Drivers THMC40 . . . TACH OUTPUT 14-Pin SOP D Package (TOP VIEW) COSC TACH CP VPWR VOUT NC PGND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VPWM H+ H– PHA PHB AGND NC THMC41 . . . RD OUTPUT 14-Pin SOP D Package (TOP VIEW) COSC RD CP VPWR VOUT NC PGND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VPWM H+ H– PHA PHB AGND NC description The THMC40 and THMC41 are 2-phase, dc brushless motor (BLM) drive and control devices intended for use with 12-Vdc cooling fans. Both devices include a high-efficiency PWM drive topology using integrated 0.5-Ω (typical) LDMOS drivers, plus a speed control input stage to provide the industry’s first solution for efficient speed control inside dc cooling fans. This patented solution eliminates the need for power drive components on the main system board, thus reducing printed-circuit board (PCB) component count, PCB space, and assembly time. This solution also offers other advantages over the two commonly used fan speed control methods, adjustable external dc supply voltage, and adjustable external PWM drive duty cycle. Unlike other methods which control speed external to the cooling fan, the THMC40 and THMC41 high-efficiency PWM drive stage adjusts only the level of motor phase winding power. All other circuitry inside the fan obtains power from the fixed dc voltage fan supply. This method eliminates the typical problem associated with an external dc voltage regulation method causing loss of headroom to internal control circuitry at low fan supply voltage and the resulting limitation of low-speed operation to ≈40%. The PWM drive method employed by the THMC40 and THMC41 also reduces fan supply power consumption over the external linear regulation method, which has V×I power loss due to the voltage drop across the regulator. An external PWM drive method disrupts power to the motor and also to all internal fan circuitry. The THM40 and THMC41 solution maintains all signal integrity with phase drive commutation and tachometer, while providing reliable low speed fan operation down to 11% PWM. This method allows fan health monitoring over the full fan speed range. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 description (continued) The VOUT duty cycle, and thus the motor speed, is proportional to the voltage present at the VPWM input terminal. This terminal allows controlling the fan speed via a DAC output from an external control IC or an RC-filtered PWM output from a PC Super I/O chip. The THMC40 and THMC41 have an internal Hall sensor amplifier and signal conditioner, global thermal shutdown, locked rotor protection, and automatic restart after a locked rotor condition. The THMC40 provides an open-drain tachometer output signal, while the THMC41 provides an open-drain locked rotor detection output signal. These devices also provide a sleep-state mode to eliminate the need for an external power component to disconnect the fan from the supply during a system sleep state or instantly available power down. The THMC40 and THMC41 are primarily intended for cooling fan applications that require RPM speed control and the availability of a tachometer or locked rotor detection signal. functional block diagram CP PWM Oscillator 23 kHz Nominal COSC PUC and VREF OSC SLEEP PWM Generator VPWM VSTART VSLEEP VPWR START and SLEEP Detection PWM High-Side Gate Drive With Synchronous Rectification Charge Pump VOUT Thermal Shutdown SLEEP PHA TACH (THMC40) Tachometer Output RD (THMC41) Low-Side Gate Drive Control Logic and Global Thermal Shutdown PHB OSC Hall Sensor Comparator Locked Rotor Detection and Auto Restart H+ H– AGND 2 POST OFFICE BOX 655303 PGND • DALLAS, TEXAS 75265 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 Terminal Functions TERMINAL NAME NO. AGND 9 CP COSC H– I/O DESCRIPTION I IC analog ground and substrate connection 3 I External charge pump capacitor 1 I/O 12 I Hall sensor negative input External oscillator capacitor H+ 13 I Hall sensor positive input NC 6, 8 – No connection PGND 7 I Power ground for high-side charge pump PHA 11 O Low-side driver for phase A motor winding PHB 10 O Low-side driver for phase B motor winding RD 2 O Open-drain locked rotor detection output—THMC41 only TACH 2 O Open-drain tachometer output signal—THMC40 only VOUT VPWR 5 O High-side PWM driver output for motor windings 4 I Supply voltage input VPWM 14 I PWM duty cycle control voltage input absolute maximum ratings over operating case temperature range (unless otherwise noted)† (see Note 1) Supply voltage input, VPWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V High-side driver, PWM output voltage, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Low-side drivers, phase A and B output, VPHA, VPHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V Hall sensor amplifier input voltage, VH+, VH– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V PWM duty cycle control input voltage, VPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Open-drain tachometer output voltage (THMC40), VTACH, or open-drain RD output voltage (THMC41), VRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Oscillator capacitor voltage, VCOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Charge pump capacitor voltage, VCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V Continuous high-side PWM output source/sink current, IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A Continuous low-side PWM output sink current, IPHA, IPHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A Junction-to-case thermal resistance, RθJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.9°C/W Junction-to-ambient thermal resistance , RθJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.3°C/W Continuous power dissipation at 25°C , PD (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 mW Power derating factor above 25°C ambient , PDERATING (see Note 4) . . . . . . . . . . . . . . . . . . . . . 8.18 mW/°C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30°C to 80°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (soldering, 10 sec), TLEAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. JEDEC low-K board with 0 LFM airflow 3. 150°C maximum junction temperature, JEDEC low-K board with 0 LFM airflow 4. 80°C maximum ambient and 150°C maximum junction temperature POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 dc electrical characteristics, VPWR = 12 V, TA = – 30°C to 80°C (unless otherwise noted) supply current PARAMETER VPWR TEST CONDITIONS MIN TYP MAX 11 12 13 V Idle condition in locked rotor detect 2.5 5 mA ILOAD = –1 A, VOUT low, TA = 25°C VPWM ≤ 0.4 V 300 400 µA UNITS Supply voltage range IVPWR VPWR supply current ISLEEP Sleep-state current 5 UNITS mA PHA, PHB low-side phase winding driver outputs PARAMETER TYP MAX 0.1 10 PHA, PHB low-level output voltage Output = OFF, VPHx = 12 V Output = ON, IPHx = 1 A, TA = 25°C TEST CONDITIONS 0.5 0.6 V PHA, PHB output ON resistance Output = ON, 0.5 0.6 Ω ILEAK VOL PHA,PHB output leakage current RDS(ON) VCLAMP PHA, PHB output active clamp voltage TA = 25°C Output = OFF, IPHx = 200 mA MIN IPHx = 1A, 32 38 MIN TYP µA V Hall sensor signal conditioning PARAMETER TEST CONDITIONS ±0.1 IIB(HL) VICR(HL) Hall input bias current VIO Hall comparator input offset voltage ICR(HL) common-mode input voltage range 1 Over VICR(HL) = 1 V to 3.5 V –7 0 MAX UNITS ±1 µA 3.5 V 7 mV VOUT high-side phase winding driver output PARAMETER TEST CONDITIONS ILEAK VOUT output sleep-state leakage current Sleep state engaged, VVOUT = 0 V to VPWR VOH VOUT high-level output voltage Run state, Output high IVOUT = –1 A,, TA = 25°C RDS(ON) VOUT output high-side resistance to VPWR VOUT output recirculation voltage VRECIR RDS(ON)(SYNC) ILIMIT MIN Run state,, Output low IVOUT = –1 A, TA = 25°C VOUT synchronous switch resistance to PGND Run state, VOUT=VPWR=12V, VCOSC > VPWM, tPULSE = 100 µs, See Note 5 Pulsed VOUT synchronous rectification current limit TYP MAX UNITS ±0.1 ±10 µA VPWR – 0.4 VPWR – 0.6 V 0.4 0.6 Ω – 0.3 – 0.5 V 0.3 0.5 Ω 2 2.6 MIN TYP A CP high-side gate drive charge pump capacitor input PARAMETER VCP VCP(UVLO) TEST CONDITIONS IVCP = –60 µA, VPWM = 2.5 V Charge pump voltage VCP undervoltage lock-out MAX 22 26 6.5 7.6 8.5 UNITS V V COSC external oscillator capacitor PARAMETER ICHARGE IDISCHARGE COSC charge source current VDISCHARGE COSC upper threshold for switching to current sink VCHARGE COSC lower threshold for switching to current source COSC discharge sink current TEST CONDITIONS MIN TYP MAX UNITS VCOSC = 1.4 V, Charge mode VCOSC = 1.4 V, Discharge mode –130 –180 –230 µA 130 180 230 µA 2 2.3 2.6 V 0.43 0.5 0.57 V NOTE 5: VOUT current limit, in conjunction with thermal shutdown function, provides device survivability under VOUT-to-VPWR short condition. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 dc electrical characteristics, VPWR = 12 V, TA = –30°C to 80°C (unless otherwise noted) (continued) VPWM high-side PWM duty cycle adjust input PARAMETER TEST CONDITIONS IIB(PWM) VPWM (100%) VPWM input bias current VPWM voltage equivalent to 100% duty cycle VSLEEP VPWM voltage threshold to engage sleep mode VPWM voltage threshold to disengage sleep mode VSTART MIN TYP MAX ±1 VPWM = 0 V to 3 V 0.6 UNITS µA 2.3 V 0.7 V 0.8 0.9 V TYP MAX UNITS 185 °C thermal shutdown characteristics PARAMETER TEST CONDITIONS TTSD VOUT, PHA, PHB global thermal shutdown thresholds Temperature increasing until outputs are off, See Note 6 THYST Thermal shutdown hysteresis After TTSD, temperature decreasing until outputs return to normal operation, See Note 6 MIN 150 °C 15 TACH Tachometer open-drain output (THMC40) PARAMETER ITACHLEAK VOL TEST CONDITIONS TACH high-level output leakage current TACH low-level output voltage MIN VTACH = 5 V ITACH = 5 mA TYP MAX 0.1 1 UNITS µA 0.1 0.3 V TYP MAX 0.1 1 µA 0.1 0.3 V RD locked rotor detection open-drain output (THMC41) PARAMETER IRDLEAK VOL TEST CONDITIONS RD high-level output leakage current RD low-level output voltage MIN VRD = 5 V, Locked rotor condition IRD = 5 mA, No locked rotor UNITS ac electrical characteristics, VPWR = 12 V, TA = –30°C to 80°C (unless otherwise noted) PARAMETER TEST CONDITIONS fPWM tRD High-side gate drive PWM frequency tRETRY tHALL Auto-restart delay time tDEAD(PHx) tf(OUT) Dead time between phase commutations tr(OUT) tf(PHx) Locked rotor detect delay time COSC = 2200 pF COSC = 2200 pF, pF See Figure 9 Hall zero-crossing deglitch time VOUT output fall time VOUT output rise time See Figure 2 RL = 20 Ω , LL = 5 mH,, See Note 6 PHA or PHB fall time tr(PHx) PHA or PHB rise time NOTE 6: Design targets only. Not tested in production. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP 22.7 1 MAX UNITS kHz s 8 s 25 µs 5 µs 25 ns 25 ns 1 µs 1 µs 5 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 PRINCIPLES OF OPERATION general overview The THMC40 and THMC41 are 2-phase dc brushless fan motor drivers with PWM speed control intended primarily for applications requiring a wide speed control range and an open-drain tachometer output signal (THMC40), or a locked rotor detection output (THMC41). The VOUT drive duty cycle, and thus fan speed, is proportional to the voltage level at the VPWM input terminal. Each device has an internal Hall sensor comparator/signal conditioner, a low power sleep-state mode, locked rotor protection with automatic restart after a locked rotor condition, and over-temperature protection. The tachometer signal (THMC40) can be used to monitor the health of the fan or to close an external loop based on fan RPM. The THMC40 and THMC41 provide a more efficient drive solution to fan RPM control than external linear voltage control. This solution is also considerably more efficient than controlling dc brushless fan RPM using external PWM drive. low-side motor phase winding driver outputs (PHA, PHB) The PHA and PHB outputs provide low-side drive of the motor’s two stator phase windings (see block diagram and Figure 1). These outputs have a typical RDS(ON) of 400 mΩ at 25°C and a 1-A continuous current rating. The PHA and PHB outputs have an active flyback clamp (VZCLAMP in Figure 1) of 38 V (typical) to snub inductive energy when a phase drive switches off. The outputs also have global thermal shutdown to prevent device failure. Drive commutation of PHA and PHB outputs is controlled according to rotor position monitored by a Hall-effect position sensor. Discussion of this function is found in the following section, and the relationship between PHA and PHB outputs to Hall input signal is shown in Figure 2. VOUT TACH (THMC40) Tachometer Output Driver RD (THMC41) Locked Rotor Detection and Auto-Restart VPWR Naked Hall Sensor H+ H– Hall Sensor Comparator PHA Low-Side Gate Drive Control Logic, and Global Thermal Shutdown VZCLAMP PHB VZCLAMP Figure 1. Low-Side Gate Drive Block Diagram 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 S N N S THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 Hall sensor comparator and signal conditioning inputs (H+, H–) Referring to Figure 1, the THMC40 and THMC41 have an internal Hall sensor comparator allowing the use of low-cost naked Hall sense elements. The Hall signal conditioning block receives a low-level differential voltage from the naked Hall position sensor element. The comparator then implements a zero differential voltage crossing detection with a deglitch time of 25 µs (typical) to reject noise on the Hall signal inputs. Referring to Figure 2, the PHx drive that was on (low) turns off after the 25-µs deglitch time is reached. Then the opposite PHx drive turns on after another delay time. This 5-µs (typical) dead time is implemented to prevent both phases from conducting simultaneously and to allow time for the inductive energy to be snubbed from the phase that was just turned off. The Hall comparator circuit has an input offset voltage (VIO) which is not greater than ±7 mV. The common-mode input voltage range is 1 V to 3.5 V (see Figure 2). Hall Sensor Waveform (VH+ - VH–) VCM VIO OFF PHA Output Voltage ON tDEAD(PHx) tHALL OFF PHB Output Voltage ON 5 µs tHALL 25 µs 25 µs tDEAD(PHx) 5 µs OFF TACH Output Voltage (THMC40) ON Time Figure 2. Hall Sensor Signal Conditioning Waveforms Table 1 shows PHA and PHB commutation, and TACH output (THMC40) functionality: Table 1. PHA and PHB Low-Side Drive Commutation and TACH Functionality H+ H– PHA PHB TACH (THMC40) + – High (OFF) Low (ON) High (OFF) – + Low (ON) High (OFF) Low (ON) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 high-side PWM output driver (VOUT) Referring to Figure 3, VOUT is a drive output to provide PWM controlled power to the common node of the motor phase windings using an internally generated PWM signal. The PWM duty cycle controls the effective drive power to the motor, and thus motor speed. The high-side VOUT DMOS output transistor has a typical RDS(ON) of 400 mΩ at 25°C and a 1-A continuous current. CP 0.1 µF COSC 2200 pF Triangle Wave Generator PUC High-Side Driver 0.5 V to 2.3 V COMP PWM VPWM Charge Pump, HS Gate Drive, Synchronous Rectification, and Global Thermal Shutdown Synchronous Low-Side Switch VPWR VOUT Figure 3. High-Side PWM Drive The frequency of the PWM drive (typically 23 kHz) is such that the L/R time constant of the motor phase winding filters the current. Referring to Figure 4, during the on-time (tON) of a PWM period, VOUT is driven high forcing voltage across a phase winding and increasing the current. During tOFF, PWM off-time, the VOUT high-side DMOS is switched off, the phase winding inductive energy is recirculated, and the current decreases. To minimize the voltage drop and the resulting energy loss during recirculation, a low-side DMOS synchronous switch is provided, as shown in Figure 3. This low-side DMOS device has a 2-A minimum current limit to prevent device failures should a solder bridge occur between the adjacent VPWR and VOUT terminals. IMOTOR IDRIVE IRECIRCULATE tPWM PWM tON tOFF Time Figure 4. Motor Current Waveform The VOUT circuit is protected by the global thermal shutdown of the THMC40 and THMC41 by turning off both the high-side and low-side DMOS drivers when an over-temperature condition is detected. VOUT is also held off when the charge-pump voltage (VCP) is lower than its undervoltage lock-out threshold, VCP(UVLO). 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 charge pump (CP) THMC40 and THMC41 have an internal charge pump which utilizes an external reservoir capacitor (CP) to generate the gate-drive voltage for the VOUT output high-side DMOS transistor (see Figure 3). The recommended value for CP is 0.1 µF, with a minimum rating of 35 WVdc. The charge pump is disabled during the sleep state (see the sleep/run state section) to minimize current consumption into VPWR. The charge pump also incorporates internal undervoltage lockout detection used to disable VOUT when the charge pump voltage does not have an adequate level above VPWR to fully drive the high-side DMOS gate. Thus, the VCP (UVLO), in conjunction with the charge pump start-up time, delays the VOUT drive for a short time after the device has transitioned from sleep to run state, until the charge pump voltage reaches the UVLO threshold. PWM oscillator/triangle waveform generator (COSC) The PWM oscillator uses source and sink currents switched into an external capacitor (COSC) to set the PWM frequency and generate a triangle waveform. A PWM oscillator cycle consists of charging COSC with a constant current source (–180 µA typical) until the COSC voltage ramps up to an upper threshold (2.3 V typical), and then discharging COSC with a constant current sink (180 µA typical) until the COSC voltage ramps down to a lower threshold (0.5 V typical). The charge/discharge cycle is repeated each time the 2.3-V or 0.5-V threshold is reached (see Figure 5). VPWR VREF V 2.3 V 2.3 V –180 µA S VCOSC Q 0.5 V COSC 2200 pF R 0.5 V Q Q 180 µA Q 0 Time PWM VPWM Figure 5. PWM Triangle Waveform Generator The following equation can be used to calculate the value of COSC needed for a desired PWM frequency, fPWM: C OSC(max) + ǒ I CHARGE(min) 2 f PWM(min) V DISCHARGE POST OFFICE BOX 655303 * VCHARGE • DALLAS, TEXAS 75265 Ǔ 9 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 PWM duty cycle control voltage (VPWM) – dc control voltage input The voltage at the VPWM terminal determines the PWM duty cycle of the output (VOUT) to control drive power to the fan motor, and thus control fan speed (see Figures 3 and 6). The VPWM voltage is internally compared against the 0.5-V to 2.3-V triangle waveform generated on the COSC terminal. The PWM signal output from this comparator has a duty cycle proportional to the voltage at VPWM, as shown in Figure 6. The output of this comparator is used as the PWM input to the VOUT drive stage. 100 90 VOUT Duty Cycle = (VPWM - 0.5)/1.8 × 100 VOUT – Duty Cycle – % 80 70 SLEEP STATE 60 RUN STATE 50 40 VSLEEP=0.7 V 30 VSTART = 0.8 V Must be exceeded to enter run state 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VPWM – Input Voltage – V 1.8 2 2.2 2.4 Figure 6. Relationship of VOUT Duty Cycle, VSTART, and VSLEEP vs VPWM Input Voltage PWM duty cycle control voltage (VPWM) – digital PWM control input To allow control of the THMC40 and THMC41 by either a PWM or a dc input control signal, it is recommended that the fan manufacturer includes a 100-kΩ, 0.1-µF RC filter between the speed control wire and the VPWM terminal (see Figure 7). This method allows the end user to control the fan speed with either a PWM signal or a dc control voltage. Many PC Super I/O ICs and hardware monitoring ICs provide one of the two fan speed control outputs. Therefore, fans with THMC40 and THMC41 ICs can be used with a wide variety of control schemes to provide variable fan speed without an external fan drive power stage. PC Motherboard VFAN Inside Cooling Fan Full Speed Option PWM Generator (Super I/O or HW Monitor) 1 – 10 MΩ† Speed Control R = 100 kΩ 1 – 10 MΩ† VPWM THMC40 and THMC41 C = 0.1 µF Sleep State Option † Optional resistors control fan operation with open speed control input. Figure 7. PWM Input Control With RC Filter Inside the Cooling Fan 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 PWM duty cycle control voltage (VPWM) – digital PWM control input (continued) Figure 8 illustrates the relationship between VOUT output duty-cycle and a 0–3.3-V digital PWM input control signal. 100 90 VOUT % =((3.3 V × (Input%÷100)-0.5)÷1.8) × 100 VOUT – Duty Cycle – % 80 70 SLEEP STATE 60 RUN STATE 50 40 VSLEEP=21% 30 20 VSTART = 24% Must be exceeded to enter run state 10 0 0 10 20 30 40 50 60 70 3.3-V Duty Cycle Input to RC Filter 80 90 100 Figure 8. Relationship of VOUT Duty Cycle, VSLEEP, VSTART vs 0–3.3 V PWM Input Duty Cycle sleep/run state Sleep-state and run-state modes are provided, as illustrated in Figures 6 and 8. The sleep state is intended to minimize VPWR (fan) supply current requirements (300 µA typical) when cooling fan operation is not required. This feature is especially beneficial for PC OEMs needing to meet the instantly available PC requirements without the use of additional external circuitry. The sleep state is engaged when the VPWM input voltage is below the VSLEEP threshold (0.7 V typical, 11.1% duty cycle). During the sleep state, all output drivers are turned off and any unused circuits are powered down to minimize current drain. Once sleep state is engaged, VPWM must exceed the VSTART threshold (0.8 V typical, 17% duty cycle) to disable the sleep state and enter the run state, allowing the motor to be driven. Once the run state is engaged, outputs VOUT, PHA, and PHB are active and the VPWM voltage can be decreased to obtain minimum fan speed down to the VSLEEP threshold. This procedure allows the user to overcome initial motor stiction with a PWM duty cycle of 17% to avoid the possibility of false locked rotor detection during initial start-up. See Figure 6 for the VPWM input voltage relationship to sleep mode and VOUT duty cycle. A control device with a voltage range of 0 V to 2.5 V is recommended to provide the adjustable VPWM reference voltage to the THMC40 and THMC41. A 2.5-V DAC is an optimal choice as the controlling circuitry, whether as a stand-alone device, or as an integrated function in a multiple-function device. Using a control device without a minimum 0.5-V to 2.3-V range reduces the RPM control range of the fan motor and may not allow duty-cycle settings of 0% and/or 100%. thermal shutdown The THMC40 and THMC41 provide protection against excessive device temperature with a thermal sensor that monitors the die temperature. Should some operating or abnormal condition cause the die temperature to exceed TTSD, the thermal shutdown threshold (165°C typical), all output drivers are turned off. Once TTSD has been exceeded, the die temperature must fall below a hysteresis temperature (typical TTSD –15°C) before the output drivers are re-enabled. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 locked rotor protection An internal digital timer monitors the output of the Hall sensor amplifier. When a change in commutation state is not observed within one second (typical with 2200 pF COSC), the VOUT, PHA, and PHB outputs are disabled for eight seconds (typical with 2200 pF COSC). After the outputs have been disabled for eight seconds (typical with 2200 pF COSC), the THMC40 and THMC41 re-enable the VOUT, PHA, and PHB outputs to automatically restart the motor after a locked rotor condition. If the locked rotor condition still exists, the above process repeats itself until the condition is removed, or the THMC40 and THMC41 are powered down (see Figure 9). NOTE: The locked rotor detection time and auto-retry time are proportional to the PWM frequency, and therefore to the value of COSC. With a COSC value of 2200 pF, the PWM frequency is typically 22.7 kHz, locked rotor detection time is typically one second, and auto-retry time is typically eight seconds. Hall Sensor Comparator Output 1s 8s 1s 8s VOUT, PHA and PHB Output Enable RD Output (THMC41) Tach Output (THMC40) Figure 9. Typical Locked Rotor Protection Timing Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 open-drain tachometer output (TACH)—THMC40 Only The THMC40 TACH output is an open-drain output activated by the Hall sensor comparator output (see Figure 9). When the Hall sensor comparator output is high, the TACH output floats high. When the Hall sensor amplifier output is low, the TACH output is pulled low. The resulting output signal has two pulses per revolution on a four-pole motor. The TACH output can be used to monitor and measure actual fan speed. This output can also be used as part of a closed-loop speed control system. NOTE: It is recommended that the fan manufacturer not place a pullup resistor for this terminal on the fan circuit board. Leaving the output as open-drain allows the end user to pull up this terminal with an external resistor to the supply voltage of their choice (that is, 3.3 V or 5 V). open-drain locked rotor detection output—THMC41 only The THMC41 RD output is an open-drain output pulled low during normal fan operation and allowed to float during a locked rotor condition (see Figure 9). This signal can be used to alert the system of a locked rotor condition. The RD output can also be used as a fan present or fan OK signal by using a general-purpose input terminal on a PC Super I/O chip to detect the logic state of this terminal. When this input is high, the signal indicates that the fan has been disconnected or is in a locked rotor condition. NOTE: It is recommended that the fan manufacturer not place a pullup resistor for this terminal on the fan circuit board. Leaving the output as open-drain allows the end user to pull up this terminal with an external resistor to the supply voltage of their choice (that is, 3.3V or 5V). supply voltage input (VPWR) The VPWR terminal serves as the voltage supply input to the THMC40 and THMC41. A 0.1-µF bypass capacitor should be placed as close to this terminal as the layout permits. Additional bulk capacitance of 2.2 µF to 10 µF on this terminal is highly recommended to reduce current spikes on the supply line during motor commutation, thus reducing radiated emissions from the fan. See Application Information for further details. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 APPLICATION INFORMATION Speed Control Input +12 V TACH 1 – 10 MΩ† Full Speed Option CR1 1N4002 1 – 10 MΩ† Sleep State Option R1 100 kΩ R2 3.01 kΩ C2 2200 pF 1 2 0.1 µF C3 C5 10 µF 16 V 4 5 + C4 0.1 µF ‡ GND 3 6 7 COSC VPWM TACH H+ CP H– VPWR THMC40D PHA PHB VOUT NC AGND 14 0.1 µF 13 MOTOR 10 9 L2 L1 † Optional resistors control fan operation with open speed control input. ‡ An analog ground trace should be connected close to the ground connection of C4 and C5. NOTE: Traces in bold handle highest current. Figure 10. THMC40 Application Schematic POST OFFICE BOX 655303 HALL SENSOR 3 11 LO 14 4 12 NC 8 PGND 1 C1 • DALLAS, TEXAS 75265 2 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 APPLICATION INFORMATION Speed Control Input +12 V RD 1 – 10 MΩ† 1 – 10 MΩ† Sleep State Option Full Speed Option CR1 1N4002 R1 100 kΩ R2 3.01 kΩ C2 2200 pF 1 2 0.1 µF C3 C5 10 µF 16 V 3 4 5 + C4 0.1 µF 6 ‡ 7 GND VPWM COSC RD H+ CP H– VPWR THMC41D PHA PHB VOUT NC AGND 14 0.1 µF 1 C1 13 4 HALL SENSOR 2 12 3 11 10 9 NC 8 PGND MOTOR L2 LO L1 † Optional resistors control fan operation with open speed control input. ‡ An analog ground trace should be connected close to the ground connection of C4 and C5. NOTE: Traces in bold handle highest current. Figure 11. THMC41 Application Schematic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 THMC40, THMC41 VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS SLIS097 – MARCH 2000 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. 16 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). 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