THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 features applications D D D D D D D D D D D D D D D D D D 14-Bit Resolution 1 MSPS and 3 MSPS Speed Grades Available On-Chip FIFO For Optimized Data Transfer Differential Nonlinearity (DNL) ±0.6 LSB Typ Integral Nonlinearity (INL) ±1.5 LSB Typ Internal Reference Differential Inputs Programmable Gain Amplifier µP Compatible Parallel Interface Timing Compatible With TI 6000 DSP Family 3.3-V Single Supply Power-Down Mode Monolithic CMOS Design xDSL Front Ends Communication Industrial Control Instrumentation Automotive IN+ AVDD AGND AGND AGND AVDD DVDD A0 A1 FOVL INT CS PFB PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 IN– AVDD VBG CML REF+ REF– AGND AGND DGND OV D13 D12 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 WR OE DGND DGND CLK DVDD DVDD D0 D1 D2 DVDD DGND D6 D5 D4 D3 D11 DVDD DGND D10 D9 D8 D7 DVDD 13 14 15 16 17 18 19 20 21 22 23 24 NC – No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 description The THS14F01 and THS14F03 are 14-bit, 1 MSPS/ 3 MSPS, single supply analog-to-digital converters with a FIFO, internal reference, differential inputs, programmable input gain, and an on-chip sample and hold amplifier. Implemented with a CMOS process, the device has outstanding price/performance and power/speed ratios. The THS14F01 and THS14F03 are designed for use with 3.3-V systems, and with a high-speed µP compatible parallel interface, making them the first choice for solutions based on high-performance DSPs like the TI TMS320C6000 series. The THS14F01 and THS14F03 are available in a TQFP-48 package in standard commercial and industrial temperature ranges. functional block diagram VBG REF+ REF REF– 1.5 V BG IN+ PGA 0..7 dB 14-Bit ADC 32-Word FIFO+ Buffer 14 IN– 15 D[13:0] + OV bit 6 A[1:0] CLK CS WR OE INT FOVL CONTROL LOGIC AVAILABLE OPTIONS PACKAGED DEVICE TA 2 TQFP (PFB) 0°C to 70°C THS14F01CPFB, THS14F03CPFB –40°C to 85°C THS14F01IPFB, THS14F03IPFB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION A[1:0] 40, 41 I Address input AGND 7,8, 44, 45, 46 P Analog ground AVDD CLK 2, 43, 47 P Analog power supply 32 I Clock input CML 4 CS Reference midpoint. This pin requires a 0.1-µF capacitor to AGND. 37 I Chip select input. Active low DGND 9, 15, 25, 33, 34 P Digital ground DVDD 14, 20, 26, 30, 31, 42 P Digital power supply D[13:0] 11, 12, 13, 16, 17, 18, 19, 21, 22, 23, 24, 27, 28, 29 I/O Data inputs/outputs FOVL 39 O FIFO Overflow. Asserted when FIFO is full. Programmable polarity IN+ 48 I Positive differential analog input IN– 1 I Negative differential analog input INT 38 O Interrupt output. Asserted when FIFO trigger level is reached. Programmable polarity OE 35 I Output enable. Active low OV 10 O Out of range output REF+ 5 O Positive reference output. This pin requires a 0.1-µF capacitor to AGND. REF– 6 O Negative reference output. This pin requires a 0.1-µF capacitor to AGND. VBG 3 I Reference input. This pin requires a 1-µF capacitor to AGND. WR 36 I Write signal. Active low absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, (AVDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V Supply voltage, (DVDD to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V Reference input voltage range, VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVDD + 0.3 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DVDD + 0.3 V Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 recommended operating conditions MIN NOM MAX Supply voltage, AVDD, DVDD 3 3.3 3.6 High level digital input, VIH 2 3.3 Low level digital input, VIL Load capacitance, CL UNIT V V 0 0.8 V 5 15 pF THS14F01 0.1 1 1 MHz THS14F03 0.1 3 3 MHz 40% 50% 60% 0 25 70 –40 25 85 MIN TYP MAX Analog supply current 81 90 mA Digital supply current 5 10 mA 270 360 mW Clock frequency frequency, fCLK Clock duty cycle C suffix air temperature Operating free free-air I suffix °C electrical characteristics over recommended operating conditions PARAMETER TEST CONDITIONS UNIT Power Supply IDDA IDDD Power Power down current DC Characteristics† Resolution DNL Differential nonlinearity INL Integral nonlinearity 14 THS14F01 THS14F03 Offset error Best fit THD Total harmonic distortion SNR Signal to noise ratio Signal-to-noise SINAD Signal to noise ratio + distortion Signal-to-noise SFDR Spurious free dynamic range ±1 ±1.5 ±2.5 ±1.5 ±2.5 PGA = 0 dB Effective number of bits 11.2 THS14F01/3 THS14F03 THS14F01/3 THS14F03 THS14F01/3 THS14F03 THS14F01/3 THS14F03 fi = 100 kHz fi = 1 MHz –78 70 fi = 100 kHz fi = 1 MHz 69 fi = 100 kHz fi = 1 MHz 11.5 –81 fi = 100 kHz fi = 1 MHz 72 72 70 70 80 73 Bits ±0.6 IN+ = IN–, PGA = 0 dB Gain error AC Characteristics† ENOB µA 20 80 LSB LSB 0.3 %FSR 1 %FSR Bits dB dB dB dB Analog input bandwidth 140 MHz † FIFO trigger level = 10 samples. Performance is ensured with the output enable signal (OE) being low during no more than one rising clock edge on CLK. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 electrical characteristics (continued) PARAMETER TEST CONDITIONS MIN TYP MAX 1.425 1.5 1.575 UNIT Reference Voltage VBG Bandgap voltage, internal mode V Input impedance 40 kΩ Positive reference voltage, REF+ 2.5 V Negative reference voltage, REF– 0.5 V 2 V Reference difference, ∆REF, REF+ – REF– Accuracy, internal reference 5% Temperature coefficient Voltage coefficient 40 ppm/°C 200 ppm/V Analog Inputs Positive analog input, IN+ 0 Negative analog input, IN– Analog input voltage difference ∆Ain = IN+ – IN–, Vref = REF+ – REF– 0 AVDD AVDD –Vref Vref Input impedance 25 PGA range 0 PGA step size V V kΩ 7 1 dB dB ±0.25 PGA gain error V dB Digital Inputs VIH VIL High-level digital input 2 V Low-level digital input 0.8 Input capacitance 5 ±1 Input current V pF µA Digital Outputs VOH VOL High-level digital output Low-level digital output IOH = 50 µA IOL = 50 µA 2.6 V IOZ Output current, high impedance Clock Timing (CS low) fCLK Clock frequency td Output delay time 0.4 V ±10 µA THS14F01 0.1 1 1 MHz THS14F03 0.1 3 3 MHz 25 Latency 9.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns Cycles 5 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 PARAMETER MEASUREMENT INFORMATION sample timing The THS14F01/3 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results are stored in the FIFO 9.5 clock cycles after the input signal was sampled. S11 S9 S12 S10 Analog Input tw(CLK) tw(CLK) CLK td INT Data C1 C2 C3 to FIFO Figure 1. Sample Timing INT goes active if the programmed FIFO level is reached. INT is either low or high active depending on the polarity bit (IP) within the control word. This signal is set synchronously to the CLK signal. It is reset by a read access to the FIFO once the number of samples in the FIFO is below the programmed threshold level. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 PARAMETER MEASUREMENT INFORMATION The parallel interface of the THS14F01/3 ADC features 3-state buffers making it possible to directly connect it to a data bus. The output buffers are enabled by driving the OE input low. Besides the sample results, it is also possible to read back the values of the control register, the PGA register, and the control register. Which register is read is determined by the address inputs A[1,0]. The ADC results are available at address 0. The timing of the control signals is described in the following sections. The FIFO can be disabled by setting FC to 0 (FIFO reset, default at power on). This makes it possible to access the device synchronously. In this case the data is updated on every clock cycle. S11 S9 S12 S10 Analog Input tw(CLK) tw(CLK) CLK td D[13:0] C0 C1 C2 C3 OV ten tdis OE th(A) A[1:0] X X tsu(OE-ACS) th(CS) CS Figure 2. Sample Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 PARAMETER MEASUREMENT INFORMATION read timing (15-pF load) PARAMETER MIN TYP MAX 4 UNIT tsu(OE–ACS) ten Address and chip select setup time Output enable 15 ns tdis th(A) Output disable 10 ns 15 ns Address hold time ns 1 th(CS) Chip select hold time NOTE: All timing parameters refer to a 50% level. 0 ns CS th(CS) OE tsu(OE–ACS) ten tdis DATA D[13:0] OV th(A) A[1:0] X ADDRESS Figure 3. Read Timing 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 X THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 PARAMETER MEASUREMENT INFORMATION write timing (15-pF load) PARAMETER MIN TYP MAX UNIT tsu(WE–CS) tsu(DA) Chip select setup time 4 ns Data and address setup time 29 ns th(DA) th(CS) Data and address hold time 0 ns 0 ns 15 ns Chip select hold time twH(WE) Write pulse duration high NOTE: All timing parameters refer to a 50% level. CS th(CS) WE tsu(WE–CS) D[13:0] tsu(DA) X DATA X th(DA) A X ADDRESS X Figure 4. Write Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 TYPICAL CHARACTERISTICS POWER vs FREQUENCY SUPPLY CURRENT vs TIME 284 90 282 80 I CC – Supply Current – mA Power – mW 280 278 276 274 272 270 70 60 50 40 30 20 10 0 268 0.1 1 f – Frequency – MHz 0 10 50 Figure 5 100 150 200 t – Time – ns 250 Figure 6 FAST FOURIER TRANSFORM 0 fs = 1 MSPS, fI = 100 kHz, –1 dB Output – dB –20 –40 –60 –80 –100 –120 –140 0 100 200 300 f – Frequency – kHz Figure 7 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 400 500 300 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM 0 Output – dB –20 –40 fs = 3 MSPS, fI = 1 MHz, –1 dB –60 –80 –100 –120 –140 0.1 0.4 0.7 1 1.3 f – Frequency – MHz Figure 8 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY 2 fs = 1 MSPS 1.5 1 0.5 0 –0.5 –1 –1.5 –2 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 9 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY 2 fs = 3 MSPS 1.5 1 0.5 0 –0.5 –1 –1.5 –2 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 DNL – Differential Nonlinearity – LSB TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY 1 0.8 fs = 1 MSPS 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples DNL – Differential Nonlinearity – LSB Figure 11 DIFFERENTIAL NONLINEARITY 1 0.8 fs = 3 MSPS 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 2048 4096 6144 8192 10240 Samples Figure 12 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12288 14336 16384 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs FREQUENCY SIGNAL-TO-NOISE RATIO vs FREQUENCY –72 80 fs = 3 MSPS, fI at –1 dB 78 SNR – Signal-to-Noise Ratio – dB THD – Total Harmonic Distortion – dB –70 –74 –76 –78 –80 –82 –84 –86 76 74 72 70 68 66 64 62 –88 –90 10 fs = 3 MSPS, fI at –1 dB 100 f – Frequency – Hz 1000 1500 60 10 100 1000 1500 f – Frequency – Hz Figure 13 Figure 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 PRINCIPLES OF OPERATION registers The device contains several registers. The A register is selected by the values of bits A1 and A0: A1 A0 Register 0 0 Conversion result 0 1 PGA 1 0 Offset 1 1 Control Tables 1 and 2 describe how to read the conversion results and how to configure the data converter. The default values (were applicable) show the state after a power-on reset. Table 1. Conversion Result Register, Address 0, Read BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function MSB ... … … … … … … … … … … … LSB The output can be configured for two’s complement or straight binary format (see D11/control register). The output code is given by: 2s complement: –8192 at ∆IN = –∆REF 0 at ∆IN = 0 8191 ∆IN = –∆REF – 1 LSB 1 LSB Straight binary: 0 at ∆IN = –∆REF 8192 at ∆IN = 0 16383 at ∆IN = –∆REF – 1 LSB DREF + 216384 Table 2. PGA Gain Register, Address 1, Read/Write BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X X X X X X X G2 G1 G0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The PGA gain is determined by writing to G2–0. Gain (dB) = 1dB × G2–0. max = 7dB. The range of G2–0 is 0 to 7. Table 3. Offset Register, Address 2, Read/Write BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X X MSB … … … … … … LSB Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The offset correction range is from –128 to 127 LSB. This value is added to the conversion results from the ADC. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 PRINCIPLES OF OPERATION Table 4. Control Register, Address 3, Read BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function PWD REF FOR TM2 TM1 TM0 OFF IP FP FC F3 F2 F1 F0 Table 5. Control Register, Address 3, Write BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function PWD REF FOR TM2 TM1 TM0 OFF IP FP FC F3 F2 F1 F0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWD: Power down 0 = normal operation 1 = power down REF: Reference select 0 = internal reference 1 = external reference FOR: Output format 0 = straight binary 1 = 2s complement TM2–0: Test mode 000 = normal operation 001 = both inputs = REF– 010 = IN+ at Vref/2, IN– at REF– 011 = IN+ at REF+, IN– at REF– 100 = normal operation 101 = both inputs = REF+ 110 = IN+ at REF–, IN– at Vref/2 111 = IN+ at REF–, IN– at REF+ OFF: Offset correction 0 = enable 1 = disable IP: INT polarity 0 = low active 1 = high active FP: FIFO FOVL polarity 0 = low active 1 = high active FC: FIFO control 0 = disable FIFO 1 = enable FIFO F3–0: FIFO threshold Sets the FIFO threshold for the INT signal in steps of 2 ranging from 0 to 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 APPLICATION INFORMATION FIFO description The FIFO is based on a circular buffer (see Figure 15, in this example the FIFO is 16 words long). The buffer is accessed using two pointers, one for the ADC writing to the FIFO, one for the processor (DSP) reading from the buffer. Both pointers move in a clockwise direction. If the distance between the ADC write pointer and the DSP read pointer is greater or equal a programmable threshold, the INT signal is asserted. If this INT signal is connected to an external interrupt pin of the processor, it is possible to read out the stored values in the FIFO at once during the interrupt service routine. If the ADC write pointer reaches the position of the DSP read pointer, an overflow occurs. In this case, the overflow bit in the ADC register is set and the FOVL is asserted. 15 0 14 1 13 2 DSP 12 3 ADC 4 11 T 5 10 6 9 8 7 Figure 15. Circular Buffer 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 APPLICATION INFORMATION DMA transfer and FIFO The FIFO makes it possible to use the available interface bandwidth of the host processor more efficiently. The following is a description based on the TMS320C6201 DSP from TI. The TMS320C6201 memory interface has a limited bandwidth, for example 200MWPS at a clock rate of 200 MHz. The THS14F04x interface is asynchronous with a maximum speed of 300MWPS, which is approximately 7 clock cycles. If the DSP uses the DMA controller to read data from the DSP, the following conditions exist: D D DMA bus arbitration: 16 clock cycles THS14F0x read access: 7 clock cycles If, for example, 10 samples need to be read from the ADC without the FIFO, the memory interface will be allocated for (10 + 7) × 16 = 272 clock cycles in total. BUSarb R BUSarb R S S BUSarb R S BUSarb R S BUSarb R S With a FIFO programmed to a 10 sample threshold, the memory interface will be allocated for 16 + 7 × 10 = 86 clock cycles in total. BUS Available for Other Peripheral BUSarb R R R R BUSarb R R R R driving the analog input The THS14F01/3 ADCs have a fully differential input. A differential input is advantageous with respect to SNR, SFDR, and THD performance because the signal peak-to-peak level is 50% of a comparable single-ended input. There are three basic input configurations: D D D Fully differential Transformer coupled single-ended to differential Single-ended POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 APPLICATION INFORMATION fully differential configuration In this configuration, the ADC converts the difference (∆IN) of the two input signals on IN+ and IN–. 22 Ω IN+ 100 pF THS14F01/3 22 Ω IN– 100 pF Figure 16. Differential Input The resistors and capacitors on the inputs decouple the driving source output from the ADC input and also serve as first order low pass filters to attenuate out of band noise. The input range on both inputs is 0 V to AVDD. The full-scale value is determined by the voltage reference. The positive full-scale output is reached, if ∆IN equals ∆REF, the negative full-scale output is reached, if ∆IN equals –∆REF. ∆IN [V] OUTPUT –∆REF – full scale 0 0 ∆REF + full scale transformer coupled single-ended to differential configuration If the application requires the best SNR, SFDR, and THD performance, the input should be transformer coupled. The signal amplitude on both inputs of the ADC is one half as high as in a single-ended configuration thus increasing the ADC ac performance. 22 Ω IN+ 100 pF R THS14F01/3 22 Ω IN– 100 pF + CML 1 µF 0.1 µF Figure 17. Transformer Coupled IN [VPEAK] –∆REF OUTPUT [PEAK] – full scale† 0 0 ∆REF + full scale† † n = 1 (winding ratio) The resistor R of the transformer coupled input configuration must be set to match the signal source impedance R = n2 Rs, where Rs is the source impedance and n is the transformer winding ratio. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 APPLICATION INFORMATION single-ended configuration In this configuration, the input signal is level shifted by ∆REF/2. 10 kΩ + 10 kΩ 10 kΩ 10 kΩ IN+ 100 pF REF+ THS14F01/3 – 22 Ω IN– 100 pF + 10 kΩ REF– 10 kΩ Figure 18. Single-Ended With Level Shift The following table shows the input voltages for negative full-scale output, zero output, and positive full-scale output: ∆IN+ [V] OUTPUT –∆REF – full scale 0 0 ∆REF + full scale Note that the resistors of the op-amp and the op-amp all introduce gain and offset errors. Those errors can be trimmed by varying the values of the resistors. Because of the added offset, the op-amp does not necessarily operate in the best region of its transfer curve (best linearity around zero) and therefore may introduce unacceptable distortion. For ac signals, an alternative is described in the following section. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 APPLICATION INFORMATION ac-coupled single-ended configuration If the application does not require the signal bandwidth to include dc, the level shift shown in Figure 4 is not necessary. 10 kΩ 10 kΩ 10 kΩ 10 kΩ IN+ 100 pF REF+ THS14F01/3 – + 10 nF 22 Ω IN– 100 pF REF– 10 kΩ 10 kΩ Figure 19. Single-Ended With Level Shift Because the signal swing on the op-amp is centered around ground, it is more likely that the signal stays within the linear region of the op-amp transfer function, thus increasing the overall ac performance. IN [VPEAK] OUTPUT [PEAK] –∆REF – full scale 0 0 ∆REF + full scale Compared to the transformer-coupled configuration, the swing on IN– is twice as big, which can decrease the ac performance (SNR, SFD, and THD). 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 APPLICATION INFORMATION internal/external reference operation The THS14F01/3 ADC can either be operated using the built-in band gap reference or using an external precision reference in case very high dc accuracy is needed. ǒ Ǔ The REF+ and REF+ outputs are given by: REF )+ VBG 1 ) 23 and REF– ǒ Ǔ + VBG 1– 23 If the built-in reference is used, VBG equals 1.5 V which results in REF+ = 2.5 V, REF– = 0.5 V and ∆REF = 2 V. The internal reference can be disabled by writing 1 to D12 (REF) in the control register (address 3). The band gap reference is then disconnected and can be substituted by a voltage on the VBG pin. programmable gain amplifier The on-chip programmable gain amplifier (PGA) has eight gain settings. The gain can be changed by writing to the PGA gain register (address 1). The range is 0 to 7dB in steps of one dB. out of range indication The OV output of the ADC indicates an out of range condition. Every time the difference on the analog inputs exceeds the differential reference, this signal is asserted. This signal is updated the same way as the digital data outputs and therefore subject to the same pipeline delay. offset compensation With the offset register it is possible to automatically compensate system offset errors, including errors caused by additional signal conditioning circuitry. If the offset compensation is enabled (D7 (OFF) in the control register), the value in the offset register (address 2) is automatically subtracted from the output of the ADC. In order to set the correct value of the offset compensation register, the ADC result when the input signal is 0 must be read by the host processor and written to the offset register (address 2). test modes The ADC core operation can be tested by selecting one of the available test modes (see control register description). The test modes apply various voltages to the differential input depending on the setting in the control register. digital I/O The digital inputs and outputs of the THS14F01/3 ADC are 3-V CMOS compatible. In order to avoid current feed back errors, the capacitive load on the digital outputs should be as low as possible (50 pF max). Series resistors (100 Ω) on the digital outputs can improve the performance by limiting the current during output transitions. The parallel interface of the THS14F01/3 ADC features 3-state buffers, making it possible to directly connect it to a data bus. The output buffers are enabled by driving the OE input low. Refer to the read and write timing diagrams in the parameter measurement information section for information on read and write access. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 – JUNE 2000 MECHANICAL DATA PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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