TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 D D D D D D D D 1.2-GHz Operation Two Operating Modes: – Philips SA7025 Emulation Mode Pin-for-Pin and Programming Compatible – Extended Performance Mode (EPM) Dual RF – IF Phase-Locked Loops Fractional-N or Integer-N Operation Programmable EPM Fractional Modulus of 1–16 Normal, Speed-Up, and Fractional Compensation Charge Pumps 2.9-V to 5.1-V Operation Low-Power Consumption PW PACKAGE (TOP VIEW) CLOCK DATA STROBE VSS RFIN RFIN VCCP REFIN RA AUXIN 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD TSETUP LOCK/TEST RF RN VDDA PHP PHI VSSA PHA description The TRF2050 is a low-voltage, low-power consumption 1.2-GHz fractional-N/integer-N frequency synthesizer component for wireless applications. Fractional-N division and an integral speed-up charge pump are used to achieve rapid channel switching. Two operating modes are available: 1) SA7025 emulation mode in which the part emulates the Philips SA7025 fractional-N synthesizer and 2) extended performance mode (EPM), which provides additional features including fractional accumulator modulos from 1 to 16 (compared to only 5 or 8 for the SA7025) and programmable control of the speed-up mode duration (compared to the SA7025 method of holding the strobe line high). Along with external loop filters, the TRF2050 provides all functions necessary for voltage-controlled oscillator (VCO) control in a dual phase-locked loop (PLL) frequency synthesizer system. A main channel is provided for radio frequency (RF) channels and an auxiliary channel for intermediate frequency (IF) channels. The current-output charge pumps directly drive passive resistance-capacitance (RC) filter networks to generate VCO control voltages. Rapid main-channel frequency switching is achieved with a charge pump arrangement that increases the current drive and alters the loop-filter frequency response during the speed-up mode portion of the switching interval. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 functional block diagram† DATA CLOCK STROBE 2 1 Serial Control Shift Registers 3 Common Registers EPM Registers 7025 Registers Conversion and Selection‡ FMOD RFIN NF Control Lines 4 Fraction Compensation Fraction Accumulator EM RFIN 5 Compensation Charge Pump 17 RF 5 N 6 CN 18 8 CL 2 14 32/33 † Prescaler Phase Detector Main Divider (N/N+1) Proportional Charge Pump 16 PHP RN SM CN 2 NR EM+EA REFIN 12 8 Select 1 2 4 8 Reference Divider SA EA AUXIN 10 PA 4/1 NA 2 8 CL 2 Integral Charge Pump CK 13 4 18 Select 12 Phase Detector Auxiliary Divider Auxiliary Charge Pump 9 11 † Terminals 4, 7, 12, 15, and 20 are for supply voltage. Terminal 19 is for testing. These terminals are not shown. ‡ Conversion and selection block provides emulation of SA7025 64/65/72 triple-modulus prescaler operation using the TRF2050 32/33 dual-modulus prescaler. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PHI LOCK/ TEST RA PHA TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 Terminal Functions ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁ ÁÁ TERMINAL NAME NO. I/O DESCRIPTION AUXIN 10 I Auxiliary channel RF input CLOCK 1 I Serial interface clock signal DATA 2 I Serial interface data signal LOCK/ TEST 18 O Lock detector/test mode output PHA 11 O Auxiliary charge pump output PHI 13 O Integral charge pump output PHP 14 O Proportional charge pump output RFIN 5 I Prescaler positive RF input RFIN 6 I Prescaler negative RF input REFIN 8 I Reference frequency input signal RA 9 I Resistor to VSSA sets auxiliary charge pump reference current RN 16 I Resistor to VSSA sets proportional and integral charge pump reference current RF 17 I Resistor to VSSA sets compensation charge pump reference current STROBE 3 I Serial interface strobe signal TSETUP 19 I Test setup for pin 18. For lock detect output, pin 19 connects to VCC through a pullup resistor; for test mode output, pin 19 terminates to ground. VCCP VDD 7 Prescaler positive supply voltage 20 Digital supply voltage VDDA VSS 15 Analog supply voltage 4 Digital ground VSSA 12 Analog ground absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCCP, VDD, VDDA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 5.6 V Input voltage range, logic signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 5.6 V Operating ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values are with respect to VSSA. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 recommended operating conditions ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ MIN NOM MAX 2.9 4.8 5.1 Supply voltage, VCCP, VDD, VDDA High-level input voltage, VIH (CLOCK, DATA STROBE) 0.7 × VDD Low-level input voltage, VIL (CLOCK, DATA STROBE) – 0.3 Operating free-air temperature, TA – 40 UNIT V VDD + 0.3 0.3 × VDD 25 V V °C 85 dc electrical characteristics VDD = VDDA = VCCP = 3.6 V, over recommended operating free-air temperature range. internal registers: CN = 128, CL = 1, CK = 3, N = 3969, NF = 1, FMOD = 8, SM = 0, NA = 296, SA = 0, PA = 1. external components: RN = 18 kΩ, RF = 24 kΩ, RA = 100 kΩ (unless otherwise noted) ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ supply current: I = IDD + ICCP + IDDA ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ PARAMETER ISTANDBY Total standby supply currents IMAIN Operational supply currents IAUX Operational supply currents TEST CONDITIONS MIN TYP EM = EA = 0 (see Notes 2 and 3) MAX UNIT 200 µA EM = 1, EA = 0 (see Note 3) 7.0 mA EM = 0, EA = 1 (see Note 3) 1.5 mA ITOTAL Operational supply currents EM = EA = 1 (see Note 3) 7.5 NOTES: 2. VRN = VRA = VRF = VDDA 3. For optimum standby and operational current consumption, the following condition should be be maintained: VDD ≤ VDDA < VDD + 1. mA digital interface PARAMETER VOH VOL High-level output voltage IIH IIL High-level input current Low-level output voltage Low-level input current TEST CONDITIONS IOH = 2 mA IOL = – 2 mA LOCK/TEST MIN TYP MAX VDD – 0.5 UNIT V DATA CLOCK, DATA, CLOCK STROBE 0.5 V 10 µA 10 µA charge pump currents (see Figure 1) ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ auxiliary charge pump PARAMETER |IPHA| Output current PHA ∆IPHA |IPHA| Relative output current variation PHA (see Figure 1) ∆IPHA Output current matching PHA (see Figure 1) TEST CONDITIONS MIN TYP MAX UNIT VPHA = 0.5 VDDA 200 250 300 µA 2% 10% VPHA = 0.5 VDDA ± 50 µA proportional charge pump, normal mode, VRF = VDDA PARAMETER |IPHP-NM| Output current PHP ∆IPHP-NM |IPHP-NM| Relative output current variation PHP (see Figure 1) ∆IPHP-NM Output current matching PHP (see Figure 1) 4 POST OFFICE BOX 655303 TEST CONDITIONS MIN TYP MAX UNIT VPHP = 0.5 VDDA 400 500 600 µA 2% 10% VPHP = 0.5 VDDA • DALLAS, TEXAS 75265 ± 50 µA TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 charge pump currents (see Figure 1) (continued) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ proportional charge pump, speed-up mode, VRF = VDDA (see the section on speed-up mode operation) PARAMETER TEST CONDITIONS |IPHP-SM| Output current PHP VPHP = 0.5 VDDA ∆IPHP-SM |IPHP-SM| Relative output current variation PHP (See Figure 1) ∆IPHP-SM Output current matching PHP (See Figure 1) MIN TYP MAX 2 2.5 3 2% 10% ± 300 VPHP = 0.5 VDDA UNIT mA µA integral charge pump, speed-up mode, VRF = VDDA (see the section on speed-up mode operation) PARAMETER TEST CONDITIONS |IPHI-SM| Output current PHI VPHI = 0.5 VDDA ∆IPHI-SM |IPHI-SM| Relative output current variation PHI (see Figure 1) ∆IPHI-SM Output current matching PHI (see Figure 1) MIN TYP MAX 4.8 6 7.2 2% 8% VPHI = 0.5 VDDA UNIT mA ± 600 µA MAX UNIT fractional compensation proportional charge pump, normal mode, VRN = VDDA PARAMETER TEST CONDITIONS Output current PHP vs fractional numerator (see Note 4) |IPHP-F-NM| VPHP = 0.5 VDDA, MIN FNUM = 1 TYP µA 1.25 NOTE: 4. Fractional compensation current is proportional to the numerator content of the fractional accumulator (FNUM). charge pump leakage currents, VRN = VRA = VRF = VDDA PARAMETER IPHP IPHI IPHA TEST CONDITIONS MIN TYP VPHP = 0.5 VDDA VPHI = 0.5 VDDA ±10 Output current PHI Output current PHA VPHA = 0.5 VDDA ±10 Output current PHP MAX ±10 UNIT nA ac electrical characteristics, VDD = VCCP = VDDA = 3.6 V, TA = 25°C (unless otherwise noted) ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ main divider PARAMETER fRFIN RF input frequency VID_RFIN Differential RF input power TEST CONDITIONS 50-W single-ended characteristic impedance; ac-coupled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ MIN – 20 TYP MAX UNIT 1.2 GHz 0 dBm 5 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 ac electrical characteristics, VDD = VCCP = VDDA = 3.6 V, TA = 25°C (unless otherwise noted) (continued) ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ auxiliary divider fAUXIN ZAUXIN PARAMETER TEST CONDITIONS Auxiliary y input frequency q y (ac-coupled) ( ) reference divider PARAMETER Reference input frequency VI_REFIN Reference input voltage ZREFIN Reference input in ut impedance im edance MIN MAX UNIT 125 70 MHz MHz PA = 0: VDDA = VDD = 4.8 V VI_AUXIN = 200 mVpp 110 MHz PA = 1: VDDA = VDD = 3.6 V VI_AUXIN = 200 mVpp 40 MHz PA = 1: VDDA = VDD = 4.8 V VI_AUXIN = 200 mVpp 72 MHz 5 Auxiliary input in ut impedance im edance fREFIN ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PA = 0: VDDA = VDD = 3.6 V VI_AUXIN= 560 mVpp VI_AUXIN = 200 mVpp TEST CONDITIONS ac-coupled MIN TYP 100 kΩ 3 pF TYP MAX UNIT 40 MHz 200 mVpp 100 kΩ 3 pF timing requirements, serial data interface (see Figure 2) MIN MAX UNIT 10 MHz fCLOCK Clock frequency tw_CLKHI tw_CLKLO Clock high time pulse width, CLOCK high 30 ns Clock low time pulse width, CLOCK low 30 ns tsu_Data Setup time, data valid before CLOCK↑ 30 ns th_Data Hold time, data valid after CLOCK↑ 30 ns th_Strobe tsu_Strobe Hold time, STROBE high before CLOCK↑ 30 ns Setup time, STROBE low after CLOCK↑ 30 ns tw_STRBHI STROBE high time pulse width, STROBE high 50 ns 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION charge-pump current output definitions Current I2 ∆ IOUT REL I1 ∆ IOUT MATCH ISINK V1 V2 Voltage ISOURCE I2 ∆ IOUT REL I1 Figure 1. Charge-Pump Output Current Definitions The relative output current variation is defined as the percent difference between charge-pump current output at two charge-pump output voltages and the mean charge-pump current output (see Figure 1): DIOUT Ť I Ť REL OUT MEAN ǒ Ǔ Ťǒ ) ǓŤ +2 I2 – I1 I2 I1 × 100%; with V 1 + 0.7 V, V2 + VDDA–0.8 V. Output current matching is defined as the difference between charge-pump sinking current output and charge-pump sourcing current output at a given charge-pump output (see Figure 1). ∆ IOUT MATCH = ISINK – ISOURCE; with V1 ≤ Voltage ≤ V2. serial-data interface timing Change Valid DATA tsu_Data D1 D0 VH D31 D30 VL th_Data tw_CLKLO tw_CLKHI VH CLOCK VL th_Strobe tsu_Strobe STROBE VH tw_STRBHI VL Figure 2. Serial-Data Interface Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 TYPICAL CHARACTERISTICS MAIN DIVIDER MINIMUM INPUT POWER vs FREQUENCY AND TEMPERATURE MAIN DIVIDER INPUT POWER vs FREQUENCY AND SUPPLY VOLTAGE 0 0 Main Divider Minimum Input Power – dBm –10 –20 5.1 V 4.4 V –30 2.9 V 3.6 V –40 –50 VCCP = VDD = VDDA = 4.8 V N = 4000 –10 –20 t = 85°C –30 t = –40°C t = 25°C –40 –50 Figure 3 1250 1150 1200 1100 1050 950 1000 900 REFERENCE DIVIDER MINIMUM INPUT POWER vs FREQUENCY AND TEMPERATURE 10 Reference Divider Minimum Input Power – dBm 10 Reference Divider Minimum Input Power –dBm 850 Figure 4 REFERENCE DIVIDER MINIMUM INPUT POWER vs FREQUENCY AND SUPPLY VOLTAGE TA = 25°C N = 100 5 0 5.1 V –5 –10 4.4 V –15 –20 3.6 V –25 –30 –35 10 15 20 25 30 35 40 45 50 55 VCCP = VDD = VDDA = 4.8 V NR = 100 5 0 –5 –10 t = –40°C –15 –20 t = 25°C t = 85°C –25 –30 –35 –40 10 f – Frequency – MHz 20 30 40 Figure 6 POST OFFICE BOX 655303 50 f – Frequency – MHz Figure 5 8 800 f – Frequency – MHz f – Frequency – MHz –40 700 750 500 550 1250 1150 1200 1050 1100 950 1000 850 900 800 750 700 650 600 500 550 650 –60 –60 600 Main Divider Input Power – dBm TA = 25°C N = 4000 • DALLAS, TEXAS 75265 60 70 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 TYPICAL CHARACTERISTICS AUXILIARY DIVIDER MINIMUM INPUT POWER vs FREQUENCY AND SUPPLY VOLTAGE AUXILIARY DIVIDER MINIMUM INPUT POWER vs FREQUENCY AND TEMPERATURE 5 Auxiliary Divider Minimum Input Power – dBm Auxiliary Divider Minimum Input Power – dBm 5 TA = 25°C PA = 1 N = 100 0 –5 –10 3.6 V –15 4.4 V 5.1 V –20 –25 –30 –35 –40 –45 –50 –5 –10 t = –40°C –15 –20 t = 25°C –25 t = 85°C –30 –35 –40 –45 –50 5 10 15 20 25 30 35 40 45 50 55 60 65 VCCP = VDD = VDDA = 4.8 V PA = 1 N = 100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 f – Frequency – MHz f – Frequency – MHz Figure 7 Figure 8 AUXILIARY DIVIDER MINIMUM INPUT POWER vs FREQUENCY AND TEMPERATURE 5 5 TA = 25°C PA = 0 NA = 100 0 –5 –10 Auxiliary Divider Minimum Input Power – dBm Auxiliary Divider Minimum Input Power – dBm AUXILIARY DIVIDER MINIMUM INPUT POWER vs FREQUENCY AND SUPPLY VOLTAGE 4.4 V 3.6 V 5.1 V –15 –20 –25 –30 –35 –40 –45 –50 5 25 50 75 100 125 150 175 200 VCCP = VDD = VDDA = 4.8 V PA = 0 t = –40°C N = 100 0 –5 –10 –15 t = 85°C –20 –25 t = 25°C –30 –35 –40 –45 –50 5 25 f – Frequency – MHz 50 75 100 125 150 175 200 f – Frequency – MHz Figure 9 Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 TYPICAL CHARACTERISTICS CH1 S11 1 µFS 2: 37.43 Ω –160.98 Ω 1.0245 pF 965.000 000 MHz 1: 89.063 Ω –272.88 Ω 500 MHz 3: 16.773 Ω –127.36 Ω 1.4 GHz 2 1 3 START 500.000 MHz STOP 1 400.000 MHz Figure 11. Typical RFIN Impedance (S11) 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 C22 .1 µ F 2 1 OUT GND NDK_OSC VCC VCONT TCXO C30 1000 pF VOSC1 J3 3 4 OUT GND MOD 5 7 8 GND OUT GND GND 6 GND GND VT C20 .1 µ F 4 3 2 1 10 11 12 9 18 C39 100 pF R15 18 R11 J2 + C38 1µF C31 1000 pF VOSC2 C11 .1 µ F J1 18 R12 C7 .1 µ F 16 15 14 13 GND C31 22 pF .022 µ F C23 VDD C33 1000 pF AUX1_VCO VCO190–S AVT 4 5 6 VOSC3 MQE001 VCC GND C34 22 pF C26 22 pF 3 2 VT VCC M_VCO GND 1 GND GND GND MOD • DALLAS, TEXAS 75265 GND POST OFFICE BOX 655303 GND MVT 18 R24 C43 220pF R26 18 18 R23 100 pF C9 R10 100 pF 49.9 C8 R25 49.9 STRB DTA CLK 220pF C24 R16 110 k VSS 9 8 AUX 10 RA REF TSET VDD PHA VSSA PHI PHP VDDA RN RF LOCK U1 TRF2050 AUX RA REF 5 RFIN RFIN 6 RFIN VDD 7 VCCP RFIN AGND 4 1 CLK 2 DATA 3 STRB 11 PHA 12 VSSA 13 PHI 14 PHP 15 VDDA 16 RN 17 RF 18 19 TSETUP 20 VDD C5 .1 µ F LOCK/TEST VDD Test 3 Lock 1 C19 1800 pF R21 36 k C21 .039 µ F R22 9.1 k JP1 VDDA C14 180 pF 0 C13 47 pF R18 12 k C17 470 pF 3.9 k R19 R13 18 k R17 C18 1200 pF 12 k R20 C10 .1 µ F 10 k R9 VDD R14 30 k C16 DNP AVT C16 180 pF MVT TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 APPLICATION INFORMATION Figure 12. Evaluation Board Schematic (Part 1 of 2) 11 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Figure 12. Evaluation Board Schematic (Part 2 of 2) + C1 4.7 µ F C32 .1 µ F GND HUB AGND DGND HUB VT 1 1k R5 3 2 W CW 220 R1 8 NC 7 VO 6 VO 5 NC VR1 LOCK LM317LBD 2 VO 3 VO 4 A 1 STROBE DATA CLOCK + R27 1.8 k C2 1 µF VDDA C29 .1 µ F VDDA Note: Evaluation board dc supply circuitry and PC interface only GND SUPPLY POWER 24 12 25 13 11 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 1 VT 1 U2 8 NC 7 VO 6 VO 5 NC VR2 1k R6 3 2 W 220 CW R28 1.8 k + VDD C28 .1 µ F 4N28S 4 1 5 R32 6.2 k 2 C3 1 µF VDD 6 CLOCK LM317LBD R2 2 VO 3 VO 4 A 1 2 4N28S 4 1 5 R31 6.2 k VT 6 8 NC 7 VO 6 VO 5 NC VR3 R7 620 270 U4 + C4 1 µF R30 2.7 k 6 STROBE C32 .1 µ F VOSC1 4N28S 4 2 1 5 R33 6.2 k LM317LBD R3 2 VO 3 VO 4 A 1 U3 DATA R29 1.8 k VDD VT 8 NC 7 VO 6 VO 5 NC VR4 R36 820 U5 6 270 + C25 1 µF C35 .1 µ F VOPTO MOC8030 LM317LBD R35 2 VO 3 VO 4 A 1 4 5 VOPTO 2 1 VT R8 820 C5 1 µF 8 NC 7 VO 6 VO 5 NC VR6 R38 390 270 + VT 2 VO 3 VO 4 A 1 LM317LBD R37 C36 .1 µ F VOSC2 270 8 NC 7 VO 6 VO 5 NC VR5 CLOCK DATA STROBE LOCK/TEST LM317LBD R4 2 VO 3 VO 4 A 1 LOCK/TEST R34 1.8 k + C37 1 µF VOSC3 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 APPLICATION INFORMATION TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 APPLICATION INFORMATION Table 1. TRF2050 Evaluation Board Parts List DESIGNATORS DESCRIPTION VALUE QTY SIZE (mm) MANUFACTURER MANUFACTURER P/N C1 Capacitor 4.7 uF 1 “A” 3.2x1.6 Venkel TA010TCM475KAR C2, 3, 4, 5, 25, 37, 38 Capacitor 1.0 uF 7 “A” 3.2x1.6 Venkel TA025TCM105KAR C6, 7, 10, 11, 20, 22, 27, 28, 29, 32, 35, 36 Capacitor 0.1 uF 12 0603 1.6x.08 Murata GRM39Y5V104Z016 C8, 9, 39 Capacitor 100 pF 3 0603 1.6x.08 Murata GRM39COG series C13 Capacitor 47 pF 1 0603 1.6x.08 Murata GRM39COG series C14, 16 Capacitor 180 pF 2 0603 1.6x.08 Venkel C0603COG series C15 Capacitor Not Used C17 Capacitor 470 pF 1 0603 1.6x.08 Murata GRM39X7R series C18 Capacitor 1200 pF 1 0603 1.6x.08 Murata GRM39X7R series C12, 30, 33 Capacitor 1000 pF 3 0603 1.6x.08 Murata GRM39X7R series C19 Capacitor 1800 pF 1 0603 1.6x.08 Venkel C0603X7R series C21 Capacitor .039 pF 1 1210 3.2x2.5 Panasonic ECH–U1H393JB C23 Capacitor .022 uF 1 0603 1.6x.08 Murata GRM39X7R series C24, 40 Capacitor 220 pF 2 0603 1.6x.08 Murata GRM39X7R series C26, 31, 34 Capacitor 22 pF 3 0603 1.6x.08 Murata GRM39COG series R1, 2 Resistor 2 0603 1.6x.08 Panasonic ERJ–3GSYJ221 R3, 4, 35, 37 Resistor 4 0603 1.6x.08 Panasonic ERJ–3GSYJ271 R5, 6 Resistor R7 Resistor R8, 36 Resistor R9 Resistor R10, 25 Resistor 49.9 W R11, 12, 15, 23, 24, 26 Resistor R13 Resistor R14 Resistor R16 Resistor R17, 20 Resistor R18 Resistor R19 Resistor R21 Resistor 220 W 270 W 1 kW 0603 1.6x.08 Not Used 2 .25” square 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series 2 0603 1.6x.08 Panasonic ERJ–3GSYJ series 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series 2 0603 1.6x.08 Panasonic ERJ–3EKF49R9 18 W 6 0603 1.6x.08 Panasonic ERJ–3GSYJ series 18 kW 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series 2 0603 1.6x.08 Panasonic ERJ–3GSYJ series 1 0603 1.6x.08 Venkel 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series 4 0603 1.6x.08 Panasonic ERJ–3GSYJ series 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series 3 0603 1.6x.08 Panasonic ERJ–3GSYJ series 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series 620 W 820 W 10 kW 30 kW 110 kW 12 kW 0W 3.9 kW 36 kW 9.1 kW R22 Resistor R27, 28, 29, 34 Resistor R30 Resistor R31, 32, 33 Resistor R38 Resistor U1 Integrated circuit 1 U2, 3, 4 Optoelectronics 3 1.8 kW 2.7 kW 6.2 kW 390 W POST OFFICE BOX 655303 Bourns TI 730C–04 • DALLAS, TEXAS 75265 Motorola 3269W001102 CR0603–16W–000J1 TRF2050 4N28S 13 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 APPLICATION INFORMATION Table 1. TRF2050 Evaluation Board Parts List (Continued) DESIGNATORS DESCRIPTION U5 Optoelectronics VALUE 1 VR1, 2, 3, 4, 5, 6 Voltage regulator 6 P1 Para. connector 1 J1, 2, 3 SMA connector TP1 to TP8 Test point Main VCO SIZE (mm) QTY 730C–04 SO–8 MANUFACTURER Motorola MANUFACTURER P/N MOC8030S National Semiconductor LM317LM AMP 747238–4 3 EF Johnson 8 Components Corp. Voltage-controlled oscillator 1 Murata MQE001 TCXO Temp.-compensated crystal oscillator 1 Toyocom TCO–980 AUX VCO Voltage-controlled oscillator 1 Vari-L Comp. Assorted ATTEN 10 dB RL 0 dBm D 142–0701–831 TP–105–01 series VCO190–S VAVG 10 10 dB/ MKR D 1.00 kHz – 48.83 dB CENTER 926.66977 MHz RBW 100 Hz VBW 100 Hz SPAN 10.00 kHz SWP 802 ms Figure 13. Close-in Noise at 926.67 MHz; MODULO – 8; NF = 1; CN = 64 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 APPLICATION INFORMATION VAVG 25 10 dB/ ATTEN 10 dB RL 0 dBm D MKR D 30.0 kHz – 63.17 dB CENTER 914.1900 MHz RBW 1 kHz VBW 1 kHz SPAN 100.00 kHz SWP 250 ms Figure 14. Fractional Spurs, fVCO = 914.19 MHz; MODULO – 8; NF = 1; CN = 64 VAVG 25 10 dB/ ATTEN 10 dB RL 0 dBm D MKR D 30.0 kHz – 63.34 dB CENTER 939.1500 MHz RBW 1 kHz VBW 1 kHz SPAN 100.00 kHz SWP 250 ms Figure 15. Fractional Spurs, fVCO = 939.15 MHz; MODULO – 8; NF = 1; CN = 64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 APPLICATION INFORMATION VAVG 25 10 dB/ ATTEN 10 dB RL 0 dBm D MKR D 30.0 kHz – 64.16 dB CENTER 914.3700 MHz RBW 1 kHz VBW 1 kHz SPAN 100.00 kHz SWP 250 ms Figure 16. Fractional Spurs, fVCO = 914.37 MHz; MODULO – 8; NF = 7; CN = 64 VAVG 25 10 dB/ ATTEN 10 dB RL 0 dBm D MKR D 30.0 kHz – 63.50 dB CENTER 939.3300 MHz RBW 1 kHz VBW 1 kHz SPAN 100.0 kHz SWP 250 ms Figure 17. Fractional Spurs, fVCO = 939.33 MHz; MODULO – 8; NF = 7; CN = 64 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION serial programming input The TRF2050 internal registers are programmed using a three-wire (CLOCK, DATA, STROBE) serial interface. The serial data is structured into 24-bit standard-length or 32-bit long-length words of which one or four bits are dedicated address bits. The flag LONG in the D-Word determines whether the A0 (LONG = 0) or A1 (LONG = 1) format is applicable. Figures 18 and 19 show the format of the serial data for two modes of TRF2050 operation: SA7025 and EPM, respectively. The least significant bit (LSB) of the C-Word determines the operational mode of the TRF2050: 0 = SA7025, 1 = EPM. In SA7025 mode, the TRF2050 emulates the Philips SA7025 with respect to serial programming. Microcontroller software written for the SA7025 works transparently when the TRF2050 is operated in SA7025 emulation mode. Figure 2 shows the timing diagram of the serial input. When the STROBE signal is low, the signal on the DATA input is clocked into a shift register on the positive edges of the CLOCK. When the STROBE signal is high, depending on the 1 or 4 address bit(s), the data is latched into different working registers or temporary registers. In order to fully program the synthesizer, four words must be sent: D, C, B, and A. The E-Word is for testing purposes only. The A-Word contains new data for the main divider. The A-Word is loaded only when a main divider synchronization signal is also active. This is done to avoid phase jumps during reprogramming the main divider. The synchronization signal is generated by the main divider. When the TRF2050 is operated in SA7025 emulation mode, programming the A-Word sets the main charge pumps, which are located on outputs PHP and PHI, into speed-up mode, as long as the STROBE is high. When the TRF2050 is operated in EPM mode, speed-up mode duration is determined by field G in the B-Word. NOTE: The C-Word must be sent during the first programming cycle after power-up in order to set the mode of operation (7025 or EPM). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION MSB (Last In) D31 LSB (First In) D0 WORD NM2 A1 0 NF NM1 NM3 CN NM2 D23 D0 NM2 A0 0 NF NM1 NM3 PR = 01 NM2 B 1 0 0 0 0 0 0 0 C 1 0 0 1 NA P A 0 0 0 0 0 MS D 1 0 1 0 NR F L E E MO SM M SA A O N D G E 1 1 1 1 CN CK CL PR = 10 PR RESERVED SET TO ZERO T Figure 18. Serial Word Format for SA7025 Emulation Mode 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Table 2. SA7025 Emulation Serial-Word-Format Function Listing SYMBOL BITS CK 4 Binary acceleration factor for integral charge pump current FUNCTION CL 2 Binary acceleration factor for proportional charge pump current CN 8 Binary current-setting factor for main charge pumps EA 1 Auxiliary divider enable flag: 0 = disabled 1 = enabled EM 1 Main divider enable flag: 0 = disabled 1 = enabled FMOD 1 Fractional-N modulus selection: 0 = modulo 5 1 = modulo 8 LONG 1 A word format selection: 0 = 24-bit A0 format 1 = 32-bit A1 format MS 2 Mode select 00 = 7025 Emulation Mode NA 12 Auxiliary divider ratio NF 3 Fractional-N increment NM1 12 Number of main divider cycles when prescaler modulus = 64 NM2 8 if PR = 01 4 if PR = 10 Number of main divider cycles when prescaler modulus = 65 NM3 4 if PR = 10 Number of main divider cycles when prescaler modulus = 72 NR 12 Reference divider ratio PA 1 Auxiliary prescaler select: 0 = divide by 4 1 = divide by 1 PR 2 Prescaler type: PR = 01; modulus 2 prescaler (64/65) PR = 10; modulus 3 prescaler (64/65/72) SA 2 Reference select for auxiliary phase detector SM 2 Reference select for main phase detector T 2 Test mode connection of internal signals to the LOCK terminal: 00 = ACCU overflow 01 = Auxiliary divider 10 = Main divider 11 = Reference divider POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION MSB (Last In) LSB (First In) D0 D23 WORD A0 0 NF N 0 G CN CK M A CL C C P P B 1 0 0 0 C 1 0 0 1 NA P A D 1 0 1 0 NR E SA E 0 0 SM M A E 1 1 1 1 FMOD RESERVED SET TO ZERO MS T Figure 19. Serial Word Format for Extended Performance Mode (EPM) 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ Table 3. Extended Performance Mode Function Table SYMBOL BITS SAME AS SA7025 MODE ACP 1 No Auxiliary charge polarity: 0 = positive 1 = negative CK 4 Yes Binary acceleration factor for integral charge pump current FUNCTION CL 2 Yes Binary acceleration factor for proportional charge pump current CN 8 Yes Binary current setting factor for main charge pumps EA 1 EM 1 Yes Main divider enable flag: 0 = disabled 1 = enabled FMOD 5 No Fraction accumulator modulus G 4 No Speed-up mode duration (See Table 9) MCP 1 No Main charge pump polarity: 0 = positive 1 = negative MS 2 No Mode select 01 = Extended Performance Mode Auxiliary divider enable flag: 0 = disabled 1 = enabled N 18 No Overall main divider integer division ratio (NM) NA 12 Yes Auxiliary divider ratio NF 4 No Fractional-N increment NR 12 Yes Reference divider ratio PA 1 Yes Auxiliary prescaler select: 0 = divide by 4 1 = divide by 1 SA 2 Yes Reference select for auxiliary phase detector SM 2 Yes Reference select for main phase detector T 2 Yes Test mode connection of internal signals to the LOCK terminal: 00 = ACCU overflow 01 = Auxiliary divider 10 = Main divider 11 = Reference divider POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION main divider – general (see Figure 20) The differential RFIN inputs are amplified to internal ECL logic levels and provide excellent sensitivity (better than –20 dBm at 1 GHz), making the prescaler ideally suited for direct interface with a VCO. The internal dual-modulus (32/33) prescaler and counter sections divide the VCO frequency down to the reference phase detector frequency. The prescaler division ratio (÷32 or ÷33) is controlled by a feedback signal that is a function of the 18-bit N-field counters. The N-field counter section is composed of two separate counters: a 5-bit A-Counter and a 13-bit B-Counter. The prescaler divides by 33 until the A-Counter reaches terminal count and then divides by 32 until the B-Counter reaches terminal count, whereupon both counters reset and the cycle repeats. The following equation relates the total N division as a function of the 32/33 prescaler: NTotal = 32 (B – A) + 33(A), where 0 ≤ A ≤ 31, and 31 ≤ B ≤ 8191. It is not necessary to determine the values of A and B in the equation above; simply program the N field with the total division ratio desired (fractional effects ignored). The N-division ratio has a range of 992 ≤ NTotal ≤ 262143. Structure of N-Word 5-Bit A-Counter N A 13 5 13 Bits LSB 18-Bit Register MSB 18 18 N FMOD to Phase Detector B 5 Bits NF 13-Bit B-Counter 32/33 Prescaler RFIN 4 5 18-Bit Adder 5-Bit Fraction Accumulator Figure 20. Main Divider Organization main divider – SA7025 emulation The internal triple modulus prescaler configuration of the SA7025 provides for prescaler division ratios of 64/65/72. The TRF2050 has internal conversion logic that allows the TRF2050 to emulate the SA7025 main divider operation. When operated in SA7025 emulation mode, the TRF2050 is programmed using the SA7025 serial interface format shown in Figure 18. The TRF2050 internal conversion is transparent and need not be considered under normal use, thereby allowing use of existing SA7025 programming codes without change. The following equations relate the total N-division as a function of the emulated 64/65 dual-modulus and 64/65/72 triple-modulus prescalers: NTotal = 64 (NM1 + 2) + 65 (NM2), where PR = 01 and NTotal = 64 (NM1 + 2) + 65 (NM2) + 72 (NM3 + 1), where PR = 10. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION For contiguous channels, the following rules must be observed: For PR = 01: 61 ≤ NM1 ≤ 4095 and 0 ≤ NM2 ≤ 63, which yields minimum and maximum divide ratios of 4032 and 266303, respectively. For PR = 10: 14 ≤ NM1 ≤ 4095 and 0 ≤ NM2 ≤ 15, and 0 ≤ NM3 ≤ 15, which yields minimum and maximum divide ratios of 1096 and 264335, respectively. main divider – synchronization The A-Word is loaded only when a main divider synchronization signal is active. This prevents phase jumps when reprogramming the main divider. The synchronization signal is generated by the main divider, and it is active while the main divider is counting down from the programmed value. When the main divider reaches its terminal count, a main divider output pulse is sent to the main phase detector. Also at this time, the loading of the A-Word is disabled. Therefore, to correctly load the new A-Word, the STROBE signal must be active high for at least a minimum number of VCO input cycles at RFIN. main divider – fractional accumulator The TRF2050 main synthesizer loop can operate as a traditional integer-N feedback PLL or as a fractional-N feedback PLL. The integer-N feedback loop divides the VCO frequency by integer values of N, which results in phase detector reference comparisons at the desired channel spacing. A fractional-N feedback loop divides the VCO frequency by an integer term plus a fractional term, which results in phase detector reference comparisons at integer multiples of the desired system channel spacing. Integer-N division: VCO frequency N = phase detector reference frequency = channel spacing Fractional-N division: VCO Frequency (N + NF/FMOD) = phase detector reference frequency where 0 ≤ NF < FMOD and 1 ≤ FMOD ≤ 16. = FMOD × channel spacing Because the main counter and prescaler sections cannot divide by a fraction of an integer, the fractional-N division is accomplished by averaging main divider cycles by N and N+1. A fractional accumulator is programmed with values of NF and FMOD to control the main counter and prescaler sections to divide by N or N+1. The fractional accumulator operates modulo FMOD and is incremented by NF at the completion of each main divider cycle. When the fractional accumulator overflows, division by N+1 occurs. Otherwise, the main counters and prescaler divide by N; division by N+1 is transparent to the user. Table 4 shows the contents of the fractional accumulator and the resulting N or N+1 division for two fractional division ratios. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION Table 4. Fractional Accumulator Operation NF = 3, FMOD = 8 ACCUMULATOR NUMERATOR STATE NF = 6, FMOD = 8 ACCUMULATOR NUMERATOR STATE 3 ÷N 6 ÷N 6 ÷N 4 ÷ N + 1, overflow 1 ÷ N + 1, overflow 2 ÷ N + 1, overflow 4 ÷N 0 ÷ N + 1, overflow 7 ÷N 6 ÷N 2 ÷ N + 1, overflow 4 ÷ N + 1, overflow 5 ÷N 2 ÷ N + 1, overflow 0 ÷ N + 1, overflow 0 ÷ N + 1, overflow For example, suppose that a typical AMPS channel of 953.25 MHz is desired. Because AMPS channel spacing is 30 kHz, for fractional-N operation the main phase detector reference frequency must be a multiple of 30 kHz; 240 kHz is typical. A value of FMOD = 8 is selected because 240 kHz / 30 kHz = 8. Dividing the channel frequency by the reference frequency results in 953.13 ÷ 240 kHz = 3971.375 = 3971 + 3/8. This example is shown in Table 4 where NF = 3 and FMOD = 8. The table shows that over the period of a complete fractional accumulator cycle, the fractional accumulator overflows three times for every eight main divider cycles. Figure 21 illustrates the division by N or N+1 for this 3/8 fractional channel example. Number of Main Divider Pulses N (3971) N (3971) N+1 (3972) N (3971) N (3971) N+1 (3972) N (3971) N+1 (3972) RF Input Main Divider Out Figure 21. 3/8 Fractional Channel Main Divider Operation The mean division over the complete fractional accumulator cycle as shown in Figure 21 is: + 3971 ) 3971 ) 3972 ) 3971 )8 3971 ) 3972 ) 3971 ) 3972 + 3971.375 + 3971 ) 3ń8 1 Therefore, fractional channels are available every 30 kHz or 240 kHz + 2408kHz. FMOD N MEAN main divider – integer channels In the case where NF = 0, only division by N occurs, and the fractional accumulator is essentially in a steady state with a numerator of 0. It never increments or overflows. A channel that requires NF = 0 is a pure integer channel because the fractional term of NF is zero. FMOD 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION main divider – fractional-N sidebands and compensation Programming a fractional-N channel means the main divider and prescaler divide by N or N + 1 as dictated by the operation of the fractional accumulator. Because the main divider operation is integer in nature and the desired VCO frequency is not, the output of the main phase detector is modulated with a resultant fractional-N phase ripple that produces sideband energy if left uncompensated. This phase ripple is proportional and synchronized to the contents of the fractional accumulator that is used to control fractional-N sideband compensation. Only channels that require a nonzero value of NF have the fractional-N sideband energy. The fractional-N sidebands, which appear at offset frequencies from the VCO fundamental tone, are multiples of NF/FMOD. Figure 22 shows the fractional-N phase detector ripple for a 3/8 fractional channel. 240 kHz Main Phase Detector Reference Main Phase Detector VCO Feedback Main Phase Detector Fractional-N Ripple Fractional Accumulator State 0 3 6 1 4 7 2 5 0 Figure 22. Fractional-N Phase Detector Ripple for 3/8 Channel The TRF2050 has internal circuitry that provides a means to compensate for the phase detector fractional-N phase ripple, thereby significantly reducing the magnitude of the fractional-N sidebands. Because the current waveform output of the main PLL proportional charge pumps is modulated with the phase detector fractional-N phase ripple, a fractional-N compensation charge-pump output is summed with the main PLL proportional charge pump. Figure 23 shows the fractional-N ripple magnitude on the main PHP charge-pump output. The magnitude is essentially constant, and the pulse width is modulated with the contents of the fractional accumulator. The area under the main PHP charge-pump curve represents the amount of charge delivered to the loop filter network. In order to minimize fractional-N sidebands in the VCO spectrum, the compensation current waveform is generated to have equal and opposite sign magnitude area to the main PHP charge pump. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION Fractional Accumulator State Main PHP Charge Pump Fractional-N Ripple Magnitude 0 3 6 1 4 7 2 5 0 Pulse-Width Modulation mA µA Compensation Charge Pump Fractional-N Ripple Magnitude Pulse-Amplitude Modulation Figure 23. Main PHP and Compensation Charge Pump Fractional-N Waveforms for 3/8 Channel The compensation waveform is pulse-amplitude modulated with the contents of the fractional accumulator. The main PHP pulse magnitude is much larger than the compensation pulse magnitude but the compensation pulse has a much longer duration than that of the main PHP pulse. The compensation pulse is optimally centered about the main PHP charge pump pulse in order to avoid additional sideband energy due to the phase offset between the main and compensation pulses. The following example illustrates a method for determining correct values for RN, RF, and CN for minimal fractional-N sidebands based on VCO frequency and reference frequency. Assumptions: The main VCO is locked on channel. 953 MHz ± 10 MHz main VCO operation, 942.99 – 962.91 MHz 19.44 MHz reference frequency 240 kHz phase detector reference frequency 500 µA peak main PHP current 1. Determine the fundamental fractional-N pulse width portion of the main PHP charge-pump output waveform for the lower, upper, and mean frequencies. Frac PW–LWR + f1 – PD N f VCO + 2401kHz – 3929 942.99 MHz + 132.557 ps, 4012 + 2401kHz – 962.91 + 129.815 ps, MHz PD VCO Frac ) FracPW–UPR + 132.557 ps ) 129.815 ps + 131.186 ps. PW*LWR Frac + PW–MEAN Frac PW–UPR + f1 – N f 2 2 The mean-unit pulse width of the fractional-N portion of the main PHP charge-pump output waveform over the VCO frequencies of interest is 131.186 ps. This fundamental pulse width is modulated by the contents of the fractional accumulator. For the 3/8 fractional-N channel example, the pulse width varies as shown in Table 5. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION Table 5. Main PHP Fractional-N Pulse-Widths and Areas for 3/8 Channel NF = 3, FMOD = 8 ACCUMULATOR STATE MAIN PHP FRACTIONAL PULSE WIDTH (ps) MAIN PHP FRACTIONAL AREA (ps X AMPS) 3 3 x PW–Mean = 393.558 393.558 ps x 500 µA = .196779 6 6 x PW–Mean = 787.116 787.116 ps x 500 µA = .393558 1 1 x PW–Mean = 131.186 131.186 ps x 500 µA = .065593 4 4 x PW–Mean = 524.744 524.744 ps x 500 µA = .262372 7 7 x PW–Mean = 918.302 918.302 ps x 500 µA = .459151 2 2 x PW–Mean = 262.372 262.372 ps x 500 µA = .131186 5 5 x PW–Mean = 655.930 655.930 ps x 500 µA = .327965 0 0 x PW–Mean = 0 0 ps x 500 µA = 0 Table 5 also shows the area of the fractional-N portion of the main PHP charge-pump waveform.1 2. Determine the pulse width of the compensation charge-pump output waveform. Comp PW + f 1 + 19.441 MHz + 51.440 ns Ref 3. Determine the fundamental compensation charge-pump current magnitude using the fundamental main PHP fractional area. Comp Frac Area + 0.065593 psA + 1.275 mA + Mag 51.440 ns Comp PW Table 6 shows the magnitude of the compensation pulse as a function of the fractional accumulator. Table 6. Compensation Pulse Magnitudes for 3/8 Channel NF = 3, FMOD = 8 Accumulator Numerator Compensation Pulse Magnitude (µA) 3 3 x 1.275 = 3.825 6 6 x 1.275 = 7.651 1 1 x 1.275 = 1.275 4 4 x 1.275 = 5.101 7 7 x 1.275 = 8.926 2 2 x 1.275 = 2.550 5 5 x 1.275 = 6.376 0 0 x 1.275 = 0 4. Using the result of step 3, determine the value of RF to give the fundamental compensation pulse magnitude. RF (kW) + Comp25 (mA) Mag 25 + 19.6 kW. + 1.275 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION1234 5. Determine the values of CN and RN for the main PHP charge-pump peak current of 500 µA. Assume that a midrange value of CN equals 128. RN(kW) + ǒ 18.75 CN 256 1 I(mA) Ǔ – 0.75 + ǒ 18.75 128 256 Ǔ 1 – 0.75 0.5 mA + 18 kW 6. The value of the fundamental compensation pulse magnitude calculated in step 3 is fixed and the compensation pulse width calculated in step 2 is also fixed. However, because the VCO can tune over a significant range of frequencies, the pulse width of the fractional-N portion of the main PHP charge-pump waveform varies; thus, the area of the same waveform varies. In order to maintain equal areas under the fractional-N portion of the main PHP charge-pump and compensation waveforms, CN must vary with the VCO frequency. As the VCO frequency increases, the fractional-N portion of the main PHP charge-pump waveform pulse width decreases proportionally, thereby decreasing the area under the same waveform. Therefore, CN is adjusted to equalize the main PHP and compensation waveform areas, as follows: FracPW-LWR = 132.557 ps for fVCO = 942.99 MHz FracPW-UPR = 129.815 ps for fVCO = 962.91 MHz The fundamental area of the fractional-N portion of the main PHP charge-pump waveform (step 1) is calculated as 0.065593 picosecond x amperes. If you calculate the fundamental area of the fractional-N portion of the main PHP charge-pump waveform using the actual pulse widths above in place of the average pulse width calculated in step 1, the fractional-N main PHP areas is obtained as follows: FracArea-LWR = 132.557 ps – 0.500 mA = 0.066279 ( ps × amps) FracArea-UPR = 129.815 ps – 0.500 mA = 0.064691 (ps × amps) The actual areas under the fractional-N portion of the main PHP waveform require slight modification in the charge-pump current. The variation of CN required for area equalization is determined using a simple ratio form: CN Frac Area–AVG + LWR Frac CN Area–AVG + Frac Frac CN Area–UPR CN UPR Area–UPR AVG AVG + 0.065593 0.066279 128 + 126 + 0.065593 0.064691 128 + 130 Therefore, for this example, CN can vary from 126-130 over the VCO frequency range of 942.99 – 962.91 MHz for optimum fractional-N sideband suppression. Due to component and circuit tolerances, additional deviations in CN may be appropriate. auxiliary divider The input signal on AUXIN is amplified by a single-ended, ac-coupled input buffer/amplifier that has sufficient sensitivity (200 mVpp at 200 MHz) for direct connection to a typical VCO. The 12-bit (NA) auxiliary divider incorporates a divide by 1 (PA = 1) or divide by 4 (PA = 0) prescaler. The total division ratio can be expressed as: NTotal = 4 x NA where PA = 0 NTotal = NA, where PA = 1 and NA = 4 to 4095 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION reference divider The input signal on REFIN is amplified by a single-ended, ac-coupled input buffer/amplifier that has sufficient sensitivity (300 mVpp at 50 MHz) for direct connection to a typical TCXO. The 12-bit (NR) reference divider total division ratio can be expressed as: NTotal = NR, where NR = 4 to 4095 A four-section postscaler is connected to the output of the reference divider section. The main and auxiliary synthesizer sections can individually select a reference postscaler division of 1, 2, 4, or 8 by programming fields SM and SA, respectively (see Figure 24). MAIN SELECT SM = “00” SM = “01” SM = “10” Main Phase Detector SM = “11” Reference Input Divide by NR ÷2 ÷2 ÷2 AUXILIARY SELECT SA = “11” SA = “10” SA = “01” Auxiliary Phase Detector SA = “00” Figure 24. Reference Divider phase detectors The main and auxiliary synthesizer sections (see Figure 25) incorporate dual D-type flip-flop phase-frequency detectors (PFD). A PFD has gain with a phase error over a range of ±2π and exhibits an infinite pull-in range. Dead-band compensation about zero-phase error is provided by forcing the sourcing and sinking charge pumps to have a minimum on-time of 1/fRef when the loop is operating in a locked condition. The phase detectors can be programmed for polarity sense. Normally, external system VCOs have a positive slope control-voltage frequency characteristic. Some VCOs have a negative slope characteristic. The TRF2050 main and auxiliary phase detectors can be programmed for use with positive or negative slope VCOs using the MCP and ACP fields, respectively, in the B-Word (EPM mode). For positive slope VCOs: MCP = ACP = 0 For negative slope VCOs: MCP = ACP = 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION VDDA SET 1 Q D Reference Divider /NR REFIN Q CLR Charge Pump Output SET 1 Main or Auxiliary Reference Divider /N or /NR REFIN or AUXIN Q D Q CLR VSSA Figure 25. Main and Auxiliary Phase Detector Circuit charge-pump current plans The TRF2050 uses internal band-gap references and external resistors to develop biasing reference currents for the various charge pumps sections. Three terminals are designated for the external resistors: RN, RF, and RA. Internal, programmable coefficients CN, CL, and CK are also used. Table 7 shows how the external resistors are used to achieve desired charge-pump peak currents. Table 7. Charge Pump Current Plans PARAMETER Peak proportional, normal mode current PHP ǒ * PK NM Ǔ)ǒ + ǒ ) Peak proportional, speed-up mode current PHP * PK SM + ) 18.75 x CN 256 RN 0.75 Peak auxiliary current PHA PK + ǒ ) Ǔ 18.75 x CN x 2 CL 1 256 RN 0.75 Peak integral, speed-up mode current PHI †Peak compensation, normal mode current ) Ǔ 18.75 x CN 256 RN 0.75 ǒ *SM + RN18.75 ) 0.75 30 Comp + RF PK Ǔ ) Ǔ x CN x CK x 2 CL 1 256 PK 1.25 x 20 RA MODE CONDITION UNIT Normal RN in kΩ mA Speed-up RN in kΩ mA Speed-up RN in kΩ mA Normal RF in kΩ µA Normal RA in kΩ mA † The compensation charge-pump current is a pulse-amplitude modulated with the contents of the fractional accumulator. See the section on Main Divider – Fractional-N Sidebands and Compensation. The average charge-pump current for the PHP, PHI, and PHA terminals is defined by: I 30 AVG + qerror 2p x I . PK POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 PRINCIPLES OF OPERATION loop enable/disable The main and auxiliary loops can be enabled and disabled by the contents of the enable bits EM and EA, respectively. When disabled, all currents in the RF input stages are switched off; the bias currents for the respective charge-pump circuits are switched off as well. When both loops are disabled (EM = EA = 0), the reference input stage currents are switched off. The reference chain can be turned off because the serial interface operates independent of the reference input for the loading of serial words. Table 8. Loop Enable/Disable EM EA 0 0 ENABLED DISABLED 0 1 Auxiliary, Reference Main, 1 0 Main, Reference Auxiliary 1 1 Main, Auxiliary, Reference Main, Auxiliary, Reference speed-up mode When the main synthesizer frequency is changed, it may be desirable to increase the loop bandwidth for a short time in order to achieve a faster lock time. The proportional charge-pump current is increased and the integral charge-pump current is switched on for the duration of speed-up mode. The section, charge-pump current plans, illustrates how the charge-pump currents are a function of the external resistor RN and the programmable coefficients CN, CL, and CK. The duration of the speed-up mode is determined by the operational mode of the TRF2050 device: enhanced performance mode (EPM) or SA7025 emulation mode. In EPM mode, the speed-up mode duration is controlled as a function of the G field in the B-Word and the reference frequency divider period. Table 9. Speed-Up Mode G VALUE 0–14 15 DURATIONEPM [(G+1) × NR × SM × 16]/fREFIN < (NR × SM)/(fREFIN × 2); which is less than 1/2 a phase detector cycle When the TRF2050 is operated in SA7025 emulation mode, the speed-up mode duration is a function of the STROBE signal associated with the A-Word. When the STROBE signal followed by an A-Word write transaction goes active, the speed-up mode currents begin and persist until the STROBE signal is returned to an inactive state. lock detect The lock condition of the PLL is defined as a phase difference of less than a ±1 cycle on the reference input REFIN. The LOCK terminal can be polled to determine the synthesizer lock condition of either or both loops. The lock detect function is described by the Boolean expression: LOCK + ǒ LD Main ) EM Ǔ·ǒ LD Aux Ǔ ) EA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 test modes The LOCK terminal may be used for test operations by terminating pin 19 to ground. When test modes are enabled, the LOCK terminal is connected to internal nodes of the TRF2050. Test modes are enabled by writing ones to the two LSBs of the E-Word. Test modes are disabled by terminating pin 19 to VCC through a pull-up resistor of 10 kΩ. Table 10. Test Modes T1 T0 MODE 0 0 Buffered output of the fractional accumulator 0 1 Buffered output of the auxiliary divider 1 0 Buffered output of the main divider 1 1 Buffered output of the reference divider The test mode can be used to verify the division ratio of the reference divider, the auxiliary divider, and the main divider and prescaler. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER SLWS030D– JUNE 1996 – REVISED OCTOBER 1998 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,32 0,19 0,65 14 0,13 M 8 0,15 NOM 4,50 4,30 6,70 6,10 Gage Plane 0,25 1 7 0°– 8° 0,75 0,50 A Seating Plane 1,20 MAX 0,10 0,10 MIN PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / D 10/95 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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