SLWS084 – DECEMBER 2000 Complete L1-Band Global Postioning GQE PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 A B C D E F G H J PRODUCT PREVIEW System (GPS) RF Receiver 2.7-V to 3.3-V Operation Low Current Consumption, 49 mA Typical at 2.7 V Integrated Voltage-Controlled Oscillator (VCO) Tank Circuit Compatible With Cellular Phone Environment While Transmitter Is Active Programmable Sleep Mode for Extended Standby Time Integrated Low Noise Amplifier (LNA) and Image Reject Mixer Front-End With Typical Cascaded Noise Figure of 2.9 dB Integrated Phase-Locked Loop (PLL) 4-Bit Analog-To-Digital Converter (ADC) With Programmable Automatic Gain Control (AGC) for Improved GPS Receiver Sensitivity Operating Temperature Range: –40°C to 85°C Code Division Multiple Access/ TimeDivision Multiple Access (CDMA/TDMA/GSM) System ClockCompatible Synthesizer Image-Reject Architecture for Reduced Parts Count and Page Control Block (PCB) Real Estate Requirements 3-Wire Serial Interface and Single Blanking Mode Control Terminal Digital CMOS Compatible Inputs/Outputs User-Selected Internal/External Sampling Clock for ADC RF BiCMOS technology with ESD Protection to 2000 V HBM (non-RF Pins) Chip Scale Package (CSP) 5 mm x 5 mm description The TRF5001 device is a dual down-conversion receiver that is compatible with cellular terminals while the transmitter is active. The TRF5001 device includes an integrated low-noise amplifier and mixer, a fixed-frequency synthesizer to generate both first and second local oscillator frequencies, and a four-bit ADC for use in GPS applications requiring exceptional sensitivity, such as E-911. By using only the most significant bit (MSB), the TRF5001 device can be mated to more conventional baseband processors requiring only single bit resolution. The typical first intermediate frequency is 222.54 MHz with a final intermediate frequency into the ADC of 2.94 MHz. An external or internal sampling clock can be selected for custom use of the TRF5001 device, as long as the Nyquist sampling rate is satisfied. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI is a trademark of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated !# !" !$#" # !#% ! " " % # !#!"# # #! " #" ! " " '" "#!$#" !"!%" # !# # ! "#$ #" !$#" &#$# # POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 6 GND_PLLA 5 CP_OUT 4 GND_VCO 3 VAR_IN VCO_TKC2 VCC_VCO 2 VCO_TKC1 1 NC SLEEP GND_SUB GND_VCO DATE AND TRACKING INFORMATION 7 8 9 A VCC_PLLA VCC_LNA B VDD_PLLD GND_LNA1 C TCXO D PLL_LOCK LNA_IN GND_DIG GND_LNA2 GND_LNA3 E DSP_CLK PRODUCT PREVIEW GND_RFMIX1 RFMIX_OUT+ F RFMIX_OUT– G B0 B1 VCC_BUFFER B2 GND_BUFFER Figure 1. Pin Assignments (Top View) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B3 CLK DATA EN GND_ADC VDD_ADC GND_IF2 IF_IN– IF_IN+ GND_IF1 J GND_SUB VCC_RFMIX H VCC_IF GND_RFMIX2 SLWS084 – DECEMBER 2000 A1 A2 B3 A3 A4 VCC_LNA B1 GND_LNA1 C1 E1 GND_RFMIX1 F2 Charge Pump ÷2 LNA GND_PLLA CP_OUT VAR_IN VCO_TKC2 VCO B8 PFD Reference Divider A9 VCC_PLLA B9 VDD_PLLD C9 TCXO D9 PLL_LOCK E8 GND_DIG Main Divider U1 TRF5001 ÷6 F1 G1 1st Mixer (Image Reject) LPF ÷ 12 or 24 E9 IF2 Amplifier F9 4-Bit ADC 2nd Mixer Digital AGC POST OFFICE BOX 655303 J5 H6 J6 EN H4 GND_ADC J3 J4 B0 B1 B2 B3 F8 VDD_ADC H3 GND_IF2 J2 IF_IN– H2 DSP_CLK 4 Programming Interface IF_IN+ J1 GND_IF1 VCC_RFMIX H9 J9 IF1 Amplifier VCC_IF H1 GND_SUB GND_RFMIX2 G9 PRODUCT PREVIEW RFMIX_OUT– A8 D2 GND_LNA3 RFMIX_OUT+ A6 A7 • DALLAS, TEXAS 75265 J7 G8 VCC_BUFFER H8 GND_BUFFER J8 CLK GND_LNA2 A5 DATA LNA_IN D1 VCC_VCO VCO_TKC1 NC GND_VCO SLEEP GND_SUB functional block diagram 3 DATE AND TRACKING INFORMATION Terminal Functions TERMINAL PRODUCT PREVIEW NAME I/O DESCRIPTION B0 F9 O ADC bit 0 (LSB) B1 G9 O ADC bit 1 B2 H9 O ADC bit 2 B3 J9 O ADC bit 3 (MSB) CLK J8 I Clock signal from 3-wire interface CP_OUT A8 O Charge pump output from PLL phase frequency detector (PFD) DATA J7 I Data signal from 3-wire interface DSP_CLK E9 I/O EN J6 I GND_ADC H6 ADC ground GND_BUFFER H8 ADC buffer ground GND_DIG E8 Digital ground GND_IF1 H3 IF ground GND_IF2 H4 IF ground GND_LNA1 C1 GND_LNA2 D2 GND_LNA3 E1 GND_PLLA B8 GND_RFMIX1 F2 GND_RFMIX2 H1 GND_SUB A2, G3, H2 GND_VCO B7, B3 Clock to/from baseband I = ADC sampling clock input 0 = internally generated sampling clock to ADC Enable signal from 3-wire interface RF LNA g ground ou d Charge pump ground RF mixer ground Substrate ground VCO ground IF_IN+ J3 I IF amplifier input IF_IN– J4 I IF amplifier input LNA_IN D1 I RF LNA input NC A3 PLL_LOCK D9 O PLL lock detected RFMIX_OUT– G1 O RF mixer output RFMIX_OUT+ F1 O RF mixer output SLEEP A1 I Sleep mode (RX blanking) enable TCXO C9 I Reference oscillator input VAR_IN No connection A7 I/O F8, G8 I ADC buffer power supply J2 I IF power supply VCC_LNA VCC_PLLA B1 I RF LNA power supply A9 I Charge pump power supply VCC_RFMIX VCC_VCO J1 I RF mixer power supply A5 I VCO power supply VCO_TKC1 VCO_TKC2 A4 I/O VCO tank A6 I/O VCO tank VDD_ADC VDD_PLLD J5 I ADC power supply B9 I PLL power supply VCC_BUFFER VCC_IF 4 NO. VCO varactor input POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLWS084 – DECEMBER 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range: VCC_IF, VCC_LNA, VCC_PLLA, VCC_RFMIX, VCC_VCO, VDD_ADC, VDD_PLLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3.6 V Input voltage to any other terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD V Power dissipation, TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD mW Junction temperature, TJmax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Operating ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ESD integrity (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV HBM † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Sensitive RF pins are not protected against voltage stress higher than 300 V HBM. recommended operating conditions (see Note 2) NOM MAX UNIT Analog supply voltage, VCC_IF, VCC_LNA, VCC_PLLA, VCC_RFMIX, VCC_VCO 2.7 3 3.3 V Digital supply voltage, VDD_ADC, VDD_PLLD, VCC_BUFFER 2.7 3 3.3 V Input logic 1 level, VIH 0.7 VDD_PLLD Input logic 0 level, VIL VDD_PLLD 0.3 VDD_PLLD 0 Output logic 1 level, VOH VDD_PLLD–0.4 0 V V Output logic 0 level, VOL Operating free-air temperature, TA V 25 0.4 V 65 °C NOTE 2: The DATA, CLOCK, and EN lines provided by the baseband DSP or microcontroller to control the serial interface has a logic 1 level less than or equal to 3.6 V. dc electrical characteristics (Typ: VDD_X = 2.7 V, TA = 25°C, Max and Min: 2.7 V < VDD_X < 3.3 V, TA = –40°C to 85°C unless otherwise noted) supply current TYP MAX Operating current PARAMETER VDD_X = 2.7 V TEST CONDITIONS 49 61 Sleep (blanking) mode current Programmed with SLEEP terminal 16 Deep sleep mode Programmed through Serial Peripheral Interface (SPI) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN 5 UNIT mA mA 10 µA 5 PRODUCT PREVIEW MIN DATE AND TRACKING INFORMATION receiver LNA/mixer cascaded performance PARAMETER TEST CONDITIONS MIN Frequency SSB noise figure Room temperature Conversion gain 28 LNA/mixer input 1-dB compression point LNA/mixer input 3rd-order intercept point PRODUCT PREVIEW TYP MAX 1575.42 MHz 2.9 3.5 32 36 –36 Fixed IF frequency at 222.54 MHz Input return loss Single ended with external matching network to 50 Ω IF output impedance Differential-open collector IF output return loss External match to single-ended output 10 Image rejection Image at 1130.34 MHz 20 All other harmonics at IF output Measured at IF port LO leakage at RF port Measured at RF input port with a Hi-Z probe Maximum RF level Maximum RF level before destruction dB dB dBm –26 IF output frequency range UNIT dBm 222.54 MHz 10 dB Ω 200 dB 25 dB –50 dBm –40 TBD dBm dBm frequency synthesizer PARAMETER TEST CONDITIONS MIN Frequency TYP MAX 1352.88 UNIT MHz Reference frequency 10 16.8 40 MHz Comparison frequency 20 40 240 kHz Main frequency divider, N 15 bits Reference frequency divider, M 12 bits 32768 4096 Reference sensitivity 0.2 2 Charge pump current 1 Current matching Typical lock time† 5 PLL spur suppression† RMS phase error† Phase noise† Vpp mA 10% Compare frequency = 40 kHz Loop bandwidth = 4 kHz Compare frequency = 40 kHz Frequency offset = 1 kHz 68 Loop bandwidth = 4 kHz Compare frequency = 40 kHz Frequency offset = 10 kHz 70 Loop bandwidth = 4 kHz Compare frequency = 40 kHz Frequency offset = 100 kHz 98 µs 50 dBc 10 degrees dBc/Hz † Minimum performance requirements for reliable GPS operation. GPS performance level established by PLL loop filter and VCO tank components selected by the designer. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLWS084 – DECEMBER 2000 IF strip TEST CONDITIONS Frequency range Noise figure At maximum gain setting Input 1-dB compression point Gain = 37 Input third-order intercept point Input 1-dB compression point MIN TYP MAX UNIT 100 222.54 250 MHz 8 12 Gain SPI = 0 –53 Gain = 37 Gain SPI = 0 –43 Gain = 73 Gain SPI = 12 –84 Input third-order intercept point Gain = 73 Gain SPI = 12 –74 Input 1-dB compression point Gain = 82 Gain SPI = 15 –93 Input third-order intercept point Gain = 82 Gain SPI = 15 –83 IF strip gain range Typical AGC range In 3-dB steps 45 Gain error (linearity) In any 20-dB window ±1 dB dBVrms dBVrms dBVrms dBVrms dBVrms dBVrms 37 73 3-dB corner frequency 82 dB dB ±1.5 dB 4.0 MHz 200 Ω For a one gain step of 3 dB 50 µs/step AGC decay time For a one gain step of 3 dB 50 µs/step Interface 3-wire interface Input impedance Differential Input return loss With external match AGC attack time 10 dB PRODUCT PREVIEW PARAMETER analog-to-digital converter (see Notes 4 and 5) PARAMETER TEST CONDITIONS MIN Resolution (number of bits) MAX 4 Sample rate Input impedance TYP 6 Differential, fin = 2.87 MHz Input bandwidth 18.79 UNIT bits 20 1 MHz kΩ 6 MHz Input dc offset voltage (offset error) –1/4 1/4 LSB Input differential nonlinearity (DNL error) –1/4 1/4 LSB 1/4 LSB Input integral nonlinearity (INL error) –1/4 RMS signal-to-noise Sampling rate = 18.79 MHz, input tone = 2.94 MHz 23.6 dB Signal-to-noise plus distortion (SINAD) Sampling rate = 18.79 MHz, input tone = 2.94 MHz 22.8 dB Effective number of bits (ENOB) Sampling rate = 18.79 MHz, input tone = 2.87 MHz 3.57 bits Total harmonic distortion (THD) Sampling rate = 18.79 MHz, input tone = 2.87 MHz –31 dBc Capacitance output load drive capability Capacitance 5 Data output latch 1 10 pF Clock cycle NOTES: 3. No missing codes. 4. ADC data words are sequential (i.e., Vin = Vin_ADC_min = 0000, . . . , Vin = Vin_ADC_max = 1111) 5. Data format of the 4-bit ADC is unsigned binary. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 DATE AND TRACKING INFORMATION DSPCLK Internal or External Analog Input N-1 ADC Output tDSPCLK = 1/Fsample tD = Sample point N-2 tD = ∼10 nsec tHOLD tSETUP tSETUP = 0.5* tDSPCLK - tD tDSPCLK tHOLD = 0.5* tDSPCLK Figure 2. ADC Timing Diagram PRODUCT PREVIEW power-up/-down time PARAMETER TEST CONDITIONS Power-up time (excludes PLL/VCO components) MIN TYP Output power within 10% of steady-state values Power-down time MAX UNIT 100 µs 100 µs MAX UNIT 20 MHz timing requirements, serial data interface (see Figure 3) PARAMETER MIN NOM f(CLOCK) t(HIGH) Clock frequency tf tr Clock fall time t(LOW) t(START) Clock low time 20 Delay to rising clock edge 10 t(END) t(SUDA) Delay from falling edge of clock to rising edge of strobe 20 ns DATA setup time 20 ns t(HDDA) t(STHIGH) DATA hold time 20 ns Minimum EN pulse hold time 40 ns Clock duty cycle 40 8 Clock hold time 20 ns Clock rise time POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8 ns 8 ns ns 20 50 ns 60 % SLWS084 – DECEMBER 2000 Data Valid DATA Data Change MSB t(SUDA) LSB t(END) t(THDA) t(HIGH) MSB –VH –VL Start of Next Word –VH CLOCK –VL tf t(LOW) tr t(STHIGH) –VH EN Clock Disabled Clock Enabled Shift in Data Store Data Strobe Enabled –VL t(START) PRODUCT PREVIEW NOTE: Most significant bit clocked in first. Figure 3. Serial Data Interface Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 DATE AND TRACKING INFORMATION PRINCIPLES OF OPERATION serial port interface The TRF5001 device registers are controlled via a synchronous serial data port. Each word contains 24 bits that are clocked into temporary holding registers with the MSB clocked in first. The total number of words hasn’t been determined. Figure 4 shows what they might look like. Word 0 and 1 are for the users while Words 2 through 7 are for internal use The operation registers are loaded with the new data residing in the temporary registers with the STROBE line. Each word can be written to the device independently. The 6 MSBs of each word contain the address of the word while the balance of the 24 bits contain the data fields. Table 1 through Table 7 describe each programming word definition bit-by-bit. 23 22 Word Desig. 21 20 19 18 17 16 15 14 13 12 11 10 Address 9 8 7 6 5 4 3 2 1 0 Data Word0 0 0 0 0 0 0 Word1 0 0 0 0 0 1 CF RD DS BS SP O AG H CS RS x x x x x S S S PRODUCT PREVIEW Next words are reserved for internal use Word2 0 0 0 0 1 0 S S S S S S S Word3 0 0 0 0 1 1 x x x x x x x Word4 0 0 0 1 0 0 S S S S S S S S x x x x x x x x MD Word5 0 0 0 1 0 1 Word6 0 0 0 1 1 0 CV Word7 0 0 0 1 1 1 OB AB CT PL FO MO AO EV LT EL EM EV ES EA EI EF EB EA LR AS LE LD x x x x x x x x x x x x x x x x x x x x PS LS x x LDW Figure 4. Serial Word Format For bit 23, 0 enables the write mode, and 1 enables the read mode. In the read mode, register data are available at the PLL_LOCK terminal. Word2 is a spare register. Word3 is reserved for future use. Address 101000 is reserved to read LPF DACWORD, AGC gain setting, and chip ID at the PLL_LOCK terminal. The first bit is MSB LPF DACWORD; the last bit is LSB chip ID. 23 22 Word Desig. 21 20 19 18 17 16 15 14 13 12 11 10 Address 9 8 7 6 5 4 3 2 1 0 x x x x x Data 1 0 Word0 0 0 0 0 0 0 Word1 0 0 0 0 0 1 000110100100 (=420) Word2 0 0 0 0 1 0 1 0 0 0 0 0 0 0 Word3 0 0 0 0 1 1 x x x x x x x x Word4 0 0 0 1 0 0 Word5 0 0 0 1 0 1 Word6 0 0 0 1 1 0 Word7 0 0 0 1 1 1 1100 0011 0 0000 0 1 01 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x 1 0 x x x x x x x 0 0 x x x x x x x 1 1 x x Next words are reserved for internal use 001011000000101 (=5637) 1 1 1 1 1 1 1 1 110010000 (=400) 0 0 0 1 0 0 0 0 Figure 5. Default Values 10 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 10000 SLWS084 – DECEMBER 2000 PRINCIPLES OF OPERATION Table 1. Serial Word 0 Format DATA FIELD WORD DS 0 DEEPSLEEP 1 Deep sleep: 1 = enabled 0 = disabled BS 0 ENABLANK 1 Enable blanking sleep mode: 1 = enabled 0 = disabled RD 0 REFDIVNUM 12 Reference frequency division ratio; typical value is 420 (TCXO frequency is 16.8 MHz). 4 Comparison frequency select: bits CF (kHz) Main Divider 0000 20 11274 0001 30 7516 0010 40 5637 0011 60 3758 0101 120 1879 1000 20 no change 1001 30 no change 1010 40 no change 1011 60 no change 1101 120 no change 1111 240 no change 0 COMPFREQ BITS DESCRIPTION/CONDITIONS Division ratio for clock LPF tuning loop 2 3 4 (default) 6 12 2 3 4 6 12 24 PRODUCT PREVIEW CF PARAMETER Table 2. Serial Word 1 Format DATA FIELD WORD PARAMETER BITS DESCRIPTION/CONDITIONS SP 1 SETP 4 This 4-bit word is used as a reference by the AGC control loop. SETP is used for AGC fine gain tuning. Initial value is 3 (0011). This value assures that the AGC control loop sets the rms value at the ADC input equal to 1/4 of the ADC range. Increasing the value (or decreasing) by 1 or 2 steps results in an equivalent number of steps increasing (or decreasing) the AGC gain setting. AG 1 GAINSPI 4 This 4-bit word sets the AGC gain (0–15). Each step increases amplifier gain by 3 dB. O 1 OVERRIDE 1 When this bit is set to 1, AGC gain is overridden using GAINSPI word. When this bit is reset to 0, AGC gain is set by the control loop. H 1 HOLD 1 Hold AGC gain setting: 1 = enabled 0 = disabled CS 1 ADREFSW 1 ADC clock select: 1 = internal 0 = external 2 Select the division ratio (12 or 24) to generate the internal ADC clock from the second LO: 00 = ADC_clk equals Ref_Freq (only for testing) 01 = divide by 12 10 = divide by 24 11 = no ADC clock RS 1 REFDIVSEL POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 DATE AND TRACKING INFORMATION PRINCIPLES OF OPERATION Table 3. Serial Word 2 Format (Spare Register) BIT POSITION WORD 17–14 2 13 9 PARAMETER BITS DESCRIPTION/CONDITIONS SWCAPSET 1 4-bit word, used in VCO version 3, to control 4 switch cap. Default value = 1000. 2 DIS_VARAC_BUF 1 In VCO versions 2 and 3, this bit disables the voltage buffer at VARACIN. 1 = buffer is enabled (default) 0 = buffer is disabled 2 MIX_BIAS_SEL 1 This bit is used to select the bias of the RF mixer. Default is 0. Table 4. Serial Word 4 Format DATA FIELD WORD MD 4 PARAMETER MAINDEVNUM BITS 15 DESCRIPTION/CONDITIONS Main divider ratio. Initial value is 5637. PRODUCT PREVIEW Table 5. Serial Word 5 Format DATA FIELD WORD EL 5 LNAENA 1 1 = enable LNA 0 = disable LNA EM 5 MIX1ENA 1 1 = enable RF mixer 0 = disable RF mixer EV 5 VCOENA 1 1 = enable VCO 0 = disable VCO ES 5 ENASYN 1 1 = enable synthesizer 0 = disable synthesizer EA 5 ENAAGCAMP 1 1 = enable AGC amplifier 0 = disable AGC amplifier EI 5 MIX2ENA 1 1 = enable IF mixer 0 = disable IF mixer EF 5 FILTENA 1 1 = enable LFP 0 = disable LFP EB 5 IFAMPENA 1 1 = enable IF amplifier 0 = disable IF amplifier EA 5 ADCENA 1 1 = enable ADC 0 = disable ADC LR 5 LPFRESET 1 The 0-to-1 transition restarts LPF tuning AS 5 AGCSEL 1 1 = fast AGC control loop 0 = slow fast AGC control loop (default) PARAMETER BITS DESCRIPTION/CONDITIONS Table 6. Serial Word 6 Format DATA FIELD WORD CV 6 COMPAREVAL 9 9-bit word used as a comparing frequency during LPF tuning. Initial value = 400. LE 6 LEVELTEST_EN 1 1 = enable digital output test 0 = disable digital output test LD 6 LEVEL_DATA 1 Sets level for digital output test. 12 PARAMETER BITS DESCRIPTION/CONDITIONS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLWS084 – DECEMBER 2000 PRINCIPLES OF OPERATION Table 7. Serial Word 7 Format DATA FIELD WORD OB 7 OUTBUFEN 1 1 = enable prescaler output buffer 0 = disable prescaler output buffer AB 7 ENAADBYP 1 1 = enable bypass ADC 0 = disable bypass ADC CT 7 CLKTESTENA 1 1 = enable internal ADC clock test 0 = disable internal ADC clock test PL 7 ENA_LOCK 1 1 = enable PLLLOCK switch 0 = disable PLLLOCK switch FO 7 ENTFILTOUT 1 1 = enable LPF output buffer 0 = disable LPF output buffer MO 7 ENTMIX2OUT 1 1 = enable IFMIXER output buffer 0 = disable IFMIXER output buffer AO 7 ENTVGAOUT 1 1 = enable AGC output buffer 0 = disable AGC output buffer EV 7 EXTVCO 1 1 = enable external VCO input 0 = disable external VCO input LT 7 ENALPFTUNE 1 1 = enable LPF tuning circuit 0 = disable LPF tuning circuit LDW 7 DACWORD 5 5-bit LPF tuning DAC word. The LPF tuning DAC word is used when ENALPFTUNE is low. PS 7 PREAMP_PS 1 1 = normal mode for preamp ADC (default) 0 = low current mode for preamp ADC LS 7 LATCH_PS 1 1 = normal mode for latch ADC (default) 0 = low current mode for latch ADC BITS DESCRIPTION/CONDITIONS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PRODUCT PREVIEW PARAMETER DATE AND TRACKING INFORMATION PRINCIPLES OF OPERATION operating modes Two operating modes exist in the TRF5001 device. Normal mode (GPS receiver enabled) powers up the entire receive chain to allow immediate processing of down-converted GPS signals. Sleep mode (also known as blanking mode) is programmable via the 3-wire interface to allow maximum flexibility. Sleep mode is optionally enabled during transmit bursts in Time-Division Multiple Access (TDMA) slotted systems to mitigate potential handset-to-GPS receiver jamming. Sleep mode also reduces power consumption in GPS applications where front-end preselect filtering has been reduced but the synthesizer must remain locked (due to its relatively longer lock time). At power up of the device, all internal devices are disabled with outputs set to zero until the device is programmed via the 3-wire interface. Table 8. Operating Mode SLEEP OPERATING MODE Sleep (blanking) mode (register data preserved) 1 Normal/GPS receiver enabled (register data preserved) PRODUCT PREVIEW 0 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLWS084 – DECEMBER 2000 PRINCIPLES OF OPERATION V supply 222.54 MHz SAW Filter 3-dB BW > 1.7 MHz RF Vcc Match Mixer Vcc Match IF Vcc 2.94 MHz Match VCO V supply Vcc 1352.88 MHz 2705.76 MHz 225.48 MHz ADC Vcc AGC ÷2 4 ÷6 PRODUCT PREVIEW RF Preselector Fc=1575.42 MHz ÷ 12 or 24 Main Divider Loop Filter Charge Pump V supply Phase Det 4-bit ADC 18.79 MHz or 9.395 MHz Reference Divider Programming Interface Cellular Terminal Voltage Regulator DPLL Vcc TCXO APLL Vcc dig Vcc Vsupply Vsupply Vsupply External Sampling Clock POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 DATE AND TRACKING INFORMATION APPLICATION INFORMATION automatic gain control The TRF5001 device uses AGC to ensure that sampled data uses the maximum dynamic range of the ADC to ensure optimum sensitivity. Since the composite signal received at the ADC input is dominated by thermal noise, the probability distribution function (PDF) of sampled voltages follows a nearly gaussian distribution. The AGC attempts to force the sampled root-mean-square (RMS) voltage at the input to the ADC to be equal to one quarter (1/4) of the total input ADC range, 0.5 V, 0.125 V, by varying the AGC gain. At power up, this loop must stabilize within 1 ms, although relatively slow short term AGC drift with temperature can occur and is to be expected. In the event of a large, undesired input signal, the AGC loop can recover automatically within 500 µs. In the event that a large jammer appears at the input, the AGC stops in 3-dB increments. PRODUCT PREVIEW If baseband processing determines that more or less gain is desired for refinement of subsequent data samples, the serial interface can be used to increment or decrement the targeted RMS voltage to the ADC input. Using the SETP control bits (word 1), values from 2 to 8, it is possible to increase or decrease the RMS voltage to the ADC input by 3 dB per step. For values from 0 to 2 there is a variation of 6 dB per step, while for values greater than 8 there is a variation of about 6 dB per step. Use of values from 2 to 8 is recommended. Values over 8 may cause the ADC to saturate. This function allows the baseband DSP or microcontroller to adjust the AGC gain as part of adaptive processing for optimum receiver sensitivity. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLWS084 – DECEMBER 2000 APPLICATION INFORMATION application characteristics Table 9 lists performance characteristics of the IF (SAW) filter recommended for use in a GPS receiver integrated into a mobile handset. Table 9. IF (SAW) Filter Performance Characteristics Recommendations TEST CONDITIONS MIN TYP MAX 222.54 1-dB Bandwidth fc±750 3-dB Bandwidth fc±850 Insertion loss kHz 0.1 MHz to fc – 2.65 MHz 35 40 fc – 2.65 MHz to fc – 1.80 MHz 20 25 fc + 1.65 MHz to fc + 2.65 MHz 20 25 fc + 2.65 MHz to 281 MHz 35 40 281 MHz to 600 MHz 45 50 fc ± 350 kHz Group delay deviation MHz kHz 8.5 Ultimate out-of-band out of band rejection UNIT 11 dB dB 300 nsp-p Table 10 lists performance characteristics of the RF preselector filter recommended for use in a GPS receiver integrated into a mobile handset. Table 10. RF Preselector Filter Performance Characteristics PARAMETER TEST CONDITIONS MIN Pass-band insertion loss TYP MAX 1.8 3.15 Pass-band lower 3-dB frequency 1574.42 Pass-band upper 3-dB frequency 1576.42 Pass-band 3-dB bandwidth MHz 1 800 MHz to 1400 MHz 50 55 1400 MHz to 1500 MHz 20 25 1650 MHz to 1710 MHz 20 25 1710 MHz to 1820 MHz 40 45 1820 MHz to 2000 MHz 45 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dB MHz MHz 2 Pass-band ripple Rejection ejec o ((referenced e e e ced to o the e pass ass ba band) d) UNIT dB dB d 17 PRODUCT PREVIEW PARAMETER Center frequency DATE AND TRACKING INFORMATION MECHANICAL DATA GQE (S-PLGA-N80) PLASTIC LAND GRID ARRAY 5,20 SQ 4,80 4,00 TYP 0,50 J 0,50 H G F E D C B PRODUCT PREVIEW A 1 0,93 0,87 2 3 4 5 6 7 8 9 1,00 MAX Seating Plane 0,33 0,23 ∅ 0,05 M 0,08 0,08 MAX 4200461/A 10/99 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar Junior LGA configuration MicroStar Junior LGA is a trademark of Texas Instruments Incorporated. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated