UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 www.ti.com SLUS492H – JUNE 2001 – REVISED MAY 2013 Dual 4-A Peak High-Speed Low-Side Power-MOSFET Drivers Check for Samples: UCC27323, UCC27324, UCC27325, UCC37323, UCC37324, UCC37325 FEATURES APPLICATIONS • • • • • • • 1 2 • • • • • • • • • • Industry-Standard Pin-Out High Current-Drive Capability of ±4 A at the Miller Plateau Region Efficient Constant-Current Sourcing Even at Low Supply Voltages TTL/CMOS Compatible Inputs Independent of Supply Voltage 20-ns Typical Rise and 15-ns Typical Fall Times with 1.8-nF Load Typical Propagation-Delay Times of 25 ns with Input Falling and 35 ns with Input Rising 4.5-V to 15-V Supply Voltage Supply Current of 0.3 mA Dual Outputs are Paralleled for Higher Drive Current Available in Thermally Enhanced MSOP PowerPAD™ Package with 4.7°C/W θJC Rated From –40°C to +125°C TrueDrive™ Output Architecture Using Bipolar and CMOS Transistors in Parallel Switch-Mode Power Supplies DC/DC Converters Motor Controllers Line Drivers Class D Switching Amplifiers DESCRIPTION The UCC37323/4/5 family of high-speed dualMOSFET drivers deliver large peak currents into capacitive loads. Three standard logic options are offered — dual-inverting, dual-noninverting, and oneinverting and one-noninverting driver. The thermally enhanced 8-pin PowerPAD MSOP package (DGN) drastically lowers the thermal resistance to improve long-term reliability. UCC3732x is also offered in the standard SOIC-8 (D) or PDIP-8 (P) packages. Using a design that inherently minimizes shootthrough current, these drivers deliver 4-A of current where it is needed most at the Miller plateau region during the MOSFET switching transition. A unique BiPolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages. BLOCK DIAGRAM INVERTING N/C 1 INA 2 GND 3 NON-INVERTING INVERTING INB 4 NON-INVERTING 8 N/C 7 OUTA 6 VDD 5 OUTB 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD, TrueDrive are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2013, Texas Instruments Incorporated UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 SLUS492H – JUNE 2001 – REVISED MAY 2013 www.ti.com D, DGN, OR P PACKAGE (TOP VIEW) ORDERING INFORMATION (1) OUTPUT CONFIGURATION Dual inverting Dual nonInverting One inverting, one noninverting (1) (2) TEMPERATURE RANGE TA = TJ PACKAGED DEVICES SOIC-8 (D) MSOP-8 PowerPAD (DGN) (2) PDIP-8 (P) –40°C to +125°C UCC27323D UCC27323DGN UCC27323P 0°C to +70°C UCC37323D UCC37323DGN UCC37323P –40°C to +125°C UCC27324D UCC27324DGN UCC27324P 0°C to +70°C UCC37324D UCC37324DGN UCC37324P –40°C to +125°C UCC27325D UCC27325DGN UCC27325P 0°C to +70°C UCC37325D UCC37325DGN UCC37325P D (SOIC-8) and DGN (PowerPAD-MSOP) packages are available taped and reeled. Add R suffix to device type (for example UCC27323DR, UCC27324DGNR) to order quantities of 2,500 devices per reel for D or 1,000 devices per reel for DGN package. The PowerPAD is not directly connected to any leads of the package. However, the PowerPAD is electrically and thermally connected to the substrate which is the ground of the device. POWER DISSIPATION RATINGS (1) (2) (3) PACKAGE SUFFIX θJC (°C/W) θJA (°C/W) Power Rating (mW) TA = 70°C (1) Derating Factor Above 70°C (mW/°C) (1) SOIC-8 D 42 84 to 160 (2) 344 to 655 (3) 6.25 to 11.9 (3) PDIP-8 P 49 110 500 9 MSOP PowerPAD-8 (2) DGN 4.7 50 to 59 (2) 1370 17.1 125°C operating junction temperature is used for power rating calculations. The PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. The range of values indicates the effect of pc-board. These values are intended to give the system designer an indication of the best and worst case conditions. In general, the system designer should attempt to use larger traces on the pc-board where possible in order to spread the heat away form the device more effectively. For information on the PowerPAD package, refer to Technical Brief, PowerPad Thermally Enhanced Package, Texas Instrument's Literature Number SLMA002, and Application Brief, PowerPad Made Easy, Texas Instruments Literature Number SLMA004. Table 1. INPUT/OUTPUT TABLE INPUTS (VIN_L, VIN_H) 2 UCC37323 UCC37324 UCC37325 INA INB OUTA OUTB OUTA OUTB OUTA L L H H L L H L L H H L L H H H H L L H H L L L H H L L H H L H Submit Documentation Feedback OUTB Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325 UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 www.ti.com SLUS492H – JUNE 2001 – REVISED MAY 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) Analog input voltage (INA, INB) MIN MAX –0.3 to VDD + 0.3 V not to exceed 16 Output body diode DC current (OUTA, OUTB) IOUT_DC Output current (OUTA, OUTB) IOUT_PULSE UNIT V 0.2 DC 0.2 Pulsed (0.5 µs) 4.5 A D Power dissipation at TA = 25°C D package 1.14 DGN package 2.12 P package 780 mW 16 V V Output voltage (OUTA, OUTB) VDD Supply voltage –0.3 16 TJ Junction operating temperature –55 150 Tstg Storage temperature –65 150 Lead temperature (soldering, 10 sec.) (1) (2) W °C 300 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. ELECTRICAL CHARACTERISTICS VDD = 4.5 to 15 V, TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT (INA, INB) VIN_H Logic 1 input threshold VIN_L Logic 0 input threshold Input current 2 1 0 V ← VIN ← VDD –10 10 V µA OUTPUT (OUTA, OUTB) Output current VDD = 14 V (1) VOH High-level output voltage VOH = VDD – VOUT, IOUT = –10 mA VOL Low-level output level IOUT = 10 mA Output resistance high TA = 25°C, IOUT = –10 mA, VDD = 14 V (2) TA = full range, IOUT = –10 mA, VDD = 14 V Output resistance low Latch-up protection (1) (2) 4 25 (2) 300 450 22 45 30 35 2.2 2.5 18 TA = 25°C, IOUT = 10 mA, VDD = 14 V (2) 1.9 TA = full range, IOUT = 10 mA, VDD = 14 V (2) 1.2 V 42 mV Ω 4 500 mA The pullup and pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET transistors. The pullup and pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325 3 UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 SLUS492H – JUNE 2001 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = 4.5 to 15 V, TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX INA = 0 V, INB = 0 V 300 450 INA = 0 V, INB = HIGH 300 450 INA = HIGH, INB = 0 V 300 450 INA = HIGH, INB = HIGH 300 450 UNIT OVERALL UCCx7323 INA = 0 V, INB = 0 V IDD Static Operating Current UCCx7324 UCCx7325 2 50 INA = 0 V, INB = HIGH 300 450 INA = HIGH, INB = 0 V 300 450 INA = HIGH, INB = HIGH 600 750 INA = 0 V, INB = 0 V 150 300 INA = 0 V, INB = HIGH 450 600 INA = HIGH, INB = 0 V 150 300 INA = HIGH, INB = HIGH 450 600 µA SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) TYP MAX TR Rise time (OUTA, OUTB) PARAMETER CLOAD = 1.8 nF, see Figure 1 TEST CONDITIONS MIN 20 40 TF Fall time (OUTA, OUTB) CLOAD = 1.8 nF, see Figure 1 15 40 TD1 Delay, IN rising (IN to OUT) CLOAD = 1.8 nF, see Figure 1 25 40 TD2 Delay, IN falling (IN to OUT) CLOAD = 1.8 nF, see Figure 1 35 35 UNIT ns Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver 4 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325 UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 www.ti.com SLUS492H – JUNE 2001 – REVISED MAY 2013 TERMINAL FUNCTIONS TERMINAL I/O FUNCTION NAME NO. GND 3 INA 2 I Input A: Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input must be tied to either VDD or GND; it must not be left floating. INB 4 I Input B: Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input must be tied to either VDD or GND; it must not be left floating. N/C 1 No connection: Must be grounded. N/C 8 No connection: Must be grounded. OUTA 7 O Driver output A: The output stage is capable of providing 4-A drive current to the gate of a power MOSFET. OUTB 5 O Driver output B: The output stage is capable of providing 4-A drive current to the gate of a power MOSFET. VDD 6 I Supply: Supply voltage and the power input connection for this device. Common ground: This ground should be connected very closely to the source of the power MOSFET which the driver is driving. Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325 5 UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 SLUS492H – JUNE 2001 – REVISED MAY 2013 www.ti.com APPLICATION INFORMATION General Information High-frequency power supplies often require high-speed, high-current drivers such as the UCC37323/4/5 family. A leading application is the needed to provide a high-power buffer stage between the PWM output of the control IC and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is used to drive the power-device gates through a drive transformer. Synchronous rectification supplies are also needed to simultaneously drive multiple devices which presents an extremely large load to the control circuitry. Driver ICs are used when having the primary PWM regulator IC directly drive the switching devices for one or more reasons is not feasible. The PWMIC does not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire to minimize the effect of high-frequency switching noise by placing the high current driver physically close to the load. Also, newer ICs that target the highest operating frequencies do not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the UCC37323/4/5. Finally, the control IC is under thermal stress due to power dissipation, and an external driver helps by moving the heat from the controller to an external package. Input Stage The input thresholds have a 3.3-V logic sensitivity over the full range of VDD voltage; yet it is equally compatible with 0 V to VDD signals. The inputs of UCC37323/4/5 family of drivers are designed to withstand 500-mA reverse current without either damage to the IC for logic upset. The input stage of each driver must be driven by a signal with a short rise or fall time. This condition is satisfied in typical power-supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The input stages to the drivers function as a digital gate, and are not intended for applications where a slow-changing input voltage is used to generate a switching output when the logic threshold of the input section is reached. While this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency. Users must not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal at the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power device, then add an external resistance between the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor also helps remove power dissipation from the IC package, as discussed in the section on Thermal Considerations (see THERMAL INFORMATION). Output Stage Inverting outputs of the UCC37323 and OUTA of the UCC37325 are intended to drive external P-channel MOSFETs. Noninverting outputs of the UCC37324 and OUTB of the UCC37325 are intended to drive external Nchannel MOSFETs. Each output stage is capable of supplying ±4-A peak current pulses and swings to both VDD and GND. The pullup and pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the internal MOSFET. In many cases, external-schottky-clamp diodes are not required. The UCC37323 family delivers 4-A of gate drive where it is most needed during the MOSFET switching transition — at the Miller plateau region — providing improved efficiency gains. A unique BiPolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing at low supply voltages. 6 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325 UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 www.ti.com SLUS492H – JUNE 2001 – REVISED MAY 2013 Source/Sink Capabilities During Miller Plateau Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCC37323/4/5 drivers have been optimized to provide maximum drive to a power MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging and discharging of the draingate capacitance with current supplied or removed by the driver IC. (see References) Two circuits are used to test the current capabilities of the UCC37323 driver. In each case, external circuitry is added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient period where the current peaked up and then settled down to a steady-state value. The noted current measurements are made at a time of 200 ns after the input pulse is applied, after the initial transient. The first circuit in Figure 2 is used to verify the current sink capability when the output of the driver is clamped around 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCC37323 is found to sink 4.5 A at VDD = 15 V and 4.28 A at VDD = 12 V. VDD 1 2 3 Signal generator producing 250 ns wide pulse 4 UCC27323 ENBA ENBB INA GND INB 8 DSCHOTTKY OUTA 10 7 VDD OUTB C2 1 µF 6 5 C3 100 µF + DADJ 5.5 V VSNS 1 µF CER 100 µF AL EL RSNS 0.1 Figure 2. The circuit shown in Figure 3 is used to test the current source capability with the output clamped to around 5 V with a string of Zener diodes. The UCC37323 is found to source 4.8 A at VDD = 15 V and 3.7 A at VDD = 12 V. Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325 7 UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 SLUS492H – JUNE 2001 – REVISED MAY 2013 www.ti.com VDD 1 2 3 Signal Generator 4 UCC27323 ENBA ENBB INA GND INB 8 DSCHOTTKY OUTA 10 Ω 7 VDD OUTB C2 1 μF 6 5 C3 100 μF 4.5 V VSNS 250 ns 1 μF CER 100 μF AL EL RSNS 0.1 Ω Figure 3. Note that the current sink capability is slightly stronger than the current source capability at lower VDD. This stronger capability is due to the differences in the structure of the bipolar-MOSFET power output section, where the current source is a P-channel MOSFET and the current sink has an N-channel MOSFET. In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the turn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transients which may turn the device back ON. 8 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325 UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 www.ti.com SLUS492H – JUNE 2001 – REVISED MAY 2013 Parallel Outputs The A and B drivers combine into a single driver by connecting the INA and INB inputs together and the OUTA and OUTB outputs together. Then, a single signal controls the paralleled combination as shown in Figure 4. VDD = 12 V UCC37323 INPUT 1 2 3 4 8 INA GND INB OUTA VDD OUTB 7 6 5 CLOAD 0.1 µF CER 2.2 µF Figure 4. Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325 9 UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 SLUS492H – JUNE 2001 – REVISED MAY 2013 www.ti.com Operational Waveforms and Circuit Layout Figure 5 shows the circuit performance achievable with a single driver (half of the 8-pin IC) driving a 10-nF load. The input pulse width (not shown) is set to 300 ns to show both transitions in the output waveform. Note the linear rise and fall edges of the switching waveforms which is due to the constant output current characteristic of the driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers. Sink and source currents of the driver are dependent upon the VDD value and the output capacitive load. The larger the VDD value, the higher the current capability; also, the larger the capacitive load, the higher the current sink and source capability. Trace resistance and inductance, including wires and cables for testing, slows down the rise and fall times of the outputs; thus reducing the current capabilities of the driver. To achieve higher current results, reduce resistance and inductance on the board as much as possible and increase the capacitive load value in order to swamp out the effect of inductance values. Figure 5. In a power driver operating at high frequency, a significant challenge is to get clean waveforms without much overshoot or undershoot and ringing. The low output impedance of these drivers produces waveforms with high di/dt, which tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout. Connecting the driver IC as close as possible to the leads is advantageous. The driver IC layout has ground on the opposite side of the output, so the ground is connected to the bypass capacitors and the load with copper trace as wide as possible. These connections are also made with a small enclosed loop area to minimize the inductance. 10 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325 UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 www.ti.com SLUS492H – JUNE 2001 – REVISED MAY 2013 VDD Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current is calculated from Equation 1. IOUT = Qg × f where • f is frequency (1) For the best high-speed circuit performance, two VDD bypass capacitors are recommended tp prevent noise problems. The use of surface mount components is highly recommended. A 0.1-μF ceramic capacitor must be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1-μF) with relatively low ESR must be connected in parallel, to help deliver the high current peaks to the load. The parallel combination of capacitors must present a low impedance characteristic for the expected current levels in the driver application. Drive Current and Power Requirements The UCC37323/4/5 family of drivers are capable of delivering 4-A of current to a MOSFET gate for a period of several-hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground which repeats at the operating frequency of the power device. A MOSFET is used in this discussion because it is the most common type of switching device used in high frequency power conversion equipment. References 1 and 2 discuss the current required to drive a power MOSFET and other capacitive-input switching devices. Reference 2 includes information on the previous generation of bipolar IC gate drivers (see References). When a driver IC is tested with a discrete, capacitive load calculating the power that is required from the bias supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 2. E = ½CV2 where • • C is the load capacitor V is the bias voltage feeding the driver (2) There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a power loss given by Equation 3. P = 2 × ½CV2f where • f is the switching frequency (3) This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. An actual example using the conditions of the previous gate drive waveform helps to clarify this. With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss is calculated with Equation 4. P = 10 nF × (12)2 × (300 kHz) = 0.432 W (4) With a 12-V supply, this equates to a current of (see Equation 5): P 0.432 W I= = = 0.036 A V 12 V (5) The actual current measured from the supply is 0.037 A, and is very close to the predicted value. But, the IDD current that is due to the IC internal consumption must be considered. With no load the IC current draw is 0.0027 A. Under this condition the output rise and fall times are faster than with a load, which could lead to an almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However, these small current differences are buried in the high frequency switching spikes, and are beyond the measurement capabilities of a basic lab setup. The measured current with 10-nF load is reasonably close to that expected. Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325 11 UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 SLUS492H – JUNE 2001 – REVISED MAY 2013 www.ti.com The switching load presented by a power MOSFET converts to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when charging a capacitor which is done by using the equivalence Qg = CeffV to provide Equation 6 for power: P = C × V2 × f = Qg × f (6) Equation 6 allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specific bias voltage. 12 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325 UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 www.ti.com SLUS492H – JUNE 2001 – REVISED MAY 2013 THERMAL INFORMATION The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the IC package. In order for a power driver to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC37323/4/5 family of drivers is available in three different packages to cover a range of application requirements. As shown in the POWER DISSIPATION RATINGS table, the SOIC-8 (D) and PDIP-8 (P) packages each have a power rating of around 0.5 W with TA = 70°C. This limit is imposed in conjunction with the power derating factor also given in the table. Note that the power dissipation in our earlier example is 0.432 W with a 10-nF load, 12 VDD, switched at 300 kHz. Thus, only one load of this size can be driven using the D or P package, even if the two onboard drivers are paralleled. The difficulties with heat removal limit the drive available in the older packages. The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means of removing the heat from the semiconductor junction. As illustrated in Reference 3 (see References), the PowerPAD packages offer a lead-frame die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board directly underneath the IC package, reducing the θJC down to 4.7°C/W. Data is presented in Reference 3 to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in Reference 4. This design allows a significant improvement in heat sinking over that which is available in the D or P packages, and is shown to more than double the power capability of the D and P packages. NOTE The PowerPAD is not directly connected to any leads of the package. However, the PowerPad is electrically and thermally connected to the substrate which is the ground of the device. References 1. Power Supply Seminar SEM-1400 Topic 2, Design And Application Guide For High Speed MOSFET Gate Drive Circuits, by Laszlo Balogh, TI Literature Number SLUP133 2. Application Note, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive Circuits, by Bill Andreycak, TI Literature Number SLUA105 3. Technical Brief, PowerPad Thermally Enhanced Package, TI Literature Number SLMA002 4. Application Brief, PowerPAD Made Easy, TI Literature Number SLMA004 Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325 13 UCC27323, UCC27324, UCC27325 UCC37323, UCC37324, UCC37325 SLUS492H – JUNE 2001 – REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Revision G (March 2010) to Revision H Page • Changed DSCHOTTKY diode direction and voltage of zener diode from 5.5 to 4.5 V in Figure 3 ............................................ 8 • Added three paragraphs after first paragraph of Operational Waveforms and Circuit Layout section before Figure 5 ..... 10 14 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) UCC27323D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 27323 UCC27323DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 27323 UCC27323DGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 27323 UCC27323DGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 27323 UCC27323DGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 27323 UCC27323DGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 27323 UCC27323DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 27323 UCC27323DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 27323 UCC27323P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 UCC27323P UCC27323PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 UCC27323P UCC27324D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 27324 UCC27324DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 27324 UCC27324DGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 27324 UCC27324DGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 27324 UCC27324DGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 27324 UCC27324DGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 27324 UCC27324DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) Level-1-260C-UNLIM -40 to 125 27324 CU NIPDAU Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) UCC27324DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 27324 UCC27324P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 UCC27324P UCC27324PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 UCC27324P UCC27325D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 27325 UCC27325DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 27325 UCC27325DGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 27325 UCC27325DGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 27325 UCC27325DGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 27325 UCC27325DGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM -40 to 125 27325 UCC27325DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 27325 UCC27325DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 27325 UCC27325P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 UCC27325P UCC27325PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 UCC27325P UCC37323D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 37323 UCC37323DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 37323 UCC37323DGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM 0 to 70 37323 UCC37323DGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM 0 to 70 37323 UCC37323DGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM 0 to 70 37323 Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) UCC37323DGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM 0 to 70 37323 UCC37323DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 37323 UCC37323DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 37323 UCC37323P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 UCC37323P UCC37323PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 UCC37323P UCC37324D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 37324 UCC37324DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 37324 UCC37324DGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM 0 to 70 37324 UCC37324DGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM 0 to 70 37324 UCC37324DGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM 0 to 70 37324 UCC37324DGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM 0 to 70 37324 UCC37324DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 37324 UCC37324DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 37324 UCC37324P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 UCC37324P UCC37324PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 UCC37324P UCC37325D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 37325 UCC37325DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 37325 UCC37325DGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM 0 to 70 37325 Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) UCC37325DGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM 0 to 70 37325 UCC37325DGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM 0 to 70 37325 UCC37325DGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS CU NIPDAUAG & no Sb/Br) Level-1-260C-UNLIM 0 to 70 37325 UCC37325DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 37325 UCC37325DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 37325 UCC37325P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 UCC37325P UCC37325PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 UCC37325P (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Addendum-Page 4 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC27324 : • Automotive: UCC27324-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 5 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC27323DGNR Package Package Pins Type Drawing MSOPPower PAD SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27323DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27324DGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27324DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27325DGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27325DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC37323DGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC37323DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC37324DGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC37324DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC37325DGNR MSOP- DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant Power PAD UCC37325DR SOIC D 8 2500 330.0 12.4 6.4 12.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC27323DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 UCC27323DR SOIC D 8 2500 340.5 338.1 20.6 UCC27324DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 UCC27324DR SOIC D 8 2500 340.5 338.1 20.6 UCC27325DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 UCC27325DR SOIC D 8 2500 340.5 338.1 20.6 UCC37323DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 UCC37323DR SOIC D 8 2500 340.5 338.1 20.6 UCC37324DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 UCC37324DR SOIC D 8 2500 340.5 338.1 20.6 UCC37325DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 UCC37325DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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