Preliminary W49L102 64K × 16 CMOS 3.3V FLASH MEMORY GENERAL DESCRIPTION The W49L102 is a 1-megabit, 3.3-volt only CMOS flash memory organized as 64K × 16 bits. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49L102 results in fast program/erase operations with extremely low current consumption (compared to other comparable 3.3-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES • Single 3.3-volt operations: Low power consumption − 3.3-volt Read − Active current: 15 mA (typ.) − 3.3-volt Erase − Standby current: 10 µA (typ.) − 3.3-volt Program • • • Automatic program and erase timing with internal VPP generation • End of program or erase detection Fast Program operation: − Word-by-Word programming: 50 µS (max.) • Fast Erase operation: 100 mS (typ.) • Fast Read access time: 55/70/90 nS • Endurance: 1K/10K cycles (typ.) • Twenty-year data retention • Hardware data protection • 8K word Boot Block with Lockout protection − Toggle bit − Data polling • Latched address and data • TTL compatible I/O • JEDEC standard word-wide pinouts • Available packages: 40-pin TSOP and 44-pin PLCC -1- Publication Release Date: June 1999 Revision A1 Preliminary W49L102 PIN CONFIGURATIONS BLOCK DIAGRAM VDD VSS A9 A10 A11 A12 A13 A14 A15 NC WE VDD NC CE DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 40 1 2 39 38 3 4 37 36 5 6 35 34 7 8 9 33 32 40-pin TSOP 10 11 12 13 14 15 16 17 18 19 20 31 30 29 28 27 26 25 24 23 22 21 V D D D / Q Q Q C N N D 13 14 15 E C C D 6 5 4 3 2 / W N E C GND A8 A7 A6 A5 A4 A3 A2 A1 A0 39 A13 8 38 A12 DQ10 9 37 A11 10 WE 44-pin PLCC 36 A10 35 A9 34 GND GND 12 NC 13 33 NC DQ7 14 32 A8 DQ6 15 31 A7 DQ5 16 30 A6 DQ4 17 29 DECODER . (56K Words) BootBlock (8K Words) A15 A5 PIN DESCRIPTION SYMBOL A0−A15 DQ0−DQ15 18 19 20 21 22 23 24 25 26 27 28 D D D D Q Q Q Q 3 2 1 0 DQ15 MAIN MEMORY A0 . . . 1 44 43 42 41 40 DQ11 11 OUTPUT BUFFER A A 1 1 5 4 7 DQ8 CONTROL OE OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 GND DQ12 DQ9 DQ0 CE / N A A O C 0 1 E A A A 2 3 4 Address Inputs Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable VDD Power Supply GND Ground NC -2- PIN NAME No Connection Preliminary W49L102 FUNCTIONAL DESCRIPTION Read Mode The read operation of the W49L102 is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details. Boot Block Operation There is one 8K-word boot block in this device, which can be used to store boot code. It is located in the first 8K words of the memory with the address range from 0000 hex to 1FFF hex. See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block can not be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. Once the boot block programming lockout feature is activated, the chip erase function will only affect the main memory. In order to detect whether the boot block feature is set on the 8K-words block, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 hex". If the output data is "FF hex," the boot block programming lockout feature is activated; if the output data is "FE hex," the lockout feature is inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command sequence (or an alternate single-word command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection. Input Levels While operating with a 3.0V−3.6V power supply, the address inputs and control inputs ( OE, CE and WE ) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to 3.6V. Chip Erase Operation The chip-erase mode can be initiated by a six-word command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed in a fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. If the boot block programming lockout is activated, only the data in the main memory will be erased to FF(hex), and the data in the boot block will not be erased (remains same as before the chip erase operation). The entire memory array (main memory and boot block) will be erased to FF hex. by the chip erase operation if the boot block programming lockout feature is not activated. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle. Main Memory Erase Operation The main memory erase mode can be initiated by a six-word command sequence. After the command loading cycle, the device enters the internal main-memory erase mode, which is automatically timed and will be completed in a fast 100 mS (typical). The host system is not required -3- Publication Release Date: June 1999 Revision A1 Preliminary W49L102 to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle. Program Operation The W49L102 is programmed on a word-by-word basis. Program operation can only change logical data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot block from "0" to "1" is needed before programming. The program operation is initiated by a 4-word command cycle (see Command Codes for Word Programming). The device will interally enter the program operation immediately after the wordprogram command is entered. The internal program timer will automatically time-out (50 µS max. TBP) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle. Hardware Data Protection The integrity of the data stored in the W49L102 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 1.8V typical. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically timeout 10 mS before any write (erase/program) operation. Data Polling (DQ7 & DQ15)- Write Status Detection The W49L102 includes a data polling feature to indicate the end of a program or erase cycle. When the W49L102 is in the internal program or erase cycle, any attempt to read DQ7 or DQ15 of the last word loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 or DQ15 will show the true data. Note that DQ7 or DQ15 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has been completed. Toggle Bit (DQ6 & DQ14)- Write Status Detection In addition to data polling, the W49L102 provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 or DQ14 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code (00DAh). A read from address 0001H outputs the device code (00BFh). The product ID operation can be terminated by a three-word command sequence or an altenate one-word command sequence (see Command Definition table). In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE high, and raising A9 to 12 volts. -4- Preliminary W49L102 TABLE OF OPERATING MODES Operating Mode Selection (VHH = 12V ± 0.5V ) MODE PINS ADDRESS DQ. CE OE WE Read VIL VIL VIH AIN Dout Write VIL VIH VIL AIN Din Standby VIH X X X High Z X VIL X X High Z/DOUT X X VIH X High Z/DOUT X VIH X X High Z VIL VIL VIH A0 = VIL; A1−A15 = VIL; A9 = VHH Manufacturer Code 00DA (Hex) VIL VIL VIH A0 = VIH; A1−A15 = VIL; A9 = VHH Device Code 00BF (Hex) Write Inhibit Output Disable Product ID TABLE OF COMMAND DEFINITION Command No. of 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle Description Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read 1 AIN Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Main Memory Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 30 Word Program 4 5555 AA 2AAA 55 5555 A0 AIN Boot Block Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40 Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit (1) 3 5555 AA 2AAA 55 5555 F0 (1) 1 XXXX F0 Product ID Exit DOUT DIN Note: Address Format: A14−A0 (Hex); Data Format: DQ15−DQ8 (Don't Care); DQ7-DQ0 (Hex) Either one of the two Product ID Exit commands can be used. -5- Publication Release Date: June 1999 Revision A1 Preliminary W49L102 Command Codes for Word Program WORD SEQUENCE ADDRESS DATA 0 Write 5555H AAH 1 Write 2AAAH 55H 2 Write 5555H A0H 3 Write Programmed-Address Programmed-Data Word Program Flow Chart Word Program Command Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555 Load data Din to programmedaddress Pause 50 µS Exit Notes for software program code: Data Format: DQ15−DQ0 (Hex); XX = Don't Care Address Format: A14−A0 (Hex) -6- Preliminary W49L102 Command Codes for Chip Erase BYTE SEQUENCE ADDRESS DATA 1 Write 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 80H 4 Write 5555H AAH 5 Write 2AAAH 55H 6 Write 5555H 10H Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause 1 Sec. Exit Notes for chip erase: Data Format: DQ15-DQ8: Don't Care; DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) -7- Publication Release Date: June 1999 Revision A1 Preliminary W49L102 Command Codes for Main Memory Erase BYTE SEQUENCE ADDRESS 1 Write 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 80H 4 Write 5555H AAH 5 Write 2AAAH 55H 6 Write 5555H 30H Main Memory Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 30 to address 5555 Pause 1 Sec. Exit Notes for chip erase: Data Format: DQ15-DQ8: Don't Care; DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) -8- DATA Preliminary W49L102 Command Codes for Product Identification and Boot Block Lockout Detection BYTE SEQUENCE ALTERNATE PRODUCT (6) IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS DATA SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT (7) ADDRESS DATA 1 Write 5555 AA 5555H AAH 2 Write 2AAA 55 2AAAH 55H 3 Write 5555 90 5555H F0H Pause 20µS Pause 20µS Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Product Identification and Boot Block Lockout Detection Mode (3) Product Identification Exit(7) Load data AA to address 5555 (2) Load data 55 to address 2AAA Read address = 00000 data = DA Load data 90 to address 5555 Read address = 00001 data = BF Pause 10 µ S Read address = 00002 data = FF/FE (2) (4) Load data 55 to address 2AAA Load data F0 to address 5555 Pause 10 µ S (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ15-DQ8 (Don't Care), DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex) (2) A1−A15 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is inactivated and the block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection. -9- Publication Release Date: June 1999 Revision A1 Preliminary W49L102 Command Codes for Boot Block Lockout Enable BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET ADDRESS DATA 1 Write 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 80H 4 Write 5555H AAH 5 Write 2AAAH 55H 6 Write 5555H 40H Pause 1 Sec. Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause 1 Sec. Exit Notes for boot block lockout enable: Data Format: DQ15-DQ8 Don't Care), DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) - 10 - Preliminary W49L102 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +4.6 V 0 to +70 °C -65 to +150 °C D.C. Voltage on Any Pin to Ground Potential except A9 -0.5 to VDD +1.0 V Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +1.0 V -0.5 to 12.5 V Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature Voltage on A9 Pin to Ground Potential Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Operating Characteristics (VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C) PARAMETER SYM. TEST CONDITIONS LIMITS MIN. TYP. Power Supply Current ICC Standby VDD ISB1 MAX. - 15 25 mA - - 1 mA - 10 50 µA Address inputs = VIL/VIH, at f = 5 MHz Current (TTL input) Standby VDD Current CE = OE = VIL, WE = VIH, all I/Os open UNIT CE = VIH, all I/Os open Other inputs = VIL/VIH ISB2 CE = VDD -0.3V, all I/Os open Other inputs = VDD -0.3V/GND (CMOS input) Input Leakage Current ILI VIN = GND to VDD - - 10 µA Output Leakage Current ILO VOUT = GND to VDD - - 10 µA Input Low Voltage VIL - -0.3 - 0.6 V Input High Voltage VIH - 2.0 - VDD +0.5 V Output Low Voltage VOL IOL = 1.6 mA - - 0.45 V Output High Voltage VOH IOH = -0.1 mA 2.4 - - V - 11 - Publication Release Date: June 1999 Revision A1 Preliminary W49L102 Power-up Timing PARAMETER SYMBOL TYPICAL UNIT Power-up to Read Operation TPU. READ 200 Power-up to Write Operation TPU. WRITE 10 µS mS MAX. UNIT 12 6 pf pf CAPACITANCE (VDD = 3.3V, TA = 25° C, f = 1 MHz) PARAMETER SYMBOL I/O Pin Capacitance Input Capacitance CONDITIONS CI/O CIN VI/O = 0V VIN = 0V AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0.4V/2.4V < 5 nS 1.5V/1.5V 1 TTL Gate and CL = 30 pF for 55/70 nS CL = 100 pF for 90 nS AC Test Load and Waveform +3.3V 1.8K Ω D OUT 30 pF for 55/70 nS 100 pF for 90 nS (Including Jig and Scope) 1.3K Ω Input Output 2.4V 1.5V 1.5V 0.4V Test Point - 12 - Test Point Preliminary W49L102 AC Characteristics, continued Read Cycle Timing Parameters (VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C) PARAMETER SYM. W49L102-55 W49L102-70 W49L102-90 MIN. MAX. MIN. MAX. MIN. MAX. UNIT Read Cycle Time TRC 55 - 70 - 90 - nS Chip Enable Access Time TCE - 55 - 70 - 90 nS Address Access Time TAA - 55 - 70 - 90 nS Output Enable Access Time TOE - 30 - 35 - 40 nS CE Low to Active Output TCLZ 0 - 0 - 0 - nS OE Low to Active Output TOLZ 0 - 0 - 0 - nS CE High to High-Z Output TCHZ - 25 - 30 - 30 nS OE High to High-Z Output TOHZ - 25 - 30 - 30 nS Output Hold from Address Change TOH 0 - 0 - 0 - nS Write Cycle Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT Address Setup Time TAS 10 - - nS Address Hold Time TAH 100 - - nS WE and CE Setup Time TCS 0 - - nS WE and CE Hold Time TCH 0 - - nS OE High Setup Time TOES 0 - - nS OE High Hold Time TOEH 0 - - nS CE Pulse Width TCP 200 - - nS WE Pulse Width TWP 200 - - nS WE High Width TWPH 200 - - nS Data Setup Time TDS 100 - - nS Data Hold Time TDH 10 - - nS Word Programming Time TBP - 30 50 µS Erase Cycle Time TEC - 0.1 1 Sec. Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL. - 13 - Publication Release Date: June 1999 Revision A1 Preliminary W49L102 AC Characteristics, continued Data Polling and Toggle Bit Timing Parameters PARAMETER SYM. W49L102-55 W49L102-70 W49L102-90 MIN. MAX. MIN. MAX. MIN. MAX. UNIT to Data Polling Output Delay TOEP - 30 - 35 - 40 nS CE to Data Polling Output Delay TCEP - 55 - 70 - 90 nS OE to Toggle Bit Output Delay TOET - 30 - 35 - 40 nS to Toggle Bit Output Delay TCET - 55 - 70 - 90 nS TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A15-0 T CE TOE OE V T TOLZ WE TCLZ DQ15-0 TOH TCHZ High-Z High-Z Data Valid Data Valid TAA - 14 - Preliminary W49L102 Timing Waveforms, continued WE Controlled Command Write Cycle Timing Diagram TAS TAH Address A15-0 CE TCS TCH TOES T OEH OE TWP WE TWPH TDS DQ15-0 Data Valid TDH CE Controlled Command Write Cycle Timing Diagram TAS TAH Address A15-0 TCPH TCP CE TOES TOEH OE WE TDS DQ15-0 High Z Data Valid TDH - 15 - Publication Release Date: June 1999 Revision A1 Preliminary W49L102 Timing Waveforms, continued Program Cycle Timing Diagram Word Program Cycle Address A15-0 2AAA 5555 55 AA DQ15-0 5555 Address A0 Data-In CE OE T WPH TBP T WP WE Word 1 Word 0 Word 2 Word 3 Internal Write Start DATA Polling Timing Diagram Address A15-0 An An An An WE TCEP CE TOEH TOES OE TOEP DQ7/DQ15 X X X TBP or TEC - 16 - X Preliminary W49L102 Timing Waveforms, continued Toggle Bit Timing Diagram Address A15-0 WE CE TOES TOEH OE DQ6/DQ14 TBP or TEC Boot Block Lockout Enable Timing Diagram Six-word code for Boot Block Lockout Feature Enable Address A15-0 DQ15-0 5555 2AAA XXAA XX55 5555 5555 XX80 XXAA 2AAA XX55 5555 XX40 CE OE TWP TWC WE TWPH SW0 SW1 SW23 SW3 - 17 - SW4 SW5 Publication Release Date: June 1999 Revision A1 Preliminary W49L102 Timing Waveforms, continued Chip Erase Timing Diagram Six-word code for 3.3V-only software chip erase Address A15-0 DQ15-0 5555 2AAA XX55 XXAA 5555 5555 XX80 XXAA 2AAA XX55 5555 XX10 CE OE TWP TEC WE TWPH SW0 SW1 SW2 SW3 SW4 SW5 Internal Erase starts Main Memory Erase Timing Diagram Six-word code for 3.3V-only software Main Memory Erase Address A15-0 DQ15-0 5555 2AAA XXAA XX55 5555 5555 XX80 XXAA 2AAA XX55 5555 XX30 CE OE TWP TEC WE TWPH SW0 SW1 SW2 - 18 - SW3 SW4 SW5 Internal Erase starts Preliminary W49L102 ORDERING INFORMATION PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. STANDBY VDD CURRENT MAX. (mA) (µA) PACKAGE CYCLE W49L102Q-55 55 25 50 (CMOS) 40-pin TSOP (10 mm × 14 mm) 1K W49L102Q-70 70 25 50 (CMOS) 40-pin TSOP (10 mm × 14 mm) 1K W49L102Q-90 90 25 50 (CMOS) 40-pin TSOP (10 mm × 14 mm) 1K W49L102P-55 55 25 50 (CMOS) 44-pin PLCC 1K W49L102P-70 70 25 50 (CMOS) 44-pin PLCC 1K W49L102P-90 90 25 50 (CMOS) 44-pin PLCC 1K W49L102Q-55B 55 25 50 (CMOS) 40-pin TSOP (10 mm × 14 mm) 10K W49L102Q-70B 70 25 50 (CMOS) 40-pin TSOP (10 mm × 14 mm) 10K W49L102Q-90B 90 25 50 (CMOS) 40-pin TSOP (10 mm × 14 mm) 10K W49L102P-55B 55 25 50 (CMOS) 44-pin PLCC 10K W49L102P-70B 70 25 50 (CMOS) 44-pin PLCC 10K W49L102P-90B 90 25 50 (CMOS) 44-pin PLCC 10K Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 19 - Publication Release Date: June 1999 Revision A1 Preliminary W49L102 PACKAGE DIMENSIONS 44-pin PLCC HD D 6 1 44 Dimension in Inches 40 Symbol 7 A A1 A2 b b c D E e G GE HD HE L y 39 E 17 GE E 29 18 28 A θ e Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.020 0.155 3.68 3.81 3.94 0.022 0.41 0.46 0.56 0.026 0.028 0.008 0.010 0.658 16.46 16.59 16.71 16.46 0.653 16.71 1.27 BSC 0.590 0.610 16.00 14.99 0.610 0.700 17.27 17.53 17.78 17.27 0.690 17.78 0.090 0.100 0.10 0.004 A A1 b1 y GD 40-pin TSOP (10 mm × 14 mm) HD Dimension in Inches Symbol D c A A1 A2 e1 M E 0.10(0.004) b A θ A2 A1 L Y L1 b c D E HD e L L1 Y θ Min. Nom. Max. Dimension in mm Min. 0.002 Max. 1.20 0.006 0.05 0.15 0.037 0.039 0.041 0.95 1.00 0.007 0.009 0.011 0.17 0.22 0.27 0.004 0.006 0.008 0.10 0.15 0.20 12.30 12.40 12.50 0.484 0.488 0.492 0.390 0.394 0.543 0.551 0.559 13.80 0.398 9.90 0.020 0.020 0.024 0.50 0.031 0.000 0 3 1.05 10 10.10 14.00 14.20 0.50 0.028 0.60 0.70 0.8 0.004 0.00 5 0 Controlling dimension: Millimeters - 20 - Nom. 0.047 0.10 3 5 Preliminary W49L102 VERSION HISTORY VERSION DATE PAGE A1 Jun. 1999 - Headquarters DESCRIPTION Renamed from W29N102C Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 21 - Publication Release Date: June 1999 Revision A1